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Abstract The idea of sources other than the test-takers’ knowledge leading to different results on high-stakes tests was the motif based on which the present investigation was initiated on the probable sources of unreliability of a test. For this purpose, the researchers went through a thorough literature review with the aim to identify the issues to be counted as sources of unreliability of a high-stakes test, i.e., the MA University Entrance Exam of English (UEEE) in Iran. First, 17 MA UEEE test-takers were asked to take part in a semi-structured interview to find out their ideas about such sources. The outcome of the thematic coding of the information from the literature and interviews was a 57-item Likert scale questionnaire which was reviewed by three assessment experts, revised accordingly, piloted with 57 MA UEEE test-takers, and revised again with 55 items remaining. The revised questionnaire was administered to 312 MA UEEE test-takers in Iran, and its reliability and construct validity were checked through Cronbach alpha (.89) and exploratory factor analysis, respectively. After checking its reliability and construct validity, 46 items remained and loaded on four factors which were named as the effect of test-takers (16 items), structure of the test and external concerns (13 items), administration conditions of the test (13 items), and role of proctors (4 items). The results of this study might familiarize test developers, test administrators, teachers, and test-takers with issues they should be aware of in developing or preparing for a high-stakes test like the MA UEEE.

The idea of sources other than the test-takers' knowledge leading to different results on high-stakes tests was the motif based on which the present investigation was initiated on the probable sources of unreliability of a test. For this purpose, the researchers went through a thorough literature review with the aim to identify the issues to be counted as sources of unreliability of a high-stakes test, i.e., the MA University Entrance Exam of English (UEEE) in Iran. First, 17 MA UEEE test-takers were asked to take part in a semi-structured interview to find out their ideas about such sources. The outcome of the thematic coding of the information from the literature and interviews was a 57-item Likert scale questionnaire which was reviewed by three assessment experts, revised accordingly, piloted with 57 MA UEEE test-takers, and revised again with 55 items remaining. The revised questionnaire was administered to 312 MA UEEE test-takers in Iran, and its reliability and construct validity were checked through Cronbach alpha (.89) and exploratory factor analysis, respectively. After checking its reliability and construct validity, 46 items remained and loaded on four factors which were named as the effect of test-takers (16 items), structure of the test and external concerns (13 items), administration conditions of the test (13 items), and role of proctors (4 items). The results of this study might familiarize test developers, test administrators, teachers, and test-takers with issues they should be aware of in developing or preparing for a high-stakes test like the MA UEEE. [ABSTRACT FROM AUTHOR]

Integrated power ICs acting as smart power switches for automotive or industrial applications are often subjected to active thermal cycling. Consequently, they undergo significant self-heating and are prone to various failure mechanisms related to the electro-thermo-mechanical phenomena that take place in the device metallization. In this article a test structure consisting of a lateral DMOS transistor equipped with several integrated sensors is proposed for metallization fatigue assessment. The design of the test structure is presented in detail, alongside with design considerations drawn from the literature and from simulation results. The testing procedure is then described, and experimental results are discussed. The experimental data provided by the integrated sensors correlated with the electro-thermal simulation results indicate the emergence of a failure mechanism and this is later confirmed by failure analysis. Conclusions are further drawn regarding the feasibility of using the proposed integrated sensors for monitoring defects in power ICs. [ABSTRACT FROM AUTHOR]

We propose and demonstrate a drop-in test structure to visualize and measure the residual stress in the conformally deposited film. For reliable device process of microsystems (such as 3-D MEMS), the residual stress must be controlled through quantitative evaluation at each deposition step. A small drop-in test structure placed near the main sample is suitable for monitoring film characteristics. We developed a free-standing rotating beam stress sensor as the drop-in test structure to visualize and measure the residual stress in conformally deposited films with no additional processes. The dimensions of the developed drop-in test structure chips were 5 mm × 10 mm. For a demonstration, supercritical fluid deposition (SCFD) was performed over the test structure chips under a couple of conditions. The residual stresses in SCFD films were successfully extracted by equation-based analysis. [ABSTRACT FROM AUTHOR]

Etch selectivity between layers is an important parameter in the fabrication of microelectronics and microsystems. This is particularly true in the case of isotropic gas/vapour etching methods used to release free standing structures through the selective etching of sacrificial layers. Commonly used structural materials have been reported to be largely inert when exposed to a given vapour etchant, indicating high selectivity when measured against typical sacrificial layers. However, there is growing evidence that these structural layers are actually etched at an enhanced rate if they are located in the proximity of the sacrificial layer being removed. Hence, removal rates given in the literature, which have resulted from measurements of layers that have been etched in isolation, can no longer be trusted to characterize critical etch processes in device fabrication. In this paper, a test structure is reported that enables a far more appropriate determination of the etch selectivity between sacrificial and structural materials. The method is demonstrated with the two most common vapour etch processes. Firstly, the XeF2 vapour etch of a polysilicon sacrificial layer located above a silicon nitride structural layer, and secondly, the HF vapour etch of silicon dioxide placed above a silicon nitride structural layer. Both test structure datasets are presented. The polysilicon and silicon nitride layers, etched with XeF2 show a selectivity of 5:4. The silicon dioxide and silicon nitride layers etched with HF, show a selectivity of 6:1 to 8:1. [ABSTRACT FROM AUTHOR]

Foraminiferal wall micro/ultra-structures of Recent and well-preserved Jurassic (Bathonian) foraminifers of distinct foraminiferal high-rank taxonomic groups, Globothalamea (Rotaliida, Robertinida, and Textulariida), Miliolida, Spirillinata and Lagenata, are presented. Both calcite-cemented agglutinated and entirely calcareous foraminiferal walls have been investigated. Original test ultra-structures of Jurassic foraminifers are given for the first time. “Monocrystalline” wall-type which characterizes the class Spirillinata is documented in high resolution imaging. Globothalamea, Lagenata, porcelaneous representatives of Tubothalamea and Spirillinata display four different major types of wall-structure which may be related to distinct calcification processes. It confirms that these distinct molecular groups evolved separately, probably from single-chambered monothalamids, and independently developed unique wall types. Studied Jurassic simple bilocular taxa, characterized by undivided spiralling or irregular tubes, are composed of miliolid-type needle-shaped crystallites. In turn, spirillinid “monocrystalline” test structure has only been recorded within more complex, multilocular taxa possessing secondary subdivided chambers: Jurassic Paalzowella and Recent Patellina. More integrated molecular and structural studies are needed in order to better understand taxonomic position and phylogeny of tubular taxa. Unilocular and multichambered Lagenata (Lagenidae and Nodosariidae, respectively) show identical test micro and ultra-structure which suggests their close phylogenetic relationship and questions most recent theories of their separate evolutionary history and origins. A comparison of Recent, Cretaceous, and Jurassic foraminiferal test structure indicates that test characteristics at particular higher-rank taxonomic levels change very little over time and thus can serve as good proxies for the taxonomic designations of fossil taxa, when their state of preservation is appropriate for microstructural observations.

Vertical PNP bipolar transistor test structures were fabricated and measured, attempting to electrically obtain information on carrier lifetime in the voltage-supporting base region of Insulated Gate Bipolar Transistors (IGBTs). Owing to the structural similarity, the test structures and functional IGBTs can be integrated on the same wafers, making it possible to directly correlate lifetime data and IGBT characteristics. To solve a problem of leaky backside PN junction, common base current gain of the test devices was measured without applying a reverse bias between the collector and base terminals, which suppressed the leakage to an acceptable level. A simple analytical formula to convert the current gain to hole lifetime in the N-type base region was proposed and used, that takes into account the existence of a commonly used N-buffer layer adjacent to the backside P-collector layer. The validity of the formula was confirmed using TCAD simulations. This method was applied to IGBT wafers with two different wafer thicknesses (i.e., base lengths): $120~{{\mu }}\text{m}$ and $360~{{\mu }}\text{m}$. Consistent lifetime values extracted in spite of the largely different thicknesses supports the validity of the proposed lifetime estimation method. [ABSTRACT FROM AUTHOR]

Methods for characterization of MOSFET gate overlap capacitances are briefly discussed. Considerations of their shortcomings due to the neglected shortening and/or narrowing of the MOSFET channel in relation to its drawn size have led to development of a new method for a simultaneous extraction of the gate overlap capacitances and of the channel width and length variations. The approach is presented and illustrated using experimental data obtained by C-V measurements of the MOSFETs in a CMOS test structure. The characterization results are compared with the parameters obtained via I-V measurements of the corresponding devices. [ABSTRACT FROM AUTHOR]

This article deals with a study of radiation-induced leakages between n-regions of various types using test structures fabricated according to the 0.18-µm CMOS technology. It is shown that, depending on the radiation exposure dose, the leakages between the n+-regions and the n-well may exceed the leakages between the n+-regions by 3–9 times, which should be taken into consideration when developing radiation resistant VSHICs. [ABSTRACT FROM AUTHOR]

Foraminiferal wall micro/ultra-structures of Recent and well-preserved Jurassic (Bathonian) foraminifers of distinct foraminiferal high-rank taxonomic groups, Globothalamea (Rotaliida, Robertinida, and Textulariida), Miliolida, Spirillinata and Lagenata, are presented. Both calcite-cemented agglutinated and entirely calcareous foraminiferal walls have been investigated. Original test ultra-structures of Jurassic foraminifers are given for the first time. "Monocrystalline" wall-type which characterizes the class Spirillinata is documented in high resolution imaging. Globothalamea, Lagenata, porcelaneous representatives of Tubothalamea and Spirillinata display four different major types of wall-structure which may be related to distinct calcification processes. It confirms that these distinct molecular groups evolved separately, probably from single-chambered monothalamids, and independently developed unique wall types. Studied Jurassic simple bilocular taxa, characterized by undivided spiralling or irregular tubes, are composed of miliolid-type needle-shaped crystallites. In turn, spirillinid "monocrystalline" test structure has only been recorded within more complex, multilocular taxa possessing secondary subdivided chambers: Jurassic Paalzowella and Recent Patellina. More integrated molecular and structural studies are needed in order to better understand taxonomic position and phylogeny of tubular taxa. Unilocular and multichambered Lagenata (Lagenidae and Nodosariidae, respectively) show identical test micro and ultra-structure which suggests their close phylogenetic relationship and questions most recent theories of their separate evolutionary history and origins. A comparison of Recent, Cretaceous, and Jurassic foraminiferal test structure indicates that test characteristics at particular higher-rank taxonomic levels change very little over time and thus can serve as good proxies for the taxonomic designations of fossil taxa, when their state of preservation is appropriate for microstructural observations. [ABSTRACT FROM AUTHOR]

The ultra-low k dielectrics have been widely used as semiconductor technology steps into 45 nm, 28 nm, and more advanced nodes. Combined with the rapid shrinks of critical dimensions, the ultra-low k dielectrics face challenges to retain the benefits of interconnect scaling both on their manufacturability and reliability performances. In this paper, abnormal failure phenomena were investigated on 28 nm ILD (Intra Level Dielectric) and IMD (Inter Metal Dielectric) qualifications and 40 nm mass production. A new failure mechanism of metal 1 to poly (M1-to-poly) leaky path was proposed based on theoretical investigations and experiments. Based on our newly proposed dielectric breakdown mechanism, a series of innovative test structures were designed for early detections and evaluations of reliability performances. These newly designed test structures have been proven to be useful due to better representing actual using profiles, more precise reliability evaluations, and more effective monitors on process variations at mass production. [ABSTRACT FROM AUTHOR]

This paper presents a debut of a physical-model-based (interconnect) metal charging design rule methodology. The methodology promises charging safe for chip transistors with a three-boundary-pinning calibration strategy at the highest, middle, and lowest metal layer. The methodology is demonstrated with a full set of interconnect charging design rules generated for 60-Å gate oxide transistors with gates either unprotected or fully protected. In contrast with the experiment-based methodology, the physical-model-based methodology inherits the advantage of consuming far less test-chip layout space and rule generation time. The methodology would provide benefit in a technology-development environment with its agility in deployment and rule generation. It also makes possible for realizing application-specific charging design rules based on specific emphasis on process or device design. The methodology is fundamental due to the fundamental transistor charging physical models incorporated. It can be implemented universally into different process technologies, such as planar and FinFet-based ones with traditional or HKMG gate oxides of different thickness. The methodology would produce metal charging design rules for technologies developed at advanced process nodes, such as the 7-nm technology or beyond so long as the transistor models, gate oxide characterization data, and backend-process plasma-loading characteristics of the technology are provided. [ABSTRACT FROM AUTHOR]

The data stored in a static random access memory (SRAM) immediately after power-up is of practical interest for some applications, such as SRAM physical unclonable functions. In this paper, measurements of SRAM cell power-up state (i.e., whether the cell is storing 0 or 1 after the power supply is turned on) using an addressable cell array test structure are reported. The test structure provides direct access to individual transistor characteristics of many SRAM cells, which would facilitate the characterization of SRAM power-up behavior. Methods and considerations necessary for reliable and stable power-up state characterization using the test structure will be discussed and demonstrated. [ABSTRACT FROM PUBLISHER]

Physical-model guided design on transistor test structures aiming for extracting backend metal charging design rules is demonstrated for the first time. Based on experimental data from a six-metal-layer technology, the demonstration shows such design methodology to be feasible. The methodology enables adequate design for the test structures from which a complete set of metal charging design rules can be extracted for a given process technology. This paper concludes that a significant reduction in the number of the required test structures and accordingly a large saving for test chip layout space during process development can be realized with the new design methodology. The number of the design-rule-extraction test structures could be reduced by a half for a six-metal-layer technology and by 77% for a thirteen-metal-layer layer technology, with a minimum number as low as four per transistor type, gate oxide thickness, and gate protection option if such methodology is adopted. The advantage inherited in the new methodology is delineated. [ABSTRACT FROM PUBLISHER]

This paper reports a versatile thermophysical test structure to measure all material properties contributing to the in-plane thermoelectric figure of merit $$ZT=S^2T\kappa ^{-1} \rho ^{-1}$$ from a single thin film sample of only about 0.5 mm $$^2$$ . These properties are the Seebeck coefficient S of the sample against aluminum (Al), its thermal conductivity $$\kappa$$ , and its resistivity $$\rho$$ . The thermal membrane-based test structure is produced using standard thin film deposition and structuring processes followed by silicon micromachining. It can be used to characterize thin films deposited at high temperature, such as doped polycrystalline silicon (poly-Si), as well as films deposited at low temperature, e.g., sputtered metals. We present the measurement of all components of the ZT of low-pressure, chemical vapor-deposited n- and p-doped poly-Si thin films in the temperature range from 300 K to 380 K. Values of 1.46 × 10 and 0.95 × 10 were found at room temperature (RT) for the ZT of n- and p-doped poly-Si films, respectively. Furthermore, the test structure was used to extract $$\rho$$ and $$\kappa$$ of a sputtered aluminum film in the same temperature range. The respective RT values are 48.7 × 10 $$\Omega {\hbox{m}}$$ and 154 W m K. [ABSTRACT FROM AUTHOR]