Extraction of small signal equivalent circuit for de-embedding of 3D vertical nanowire transistor

International audience; In this paper, we present an improved methodology to extract the small signal electrical equivalent circuit of the parasitic elements using RF test-structures for a 3D vertical nanowire transistor technology. The methodology is based on the extraction of parasitic elements from a virtual open structure constructed using electromagnatic simulation and calibrated against on-wafer S-parameter measurements up to 40 GHz. The electrical equivalent circuit of the passive device was then used for deembedding of the transistor S-parameters for extraction of intrinsic small signal parameters such as the gate capacitances.