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Wet etching of Silicon nitride (Si3N4) by phosphoric acid (H3PO4) is one of the key steps in the semiconductor fabrication process, especially for three‐dimensional integrated circuits (ICs). Unfortunately, few systematic studies of phosphoric acid etching of Silicon nitride are available. Summarizing how various factors affect etching and determining the reaction mechanism behind the etching process will help further optimize the etching process. In this work, how the boiling point of hydrous phosphoric acid solutions depends on phosphoric acid concentration is firstly investigated. Next, the etching of over 100 samples of Silicon nitride by H3PO4 at different concentrations and temperatures is systematically studied. The results show that the etching rate increases nearly linearly in both temperature and H3PO4 concentration, while temperature play more important role as compared to concentration. For each concentration, the reaction rate is maximal at the boiling point of the hydrous H3PO4 solution. Moreover, the etching rate of 85 wt % phosphoric acid is analyzed using the Arrhenius equation, yielding an apparent activation energy Ea=57.28 KJ/mol. Finally, a mechanism of Silicon nitride etching in phosphoric acid is proposed which explains the prior studies well. This work contributes to precisely control semiconductor processing for three‐dimensional ICs. [ABSTRACT FROM AUTHOR]

In this study, the microstructural evolution of Ag films with different amounts of (111)-oriented grains and coincident site lattice Σ3 (CSL-Σ3) twin boundaries after low-temperature direct bonding was demonstrated. The highly (111)-oriented surface grains provided the rapid surface diffusion paths and the special twin boundaries contributed to structural stability of the Ag films during bonding. Combining both, perfect bonding can be achieved at a low temperature of 150 °C for 60 min in the bonding of Ag films with 99.4% (111) grains. Owing to the low recrystallization temperature, bonding interfaces with only a few small voids were observed after bonding at 250 °C for 30 min. Annealing twins grew across the bonding interface and extended to the other side of the Ag films, implying a strong bonding strength. Though increasing the bonding temperature and period could help to achieve a bonding interface with the least voids formed, it was suggested that increasing the amount of (111) grains on the Ag film bonding surfaces is the key point to achieved perfect bonding at temperatures lower than 250 °C. This would provide great potential for Ag as a suitable material for applications in three-dimensional integrated circuit (3D-IC) interconnections. [ABSTRACT FROM AUTHOR]

Due to the increasing speed of high-speed trains, the grounding system faces new challenges. When the relative motion between the train and the track occurs, the phenomenon of ground backflow will be intensified, resulting in the rise of train body potential, the abnormity or even damage of bearing and ground carbon brush, insulation joint, on-board sensors and other problems. In view of the existing problems of grounding reflux and train body potential of high-speed trains and the failure of twodimensional model of high-speed train grounding system to simulate and analyze the potential of the left and right sides of the same axle based on radial parameters, it is necessary to conduct a more perfect three-dimensional modeling of the integrated grounding system of high-speed trains. In order to suppress the grounding current and reduce the potential of the vehicle body, optimized analysis of the grounding mode and grounding parameters of the grounding system is conducted. In this paper, based on the measured data and theoretical analysis of the impedance and inductance parameters of the train body as well as the actual size parameters of the train body by the RCL tester, the three-dimensional circuit model of the integrated grounding system of the high-speed train is completed respectively from the aspects of traction transformer, overhead contact line, on-board transformer of high-speed train, high-voltage cable and train body under the premise of fully considering all the influencing factors. At the same time, combined with the dynamic grounding reflux test of the train passing under the on-line condition and the static overvoltage test of the high-speed train raising the pantograph and closing the VCB, the simulation results are compared with the measured results to verify the reliability of the three-dimensional model. Finally, based on the threedimensional simulation model, the radial parameters of the docking system and the three-dimensional distribution of the protection grounding and working grounding are optimized. After optimization, the ground current flowing through the protection grounding of the train is reduced to different degrees, and the distribution becomes more uniform. Meanwhile, the potential of the train body is maintained within the safety limit. [ABSTRACT FROM AUTHOR]

High-performance three-dimensional integrated circuits (3D ICs) are now severely constrained by the thermal issue resulting from the high-power density and limited thermal conductivity among vertically stacked chips. The power distribution networks (PDNs) in 3D ICs are composed of good thermal conductors, but several existing methods are unable to demonstrate their heat dissipation effect successfully, and the thermal models of 3D ICs currently used are either incomplete or have significant errors. In this paper, the Adaptive Unit Difference Iterative (AUDI) method is proposed to establish the equivalent thermal model which can characterize the temperature distribution of 3D ICs accurately. Compared with the simulation results from the Finite Element Method (FEM) tool, the proposed model improves the computational efficiency greatly, and the error in temperature responses is within 3%. The model is used to analyze the effect of 3D PDNs parameters on temperature characteristics and the priority of temperature optimization is indicated, which is of significance for the thermal design. [ABSTRACT FROM AUTHOR]

In this study, we developed a shallow defect layer formation process using moderate-pressure H2 plasma at 3.3 kPa for an extrinsic gettering layer of ultra-thin Si chips aimed at three-dimensional integrated circuits. This process can be conducted in the presence of trivial amounts of air impurities (∼0.01 vol. %), thereby avoiding the use of high-vacuum equipment. We investigated the dependence of defect formation behavior on various processing parameters such as H2 flow rate, processing time, substrate temperature, and input power. It was determined that the absence of H2 gas flow was favorable for the defect layer formation because Si etching by hydrogen atoms was suppressed. A low Si temperature and high input power are desirable for a high defect density in the shallow surface region of the extrinsic gettering layer. When pulse-modulated plasma irradiation was attempted, the defect layer that formed became thinner and had a higher defect density than that obtained by continuous plasma, demonstrating good Cu gettering performance. Without using harmless chemicals, or high-cost equipment, a shallow gettering layer can be formed using inexpensive H2 gas. [ABSTRACT FROM AUTHOR]

As demand for smaller, quicker, and more powerful devices rises, Moore's law is strictly followed. The industry has worked hard to make little devices that boost productivity. The goal is to optimize device density. Scientists are reducing connection delays to improve circuit performance. This helped them understand three-dimensional integrated circuit (3D IC) concepts, which stack active devices and create vertical connections to diminish latency and lower interconnects. Electrical involvement is a big worry with 3D integrates circuits. Researchers have developed and tested through silicon via (TSV) and substrates to decrease electrical wave involvement. This study illustrates a novel noise coupling reduction method using several electrical involvement models. A 22% drop in electrical involvement from wave-carrying to victim TSVs introduces this new paradigm and improves system performance even at higher THz frequencies. [ABSTRACT FROM AUTHOR]

For decades, Moore's Law has been approaching its limits, posing a huge challenge for further downsizing to nanometer dimensions. A promising avenue to replace Moore's Law lies in three-dimensional integrated circuits, where Cu–Cu bonding plays a critical role. However, the atomic diffusion rate is notably low at temperatures below 300 °C, resulting in a distinct weak bonding interface, which leads to reliability issues. In this study, a quenching treatment of the Cu film surface was investigated. During the quenching treatment, strain energy was induced due to the variation in thermal expansion coefficients between the Si substrate and the Cu film, resulting in a wrinkled surface morphology on the Cu film. Grain growth was observed at the Cu–Cu bonding interface following bonding at 300 °C for 2 and 4 h. Remarkably, these procedures effectively eliminated the bonding interface. [ABSTRACT FROM AUTHOR]

X-ray nanotomography is a powerful tool for the characterization of nanoscale materials and structures, but it is difficult to implement due to the competing requirements of X-ray flux and spot size. Due to this constraint, state-of-the-art nanotomography is predominantly performed at large synchrotron facilities. We present a laboratory-scale nanotomography instrument that achieves nanoscale spatial resolution while addressing the limitations of conventional tomography tools. The instrument combines the electron beam of a scanning electron microscope (SEM) with the precise, broadband X-ray detection of a superconducting transition-edge sensor (TES) microcalorimeter. The electron beam generates a highly focused X-ray spot on a metal target held micrometers away from the sample of interest, while the TES spectrometer isolates target photons with a high signal-to-noise ratio. This combination of a focused X-ray spot, energy-resolved X-ray detection, and unique system geometry enables nanoscale, element-specific X-ray imaging in a compact footprint. The proof of concept for this approach to X-ray nanotomography is demonstrated by imaging 160 nm features in three dimensions in six layers of a Cu-SiO2 integrated circuit, and a path toward finer resolution and enhanced imaging capabilities is discussed. [ABSTRACT FROM AUTHOR]

For decades, Moore's Law has neared its limits, posing significant challenges to further scaling it down. A promising avenue for extending Moore's Law lies in three-dimensional integrated circuits (3D ICs), wherein multiple interconnected device layers are vertically bonded using Cu–Cu bonding. The primary bonding mechanism involves Cu solid diffusion bonding. However, the atomic diffusion rate is notably low at temperatures below 300 °C, maintaining a clear and distinct weak bonding interface, which, in turn, gives rise to reliability issues. In this study, a new method of surface modification using epoxy resin to form fine grains on a nanotwinned Cu film was proposed. When bonded at 250 °C, the interfacial grains grew significantly into both sides of the Cu film. When bonded at 300 °C, the interfacial grains extended extensively, eventually eliminating the original bonding interface. [ABSTRACT FROM AUTHOR]

Three-dimensional integrated circuits can significantly mitigate the challenges posed by shrinking feature sizes and enable heterogeneous integration. This paper focuses on the 3D floorplanning problem. We formulate it as a multi-objective optimization issue and employ multi-objective simulated annealing to simultaneously optimize area, wirelength and number of vias. During the optimization process, neighboring solutions are explored in the design space through inter-layer or intra-layer perturbations, and decision criteria for the exploration process are formulated based on the dominance relationship of solutions. Test results on the GSRC benchmark demonstrate that our approach delivers superior performance in optimizing area and wirelength. Compared to 2D floorplanning, our method reduces the area by approximately 49% and the wirelength by 21%. Compared to other similar 3D floorplanning methods, we raise the success rate in satisfying the fixed-outline constraint to 100% and improve the wirelength by 3%. The multi-objective simulated annealing method proposed in this paper can effectively address the 3D floorplanning problem. [ABSTRACT FROM AUTHOR]

In soft electronics, anisotropic conductive adhesive films (ACFs) are the trending interconnecting approach due to their substantial softness and superior bondability to flexible substrates. However, low bonding pressure (≤1 MPa) and fine-pitch interconnections of ACFs become challenging while being extended in advanced device developments such as wafer-level packaging and three-dimensional multi-layer integrated circuit board assembly. To overcome these difficulties, we studied two types of ACFs with distinct conductive filler sizes (ACF-1: ~20 μm and ACF-2: ~5 μm). We demonstrated a low-pressure thermo-compression bonding technique and investigated the size effect of conductive particles on ACF's mechanical properties in a customized testing device, which consists of flexible printing circuits and Flex on Flex assemblies. A consistency of low interconnection resistance (<1 Ω) after mechanical stress (cycling bending test up to 600 cycles) verifies the assembly's outstanding electrical reliability and mechanical stability and thus validates the great effectiveness of the ACF bonding technique. Additionally, in numerical studies using the finite element method, we developed a generic model to disclose the size effect of Au/Ni-coated polymer fillers in ACF on device reliability under mechanical stress. For the first time, we confirmed that ACFs with smaller filler particles are more prone to coating fracture, leading to deteriorated electrical interconnections, and are more likely to peel off from substrate electrode pads resulting in electrical faults. This study provides guides for ACF design and manufacturing and would facilitate the advancement of soft wearable electronic devices. [ABSTRACT FROM AUTHOR]

Ni–Cu under-bump metallisation (UBM) can reduce stress and improve wetting ability in technology for electronic packaging technology advances with three-dimensional integrated circuit (3D IC) devices. The bond between the Sn-based solder and Ni–Cu UBM is affected by the formation of intermetallic compounds (IMCs), specifically Ni3Sn4 and (Ni,Cu)3Sn4. This paper investigates the mechanical properties of IMCs, which are critical in assessing the longevity of solder joints. First-principles calculations were carried out to investigate the phase stability, mechanical properties and electronic structures of Ni3Sn4, Ni2.5Cu0.5Sn4, Ni2.0Cu1.0Sn4, and Ni1.5Cu1.5Sn4 IMCs. The calculated formation enthalpies show that the doping of Cu atoms leads to a decrease in the stability of the phases and a reduction in the mechanical properties of the Ni3Sn4 crystal structure. As the concentration of Cu atoms in the Ni3Sn4 cells increases, the bulk modulus values of (Ni,Cu)3Sn4 formed with different compositions decrease from 107.78 GPa to 87.84 GPa, the shear modulus decreases from 56.64 GPa to 45.08 GPa, and the elastic modulus decreases from 144.59 GPa to 115.48 GPa, indicating that the doping of Cu atoms into the Ni3Sn4 cells may adversely affect their mechanical properties and increase the possibility of microcracking at the interface during actual service. The anisotropy of (Ni,Cu)3Sn4 is more significant than that of Ni3Sn4, with Ni2.0Cu1.0Sn4 showing the highest anisotropy. After evaluating the electronic structures, the metallic properties of Ni3Sn4 and the Ni2.5Cu0.5Sn4, Ni2.0Cu1.0Sn4, and Ni1.5Cu1.5Sn4 phases are revealed by electronic structure analysis. The total density of states (TDOS) for (Ni,Cu)3Sn4 structures is mainly influenced by Ni-d and Cu-d states. The addition of Cu atoms can increase the brittleness of Ni3Sn4. In addition, the region where d and p hybridisation occurs gradually increases with increasing Cu content. The electronic properties suggest that the binding energy between Ni and Sn atoms weakens with the addition of Cu atoms, resulting in a decrease in the elastic modulus. This research can serve as a valuable reference and theoretical guide for future applications of these materials. [ABSTRACT FROM AUTHOR]

The combined use of Through Silicon Via (TSV) and metal lines, referred to as TSV-metal lines, is an essential structure in three-dimensional integrated circuits. In-depth research into the electromigration failure mechanism of TSV and the microstructure evolution can serve as theoretical guidance for optimizing three-dimensional stacking. This article conducted electromigration experiments on TSV-metal line structural samples at current densities of 1.0 × 105 A/cm2, 5 × 105 A/cm2, and 1 × 106 A/cm2. Additionally, Electron Back Scattered Diffraction (EBSD) technology was employed to systematically investigate the microstructural evolution of the TSV-metal line structure profiles before and after the application of electrical testing. The results indicate that the current induces a change in the crystal orientation at the TSV-metal interface (TSV/metal interface) and the bottom metal line. This phenomenon notably depends on the initial angle between the grain orientation and the current flow direction. When the angle between the current direction and the grain orientations [001] and [010] is relatively large, the crystals are more likely to deviate in the direction where the angle between the grain orientation and the current is smaller. This is because, at this point, the current direction is precisely perpendicular to the <100> crystal plane family, where the atomic density is lowest, and the energy required for electron transport is minimal. Therefore, the current readily rotates in the direction of this crystal orientation. Before the electromigration tests, areas with a high level of misorientation were primarily concentrated at the TSV/metal interface and the corners of the TSV-metal line. However, these areas were found to be more prone to developing voids after the tests. It is conjectured that the high misorientation level leads to elevated stress gradients, which are the primary cause of cracking failures in the TSV-metal line. As the current density increases from 5 × 105 A/cm2 to 1 × 106 A/cm2, the electromigration failure phenomena in the TSV become even more severe. [ABSTRACT FROM AUTHOR]

In this article, we propose a fast three‐dimensional integrated circuit (3D‐IC) floorplanning method for hard macroblocks that includes a thermal management scheme. It applies a genetic algorithm constituted by an optimal combination of crossover and mutation operations to identify the optimal solution for design variables, namely, total wire length, number of through‐silicon vias (TSVs), and maximum average layer power density. The proposed method additionally makes use of a unique TSV placement scheme that arranges TSVs next to their respective functional blocks. To enable efficient heat transmission to the ambient environment, layers with higher power densities are placed closer to the heat sink. The proposed 3D‐IC floorplanning approach provides the fewest TSVs, the lowest peak temperature, and promising values of wire length within the least amount of computation time. Compared to the recent fast thermal analysis for fixed‐outline 3D‐floorplanning, it generates 13.14% shorter wire length, 39.27% lower peak temperature, and 34.35% lesser number of TSVs on average with significant improvement in computation time, while analyzing GSRC thermal benchmark circuits. [ABSTRACT FROM AUTHOR]

The thermal effect and heat dissipation have a significant impact on three-dimensional stacked chips, and the positional layout of the chip's three-dimensional layout directly affects the internal temperature field. One effective way is to plan the overall layout of three-dimensional integrated circuits by considering the thermal effect and layout utilization. In this paper, an ant colony algorithm is used to search for the most planned paths and achieve the overall layout optimization by considering the effects of power, temperature, and location on the thermal layout and using feedback optimization of pheromone concentration. The simulation results show that the optimization of the thermal layout of 3D integrated circuits can be well realized by adjusting the algorithm parameters. The maximum temperature, temperature gradient, and layout scheme verify reliability and practicability. It improves the utilization rate of chips, optimizes the layout, realizes energy conservation, and reduces resource waste. [ABSTRACT FROM AUTHOR]

The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). Atomic layer deposition (ALD) deposited ZnO is an attractive candidate due to its excellent electrical properties, low processing temperature below copper interconnect thermal budget, and conformal sidewall deposition for novel 3D architecture. An optimized ALD deposited ZnO thin-film transistor achieving a record field-effect and intrinsic mobility (µFE /µo) of 85/140 cm2/V·s is presented here. The ZnO TFT was integrated with HfO2 RRAM in a 1 kbit (32 × 32) 1T1R array, demonstrating functionalities in RRAM switching. In order to co-design for future technology requiring high performance BEOL circuitries implementation, a spice-compatible model of the ZnO TFTs was developed. We then present designs of various ZnO TFT-based inverters, and 5-stage ring oscillators through simulations and experiments with working frequency exceeding 10's of MHz. The progress of high-performance oxide-based transistors is essential for seamlessly integrating monolithic 3-D circuits into the CMOS backend. The authors propose using atomic layer deposition for ZnO due to its compatibility with low-temperature backend integration. They also successfully integrated ZnO TFTs with HfO2 RRAM in a 1 kbit 1T1R array, showcasing RRAM switching capabilities. [ABSTRACT FROM AUTHOR]

Advanced packaging technology has become more and more important in the semiconductor industry because of the benefits of higher I/O density compared to conventional soldering technology. In advanced packaging technology, copper–copper (Cu-Cu) bonding has become the preferred choice due to its excellent electrical and thermal properties. However, one of the major challenges of Cu-Cu bonding is the high thermal budget of the bonding process caused by Cu oxidation, which can result in wafer warpage and other back-end-of-line process issues in some cases. Thus, for specific applications, reducing the thermal budget and preventing Cu oxidation are important considerations in low-temperature hybrid bonding processes. This paper first reviews the advancements in low-temperature Cu-based bonding technologies for advanced packaging. Various low-temperature Cu-Cu bonding techniques such as surface pretreatment, surface activation, structure modification, and orientation control have been proposed and investigated. To overcome coplanarity issues of Cu pillars and insufficient gaps for filling, low-temperature Cu-Cu bonding used, but it is still challenging in fine-pitch applications. Therefore, low-temperature Cu/SiO2, Cu/SiCN, and Cu/polymer hybrid bonding have been developed for advanced packaging applications. Furthermore, we present a novel hybrid bonding scheme for metal/polymer interfaces that achieves good flatness and an excellent bonding interface without the need for the chemical mechanical polishing (CMP) process. [ABSTRACT FROM AUTHOR]

A high-resolution frontside fault isolation methodology for the analysis of wafer-to-wafer (W2W) hybrid bonding interconnects in three-dimensional integration is reported. The approach utilizes the visible light optical beam induced resistance change (VL-OBIRCH) method and incorporates a localized substrate removal technique, eliminating the need for a costly backside approach that requires a solid immersion lens. The top silicon substrate is removed using laser lithography and selective etching techniques, enabling the utilization of 405 nm excitation light for the VL-OBIRCH analysis. The validity of the methodology is demonstrated on W2W interconnect test structures with varying interconnect pitch and pad dimensions. The effectiveness of the proposed approach is confirmed through cross-sectional analysis. [ABSTRACT FROM AUTHOR]

Considering the manufacturing and packaging process, 3-D integrated circuits design often requires irregular chip structures. The 3-D integrated circuits with irregular structures can facilitate differentiated chip design and reduce manufacturing costs. Highly complex through-silicon vias have not been considered in past thermal modelling and analysis of irregularly structured 3-D integrated circuits. Thus, a detailed model of a three-layer irregularly structured 3-D integrated circuit with through-silicon vias and microbumps is developed, and an analytical method based on the thermal resistance network model is proposed to extract the equivalent thermal conductivity of through-silicon vias and microbumps, the accuracy of which is verified by a 3-D finite element simulation method. The results show that the maximum temperature and temperature gradient obtained by the equivalent model simulations agree well with the detailed model results, proving the validity of the equivalent model. To save the computational cost, the effects of heat source area, power setting and through-silicon vias structure parameters on the maximum temperature are studied by numerical simulation method based on the equivalent model. Heat source area equal to the overlap between chip layers, high power chips close to the heat sink, and reducing through-silicon vias pitch can better reduce the maximum temperature. The results provide a reference value for thermal design and optimization of 3-D integrated circuits with irregular structures. [ABSTRACT FROM AUTHOR]

In the past few years, thermal through silicon via (TTSV) has been experimentally investigated as an effective heat dissipation path. Although a lot of heat dissipation- related issues have been solved in 3-D integrated circuit (3-D-IC), there are neglections in TTSV placement with non-uniform heat sources so far. In this study, a unique optimization is proposed to locate TTSV while effectively alleviating hot spots in 3-D-IC. The thermal dissipation of non-uniform heat sources are studied using the finite element method. The simulation results show that the minimum temperature is reduced by 2.1% compared with peak temperature in the single-layer chip, and by 1.9% in the three-layer chip. [ABSTRACT FROM AUTHOR]

The development of big data and artificial intelligence technology is increasing the need for electronic devices to become smaller, cheaper, and more energy efficient, while also having enhanced functionalities. However, the miniaturization of silicon chip technology is approaching its Moore's law (i.e., physical) limits. Thus, the application of three-dimensional integrated circuits (3D ICs), in which multiple chips are stacked vertically, provides the most achievable approach for the advancement of post-Moore electronics. In the recent decade, various key techniques have been developed for stacking chips vertically such as through-silicon vias, micro-bumps, low melting point tin–bismuth solders, redistribution layers, and copper-to-copper direct bonding. However, the need for high current densities in these structures results in severe Joule heating, making electromigration (EM) an increasingly challenging problem. This paper reviews studies on EM failures, mechanisms, and potential solutions for the key components of 3D IC packaging. [ABSTRACT FROM AUTHOR]

The results of a theoretical study of the behavior of a system of nanophotonic devices, consisting of receiving and transmitting plasmonic metal antennas, are presented. Based on the finite element method, the main parameters of antennas located in the TSV channel and receiving a signal in the terahertz frequency range are calculated. The limiting range of signal transmission and the coefficient of its amplification are determined. Conclusions are drawn on the suitability of the presented configuration as a system for wireless data transmission and reception in three-dimensional integrated circuits. [ABSTRACT FROM AUTHOR]

At 12.8 MHz center frequency, the advanced miniaturized polymerbased planar high quality factor (Q) passive elements embedded bandpass filter works in the L-band. Because most of the demands operate inside the spectrum, the wideband or high-speed operation necessary to enhance must be acquired in microwave frequency ranges. The channel has a quiet, high-performance microfilter with wideband rejection. Capacitors and inductors are used in the high quality factor (Q) passive components, and related networks are incorporated in the filter. Embedded layers are concatenated using Three-Dimensional Integrated Circuit (3D-IC) integration, parasitics are removed, and interconnection losses are negotiated using de-embedding methods. A wireless application-based Liquid Crystalline Polymer (LCP) viewpoint is employed as a substrate material in this work. The polymer processes, their properties, and the incorporated high-Q Band Pass Filter Framework. The suggested filter model is computed and manufactured utilizing the L-band frequency spectrum, decreasing total physical length by 31% while increasing bandwidth by 45%. [ABSTRACT FROM AUTHOR]

Through silicon via technology is a promising and preferred way to realize the reliable interconnection for 3-D integrated circuit (3-D IC), which can transfer heat from multiple dies to the heat sink in vertical direction. In this paper, a new general model of the through-silicon via (TSV) is proposed to investigate the thermal performance of the 3-D IC. The heat transfer characteristics of conical-annular TSV are studied for the first time. The impacts of different sidewall inclination angles and insulating layer thicknesses of TSV on the heat dissipation of 3-D IC were compared and analyzed in detail. As expected, our proposed model is in good agreement with the results of the existing models, which shows that the proposed model considering the lateral heat transfer and TSV structures can predict the distribution of temperature more efficiently and accurately. Furthermore, it is found that conical-annular TSV has more excellent heat dissipation performance. [ABSTRACT FROM AUTHOR]

This study proposed a novel source/drain (S/D) extension scheme to increase the stress in nanosheet (NS) field-effect transistors (NSFETs) and investigated the scheme by using technology-computer-aided-design simulations. In three-dimensional integrated circuits, transistors in the bottom tier were exposed to subsequent processes; therefore, selective annealing, such as laser-spike annealing (LSA), should be applied. However, the application of the LSA process to NSFETs significantly decreased the on-state current (Ion) owing to diffusionless S/D dopants. Furthermore, the barrier height below the inner spacer was not lowered even under on-state bias conditions because ultra-shallow junctions between the NS and S/D were formed far from the gate metal. However, the proposed S/D extension scheme overcame these Ion reduction issues by adding an NS-channel-etching process before S/D formation. A larger S/D volume induced a larger stress in the NS channels; thus, the stress was boosted by over 25%. Additionally, an increase in carrier concentrations in the NS channels improved Ion. Therefore, Ion increased by approximately 21.7% (37.4%) in NFETs (PFETs) compared with NSFETs without the proposed scheme. Additionally, the RC delay was improved by 2.03% (9.27%) in NFETs (PFETs) compared with NSFETs using rapid thermal annealing. Therefore, the S/D extension scheme overcame the Ion reduction issues encountered in LSA and significantly enhanced the AC/DC performance. [ABSTRACT FROM AUTHOR]

In response to the increasing manufacturing complexity/cost in maintaining DRAM advancements through traditional scaling, three-dimensional integrated circuits (3D ICs) and 2.5-dimensional ICs with Si interposers are known as promising candidates to overcome these challenges due to their advantages of low power, small form factor, high density, and high bandwidth. In this work, we present a true process-heterogeneous stacked embedded DRAM (SeDRAM) using hybrid bonding 3D integration process, achieving high bandwidth of 34 GBps/Gbit and high energy efficiency of 0.88 pJ/bit. Moreover, the critical factors of the SeDRAM design are presented (e.g., the low data movement energy, high-density physical interface, simplified protocol definition, process compatibility, density extensibility, and hybrid bonding connection fast test by DFT (design for test). Our results and design methodology have paved the way to realize applications of hybrid bonding to high bandwidth and energy efficiency DRAM. More importantly, the SeDRAM solution can also support the maximum storage density of 48 Gbit and the bandwidth capability of TBps. It can greatly alleviate the "memory wall" problem and thus improve its competitiveness in near-memory computing/computing-in-memory fields. [ABSTRACT FROM AUTHOR]

This paper proposes a novel technique of TSV BIST repair that targets the design yield and various test challenges of three-dimensional integrated circuits (3D stacked ICs). The proposed methodology is efficient to cover the various faults during the fabrication, the interconnect breakages, shorts, bridges, void formation, thermal and physical stress, etc., during the TSV fabrication and stacking of 3D ICs. The repair mechanism provides a redundancy feature to replace the failing TSVs with spare TSVs in the design. It provides a significant impact on yield compared to the standard TSV testing approach. Further analysis was performed on different stacked levels of 3D ICs, and the results were compared with the existing industrial methods in terms of the yield and test time parameters. The proposed mechanism showed a significant improvement of 12.5% in the yield and 17.5% in the test time and also recovered all defective chips efficiently. [ABSTRACT FROM AUTHOR]

This paper introduces a new method to reduce the crosstalk effects in copper-multiwalled carbon nanotube (Cu-MWCNT) based heterogeneous coaxial through-silicon vias (HCTSVs) for three-dimensional integrated circuits (3D ICs). The proposed HCTSV structure utilizes Cu-MWCNT bundles as a conducting material and polymer liners such as polyimide, polypropylene carbonate (PPC) and benzo cyclobutene (BCB) as dielectric materials. The crosstalk effects such as functional and dynamic crosstalks are evaluated for the coupled HCTSVs by using an electrical equivalent model implemented in synopsis based HSPICE simulator. Moreover, the other performance parameters such as power consumption, power delay product (PDP) and energy delay product (EDP) are analyzed. From the analysis, it is noticed a significant improvement in crosstalk effects, power consumption, PDP, and EDP for polymer liners over the conventional silicon dioxide liner. Moreover, the performance is also evaluated by changing the different heights of HCTSVs from 50 to 200 μm, respectively. It is observed that the performance of the coupled HCTSVs are increased as the TSV height is reduced. [ABSTRACT FROM AUTHOR]

In advanced lithography and etch processes, the after-etch overlay is rendered unequal to the after-development overlay, and an etch process–induced overlay plays an extremely important role in determining the total overlay. This makes it difficult to achieve feedback control and also throws the overlay residue out of the control specifications. As the layer number of three dimensional integrated circuits increases or the overlay residue is only several nanometers in extreme ultraviolet technology, differentiations in etch tools lead to lot-to-lot overlay differences. Tool difference should be considered to compensate the overlay, irrespective of which method, interfield, intrafield, or correction per exposure (CPE), is used. However, it is not recommended to compensate the overlay for every lot as it will increase the cost of metrology. One of the widely used methods is to separate the lots by groups. In this paper, we propose a Zernike-CPE method to conduct a systematic study on how to reduce the overlay residue during the process of providing CPE feedback and to monitor tool performance. The research results demonstrate that the proposed method has potential roles to play in achieving overlay control and is highly suitable for advanced technology process monitoring. [ABSTRACT FROM AUTHOR]

Through silicon vias (TSVs) are a key enabling technology for interconnection and realization of complex three‐dimensional integrated circuit (3D‐IC) components. In order to perform failure analysis without the need of destructive sample preparation, x‐ray microscopy (XRM) is a rising method of analyzing the internal structure of samples. However, there is still a lack of evaluated scan recipes or best practices regarding XRM parameter settings for the study of TSVs in the current state of literature. There is also an increased interest in automated machine learning and deep learning approaches for qualitative and quantitative inspection processes in recent years. Especially deep learning based object detection is a well‐known methodology for fast detection and classification capable of working with large volumetric XRM datasets. Therefore, a combined XRM and deep learning object detection workflow for automatic micrometer accurate defect location on liner‐TSVs was developed throughout this work. Two measurement setups including detailed information about the used parameters for either full IC device scan or detailed TSV scan were introduced. Both are able to depict delamination defects and finer structures in TSVs with either a low or high resolution. The combination of a 0.4×$$ \times $$ objective with a beam voltage of 40 kV proved to be a good combination for achieving optimal imaging contrast for the full‐device scan. However, detailed TSV scans have demonstrated that the use of a 20×$$ \times $$ objective along with a beam voltage of 140 kV significantly improves image quality. A database with 30,000 objects was created for automated data analysis, so that a well‐established object recognition method for automated defect analysis could be integrated into the process analysis. This RetinaNet‐based object detection method achieves a very strong average precision of 0.94. It supports the detection of erroneous TSVs in both top view and side view, so that defects can be detected at different depths. Consequently, the proposed workflow can be used for failure analysis, quality control or process optimization in R&D environments. [ABSTRACT FROM AUTHOR]

Advances in the theory of semiconductors in the 1930s in addition to the purification of germanium and silicon crystals in the 1940s enabled the point-contact junction transistor in 1947 and initiated the era of semiconductor electronics. Gordon Moore postulated 18 years later that the number of components in an integrated circuit would double every 1 to 2 years with associated reductions in cost per transistor. Transistor density doubling through scaling—the decrease of component sizes—with each new process node continues today, albeit at a slower pace compared with historical rates of scaling. Transistor scaling has resulted in exponential gain in performance and energy efficiency of integrated circuits, which transformed computing from mainframes to personal computers and from mobile computing to cloud computing. Innovations in new materials, transistor structures, and lithographic technologies will enable further scaling. Monolithic 3D integration, design technology co-optimization, alternative switching mechanisms, and cryogenic operation could enable further transistor scaling and improved energy efficiency in the foreseeable future. [ABSTRACT FROM AUTHOR]

Cu-to-Cu direct bonding plays an important role in three-dimensional integrated circuits (3D IC). However, the bonding process always requires high temperature, high pressure, and a high degree of consistency in height. In this study, Sn is passivated over electroplated copper. Because Sn is a soft material and has a low melting point, a successful bond can be achieved under low temperature and low pressure (1 MPa) without any planarization process. In this experiment, Sn thickness, bonding temperature, and bonding pressure are variables. Three values of thicknesses of Sn, i.e., 1 μm, 800 nm, and 600 nm were used to calculate the minimum value of Sn thickness required to compensate for the height difference. Additionally, the bonding process was conducted at two temperatures, 220 °C and 250 °C, and their optimized parameters with required pressure were found. Moreover, the optimized parameters after the Cu planarization were also investigated, and it was observed that the bonding can succeed under severe conditions as well. Finally, transmission electron microscopy (TEM) was used to observe the adhesion property between different metals and intermetallic compounds (IMCs). [ABSTRACT FROM AUTHOR]

Tier partitioning is one of the most critical stages in monolithic 3-D (M3D) integrated circuits (ICs) implementation flows. It transforms 2-D netlists into 3-D by performing tier assignment for each design instance, which directly impacts the power, performance, and area (PPA) metrics of final 3-D full-chip designs. However, the current state-of-the-art tier partitioning approach named bin-based min-cut algorithm has fundamental flaws that lead to severe drawbacks, such as timing degradation, 3-D routing overhead, and redundant monolithic intertier vias (MIVs) insertion. To overcome these issues, in this article, we propose TP-GNN, an unsupervised graph learning-based tier partitioning framework that utilizes graph neural networks (GNNs) and advanced machine learning (ML) techniques to perform tier partitioning. The proposed framework comprehends design- and technology-related parameters properly so that it is generalizable to various netlists and technologies. In addition, it can be integrated with any style of M3D design flows that require tier assignments of standard cells. In the experiments, we validate the proposed framework on seven industrial designs with two different fashions of M3D implementation flows: 1) partitioning-first (Snap3D) and 2) partitioning-last (Shrunk2D and Compact2D) flows. We demonstrate that our framework, TP-GNN, significantly improves the 3-D quality of results (QoR) across most testing designs in a large margin compared with the bin-based min-cut tier partitioning algorithm. Specifically, in OpenPiton, an RISC-V-based multicore system, we observe 27.4%, 7.7%, and 20.3% improvements in performance, wirelength, and energy-per-cycle, respectively. Finally, we perform a case study by applying the proposed framework to a heterogeneous M3D design flow, Pin3D, on a commercial CPU design and observe that TP-GNN reaches better partitioning solutions than the existing partitioning approaches for heterogeneous 3-D ICs. [ABSTRACT FROM AUTHOR]

In this work, an ultra-thin cobalt film is used as a passivation layer to achieve a Cu–Cu quasi-direct bonding process, and successful bonding was achieved at the bonding temperature of 230 °C with the bonding pressure of 0.5 MPa in non-vacuum conditions. A tensile bonding strength of over 12.8 MPa can be achieved. With the cobalt layer, the total film roughness is greatly reduced to around 1 nm, and the cross-sectional transmission electron microscope images reveal the presence of a void-free bonding interface. Time-of-flight secondary ion mass spectrometry depth analysis is carried out using a PVD deposited multilayer sample, which simulates the bonding process without pressure. It is found that a Cu–Co intermixing layer formed between the Cu and Co interfaces during annealing, and Cu has diffused into the Co layer. Due to the nanocrystalline structure of the Co film and the low roughness of the system, a low bonding temperature can be achieved. These results demonstrate that Co, which can be selectively grown on the Cu surface, can be used as a passivation layer to achieve low-cost and high-quality interconnect for the three-dimensional integrated circuits. [ABSTRACT FROM AUTHOR]

Exploiting thermal coupling among the cores of a processor to secretly communicate sensitive information is a serious threat in mobile, desktop, and server platforms. Existing works on temperature-based covert communication typically rely on controlling the execution of high-power CPU stressing programs to transmit confidential information. Such covert channels with high-power programs are typically easier to detect as they cause significant rise in temperature. In this work, we demonstrate that by leveraging vertical integration, it is sufficient to execute typical SPLASH-2 benchmark applications to transfer 200 bits per second (bps) of secret data via thermal covert channels. The strong vertical thermal coupling among the cores of a 3-D multicore processor increases the rates of covert communication by $3.4\times $ compared to covert communication in conventional 2-D integrated circuits (ICs). Furthermore, we show that the bandwidth of this thermal communication in 3-D ICs is more resilient to thermal interference caused by applications running in other cores. This reduced interference significantly increases the danger posed by such attacks. We also investigate the effect of reducing intertier overlap between colluded cores and show that the covert channel bandwidth is reduced by up to 62% with no overlap. [ABSTRACT FROM AUTHOR]

In three-dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, yield is one of the key obstacles to adopt the TSV-based 3D-ICs technology in the industry. Various fault-tolerance structures using redundant TSVs to repair faulty functional TSVs have been proposed in the literature for yield and reliability enhancement. However, the TSV repair paths under delay constraint cannot always be generated due to the lack of appropriate repair algorithms. In this article, we propose an effective TSV repair strategy for the router-based TSV redundancy architecture, taking into account the delay overhead. First, we prove that the router-based fault-tolerance structure configuration (RFSC) with the delay constraint is equivalent to the length-bounded multicommodity flow (LBMCF) problem. Then, an integer linear programming (ILP) formulation with acceptable scalability is presented to solve the LBMCF problem. The experimental results demonstrate that, compared with state-of-the-art fault-tolerance designs, the proposed ILP model can provide higher yield and lower delay overhead. [ABSTRACT FROM AUTHOR]

The relatively large total device dimension (${L}_{\rm Tot}$) of Ferroelectric-Semiconductor Tunnel Junctions (MFIS-FTJs) strictly obstructs their potential for hyper-scaling 3D integration. Towards such an issue, we propose an engineered MFIS-FTJ with the ultrathin semiconductor electrode (SE). The design rule for MFIS-FTJs with ultrathin SE is also investigated, considering voltage redistribution, SE thickness limitation, and quantum confinement effect. With careful design, our MFIS-FTJs with an 8.5 nm-thick SE achieve an ultrascaled ${L}_{\rm Tot}$ around 10 nm and acquire ~40 times enhancement in the tunneling electroresistance ratio over the bulk reference devices. This opens up a feasible pathway for ${L}_{\rm Tot}$ scaling in MFIS-FTJ and is instructive for practical application. [ABSTRACT FROM AUTHOR]

Three-Dimensional Integrated Circuit (3D IC) based on Through-Silicon-Via (TSV) has brought a drastic change in IC technology. Since TSVs connect different layers of 3D stacks, their proper functioning is an essential prerequisite for system operation. Therefore, testing of TSV is essential for 3D IC. In this article, we propose a cost-effective Built-In Self-Test (BIST) method to test the TSVs of a 3D IC. The test method aims at identifying single and multiple defective TSVs using low test time with small hardware overhead. Further, we introduce a BIST partitioning scheme to reduce the test time and hardware overhead for many TSVs. We also present EBIST, an extended-BIST, to enhance BIST reliability with the least hardware cost. The time cycle needed for testing is calculated and compared with previously proposed methods. The simulation result shows that the proposed BIST reduces the test time by 87% compared to prior works. Moreover, the approach yields reduced area as compared to existing test architecture. [ABSTRACT FROM AUTHOR]

A surface creep model is presented for analyzing Cu-to-Cu direct bonding under thermal compression. The driving force is a pressure gradient, which squeezes layers of atoms to fill voids at the bonding interface. The link among the key parameters of surface roughness, experimental bonding time, temperature, and pressure is presented in a kinetic equation. The theoretical bonding time can be calculated through these key parameters. The benchmark of the theoretical bonding time is the time required for the bonding area to reach 95%, which is measured from TEM images of the bonding interface. The experimental bonding time might be longer, and the bonding area might larger than 95%. Because the bonding mechanism includes surface diffusion and grain boundary diffusion, it is difficult to distinguish their individual influence. Therefore, the effective diffusivity (Deff) is calculated from the bonding conditions of other research and the equation of bonding model. If the bonding surface is highly (111)-oriented, the Deff is close to the (111) surface diffusivity. From the surface creep bonding model, the theoretical bonding time of grain boundary diffusion is very sensitive to the bonding temperature, while that of (111) surface diffusion is not. Additionally, at low temperature bonding (

Through silicon via (TSV) is the key technology for 3-D integrated circuits (3-DICs) which could vertically stack homogeneous or heterogeneous dies with the high performance and density. To evaluate the electrical characteristics of TSV at the high-frequency transmission, the skin effect and surface roughness effect are necessary to be considered. However, these effects would significantly result in the TSV equivalent resistance under the high operating frequency. Thus, it is important to investigate the carbon nano tubes (CNTs) TSV which has less skin effect intrinsically. In this work, we analyze the advantage of CNTs as TSV compared to the conventional filling materials such as copper (Cu). Furtherly, we also propose the equivalent circuit model of TSV and its multi-layer structure to simulate the electrical behaviors with different TSV pitch, height, diameter, and stacking layers by using ANSYS designer and high-frequency structure simulator (HFSS). Based on the frequency-domain analysis, it can be found that CNTs TSV has the lower frequency-dependent loss than Cu due to the lower equivalent resistance. In a summary, CNTs could be a promising TSV filling material at the high-speed transmission frequency based on our study. [ABSTRACT FROM AUTHOR]

In this article, an efficient approach based on the parallel alternating direction implicit (ADI) method is presented for the transient thermal simulation of liquid-cooled 3-D integrated circuits (ICs). To accurately characterize the thermal behaviors, a compact thermal model based on finite-difference approximation is established. The ADI method with linear time complexity is utilized to reduce computational cost, which can easily deal with large-scale problems. To suppress the oscillations of transient results in the case of large time steps, an effective technique using the exponentially expanding subtime steps is introduced, which improves the accuracy of results significantly. In addition, taking the advantage of parallel computing, the transient simulation is further accelerated by the parallel cyclic reduction (PCR) algorithm implemented on graphics processing units (GPUs). The accuracy and efficiency of the proposed method are demonstrated by several numerical examples. [ABSTRACT FROM AUTHOR]

In this article, a discontinuous Galerkin time-domain (DGTD) method hybridized with Robin transmission condition (RTC-DGTD) is proposed for the transient thermal analysis of 3-D integrated circuits (ICs). As a kind of domain decomposition method (DDM), the DGTD method employs a term named numerical flux for the information exchange of solutions between neighboring subdomains. The numerical flux is a function of both temperature $T$ and heat flux q, and thus for the heat equation, apart from $T$ , the variable q has to be solved as well. To reach this, the traditional DGTD method decomposes the second-order partial-differential thermal equation into two first-order ones, which results that both $T$ and q need to be solved in the whole computational domain, thereby the computational cost is extremely expensive. In this work, to get this trouble-treated, the proposed DGTD method is directly applied to discretize the second-order heat equation. An RTC is established at the interfaces of subdomains, which serves as the second governing equation and meanwhile bridges another connection of solutions in adjacent subdomains. In this way, the new variable q is now only present at the interfaces of subdomains. Consequently, the total number of unknowns is significantly reduced compared with that in the traditional DGTD method. To further speed up the time-marching scheme, an adaptive time-stepping method in terms of the proportional–integral–derivative (PID) control algorithm is employed. Besides, by introducing a restriction operator, the globally coupled matrix equation is torn into a number of small matrix equations pertinent to each subdomain, which is later solved via a finite-element tearing and interconnecting (FETI)-like method. To validate and verify the accuracy and efficiency of the proposed algorithm, several representative examples are studied and compared with COMSOL simulations. [ABSTRACT FROM AUTHOR]

During the manufacturing process of three-dimensional integrated circuits (3-D ICs), many defects may occur in through-silicon vias (TSVs). These defects affect the integrity of the signal passing through TSVs, therefore detecting these defects in the early production stage is crucial. This article proposed a built-in-self-test (BIST) method with a simple test structure and easily implemented fault detection process. Due to the fact that the defects in TSVs influence the charge/discharge speed of TSVs’ equivalent capacitance, a weak current source is designed as the central part of the proposed test structure, which can measure the TSVs’ charge/discharge speed and quantify it using digital values. The effectiveness and robustness of the proposed method is validated by HSPICE simulation. The minimum measurable fault, test time, and test circuit area are also assessed in this article. The simulation results show that the method this article proposed can detect weaker faults, compared with the traditional test methods. [ABSTRACT FROM AUTHOR]

As Moore’s law with traditional process node scaling is slowing down, other techniques are required for the advancement of process nodes. In this work, we focus on one such alternative: 3-D physical design of integrated circuits (ICs). While many recent studies have shown the benefits of 3-D IC design on timing and power consumption of circuits, routing in 3-D is solely done with the automatic commercial routers and has not been well studied. In this article, we discuss the various routing scenarios that arise from cell partitioning and the metal layer stack in 3-D. Unlike a 2-D IC, the metal layer configuration in 3-D depends on the orientation in which the dies are bonded together. Due to this, depending on the configuration, cells in one tier tend to use routing layers from the other tier. This is referred to as metal layer (or) routing sharing. This depends on the metal layer stack and the cell partitioning in 3-D, as well as the via pitch used for 3-D connections. By analyzing metal layer sharing in detail, we see that it can help reduce metal layer costs in 3-D as well as improve the power consumption and, in some cases, the maximum achievable performance of the circuits. Overall, the 3-D metal layer cost can decrease by 9% along with an improved power delay product of up to 7.5% just from the routing sharing in monolithic 3-D ICs. [ABSTRACT FROM AUTHOR]

We describe a design and fabrication experiment that has been performed to investigate a methodology for assessing the security of application specific integrated circuits (ASICs) fabricated in a split-manufacturing process based on 3-D integrated circuit (3DIC) technologies. The purpose of this process is to protect critical IP from reverse engineering if an adversary obtains either the fabricated wafers or their GDS. A number of 3DIC-based fabrication alternatives were evaluated, and one is selected for this experiment. Several designs, from the trivial to the complex, were used for the study. A self-test module was embedded in each design to facilitate the postfabrication testing. Various obfuscation techniques that include camouflage in the form of function and lookup table hiding and insertion of redundant logic in order to confuse potential attackers were applied. Smart partitioning was implemented for each design in an attempt to conceal vital functions. We introduced metrics that are based on the number of connection possibilities ($C_{p}$) and the depth of partitioning ($P_{\mathrm{ depth}}$) to measure the obfuscation strength. The results show that it should take more than 10 60 years to reconstruct the netlist using a brute-force attack. Measurement results are presented showing fabrication success. [ABSTRACT FROM AUTHOR]

An original concept of 3-D through-silicon via (TSV)-based Marchand baluns and its design methodology is proposed for on- chip and 3-D integration. By utilizing a 3-D packaging process that includes a TSV and redistribution layer (RDL), a meander coupling path is established and embedded in the vertical direction of the substrate for balun design. The 3-D structure can effectively reduce the on- chip area while maintaining good balance characteristics. Furthermore, the structure can be flexibly integrated with 3-D integrated circuits (3-D ICs) to realize signal conversion between different stacking tiers. An equivalent circuit model based on the TSV-to-TSV coupling channel and coupled transmission line has been established for initial estimation before electromagnetic (EM) optimization. To shorten the design cycle, a specific flow is proposed to meet the structural particularity and different application scenarios. To verify the design method and flow, a design case is analyzed and EM simulated with the antenna feeding network as the target application. The EM simulation results show that the design can work at 43–82 GHz with an amplitude imbalance of less than 0.3 dB and a phase imbalance of less than 1.3°, which meets the requirements of balanced feeding. It only costs a $0.084\,\,\lambda _{\text {g}}\,{\times }\,0.009\,\,\lambda _{\text {g}}$ footprint, which is far lower than that of the conventional planar types. [ABSTRACT FROM AUTHOR]

Sn-rich solder joints in three-dimensional integrated circuits and their reliability issues, such as the electromigration (EM), thermomigration (TM), and thermomechanical fatigue (TMF), have drawn attention related to their use in electronic packaging. The Sn grain orientation is recognized as playing an important role in reliability issues due to its anisotropic diffusivity, mechanical properties, and coefficient of thermal expansion. This study reviews the effects of the Sn grain orientation on the EM, TM, and TMF in Sn-rich solder joints. The findings indicate that in spite of the failure modes dominated by the Sn grain orientation, the size and shape of the solder joint, as well as the Sn microstructures, such as the cycling twining boundary (CTB), single crystals, and misorientations of the Sn grain boundary, should be considered in more detail. In addition, we show that two methods, involving a strong magnetic field and seed crystal layers, can control the Sn grain orientations during the solidification of Sn-rich solder joints. [ABSTRACT FROM AUTHOR]

In this work, an analytical model of strain and stress of symmetrical multilayer medium is proposed to solve the thermal problem that occurs in silicon-core coaxial through-silicon vias (S-CTSV). Based on the 3-D Kane–Mindlin theory, the proposed analytical model of strain considers both elastic strain and thermal strain. In addition, the stress is discussed in segments using planar stress and Hooke’s law in the model of S-CTSVs to improve the accuracy. The results indicate that the average relative errors in terms of strain and stress between the results of the proposed analytical model and the finite-element method (FEM) were 4.06% and 0.17%, respectively. Compared with the back propagation (BP) neural network-based prediction algorithm, the average relative errors in strain and stress between the proposed model and the FEM were decreased by 3.97% and 3.23%, respectively. Moreover, the stress of three different CTSVs was also compared. The stress of the proposed S-CTSVs model was lower than those of the two traditional CTSVs, which ensure higher reliability. The results in this article would provide some design guides for S-CTSVs in 3-D integration. [ABSTRACT FROM AUTHOR]