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Standard CMOS reliability has been focused on digital applications and the user profiles associated with these products. However, emerging applications in mobility, automotive, communication networks and data centers require additional, more rigorous reliability specifications. For these applications, the devices operate beyond the typical safe operation area (SOA) mostly because large drain biases are applied during the normal operation. In this situation, off-state TDDB could be a concern and it must be considered during product design. In this study, we present the models to describe off-state TDDB and the methodology to accurately predict the SOA for circuits under standard operation condition in field. The presented SOA approach relaxed the stringent reliability requirements defined on DC operation, reducing design overhead, and developing and verification costs.

The endless demand for high performance and low power CMOS devices at extremely scaled cell dimensions led the semiconductor industry to migrate to FinFET structures. This evolution has brought higher integration complexity and has forced the reliability engineers to be aware of interrelation among process conditions affecting electrical degradation and failure. In this work, major integration steps which impact FEOL/MOL reliability are discussed, and guidance is provided for reliability-aware FinFET design.

We report extensive experimental results on the Negative Bias Temperature Instability (NBTI) of SiGe channel pMOSFETs as a function of the main gate stack parameters. These results clearly show that this high-mobility channel technology offers a significantly improved NBTI robustness compared to Si-channel devices, which can virtually eliminate this critical reliability issue for sub-1 nm EOT devices. The intrinsically superior NBTI robustness is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. Thanks to this effect, both a significantly reduced time-dependent variability in nanoscaled SiGe devices and a reduced low-frequency noise are also observed. Other reliability mechanisms, such as Channel Hot Carriers and Time-Dependent Dielectric Breakdown are shown not to be showstoppers. All these aspects underscore the SiGe channel technology as a very promising alternative to Si pMOSFETs for future CMOS technology nodes.

In this invited paper, we demonstrate how physical analysis techniques that are commonly used in integrated circuits failure analysis can be applied to detect the failure defects associated with ultrathin gate dielectric wear-out and breakdown in [email protected] materials and investigate the associated failure mechanism(s) based on the defect chemistry. The key contributions of this work are perhaps focused on two areas: (1) how to correlate the failure mechanisms in [email protected]/metal gate technology during wear-out and breakdown to device processing and materials and (2) how the understanding of these new failure mechanisms can be used in proposing ''design for reliability'' (DFR) initiatives for complex and expensive future CMOS nanoelectronic technology nodes of 22nm and 15nm. Hf-based [email protected] materials in conjunction with various gate electrode technologies will be used as main examples while other potential [email protected] gate materials such as cerium oxide (CeO"2) will also be demonstrated to further illustrate the concept of DFR.

In this paper, we examine the time-dependent dielectric breakdown (TDDB) reliability of p-type field-effect transistor devices with 0.7-nm-equivalent-oxide-thickness HfO2 gate dielectric layers. The TDDB distributions indicate ten-year lifetime with operating voltages in excess of 1 V. The reason for this high reliability lies in the high Weibull slopes (~1.2) of the measured TDDB distributions. In order to understand the mechanism behind the high Weibull slope, a detailed study of the defect generation by stress-induced leakage current (SILC) measurements is presented. The layers show different defect generation behavior as a function of temperature where the SILC generation rate at high temperature is stress voltage dependent.

HfSiOx with TiN gate is investigated under substrate injection with respect to stress-induced leakage current (SILC). Most damage caused by electrical stress was found in the high- layer and not in the interface to silicon. Dependent on the application, SILC can exhibit several levels of severity. In pure logic circuits, a large area approximation is sufficient. However, for memory applications, the current increase in small area is important as well. Both contributions are investigated, revealing no lifetime-limiting current increase. With an improved deposition process, SILC can even be suppressed.

Atomic layer deposition (ALD) with HfCl4 as a precursor is widely used for HfO2 fabrication. Due to the nature of the precursor under study, i.e., HfCl4 and H2O, the presence of chlorine residues in the film due to insufficient hydrolysis is eminent. Obviously, the chlorine residue in the HfO2 film is suspected to affect the quality of the HfO2 film. In this paper, The authors reduced the concentration of chlorine residues by increasing the H2O oxidant pulse time in between the deposition cycles from 0.3 to 10 and 90 s. Time-of-flight secondary ion mass spectrometry analysis shows that this decreases the chlorine concentration in the HfO2 film by more than one order of magnitude. However, time-dependent dielectric breakdown analysis shows that the lifetime remains quasi unaffected (within identical error bars) for the different injection cycles. Charge pumping analysis was done by varying both pulse frequency and amplitude to investigate the creation of defects, but negligible differences were observed. Therefore, the presence of chlorine residues has no significant impact on the trap generation and reliability of ALD HfO2 layers, and this result corresponded with the mobility result. The experimental picture is confirmed with first-principle calculations that show that the presence of chlorine residues does not induce defect levels in the bandgap of HfO2

In this paper, we propose a new methodology for sensing the breakdown location along the channel length with the MOSFET biased in the inversion regime. The usefulness of this technique is demonstrated in the characterization of ultrathin Hf-silicate gate dielectrics breakdown. Two different breakdown modes are deconvoluted: an initial progressive breakdown in the channel with a degradation rate strongly dependent on the applied voltage and a successive hard-breakdown at source and drain extensions, which more impacts the device reliability.

Channel Hot-Carrier (CHC) degradation in short channel transistors with a high-k/metal gate stack processed in CMOS technology has been analysed. For short channel transistors (L≪0.15?m), the most damaging stress condition has been found to be V G =V D instead of the "classical" V G =V D /2 determined for long channel transistors. In this work, we have demonstrated that this shift is not caused by the presence of the high-k layer but due to short channel effects. Furthermore, the CHC degradation lifetime has been evaluated, revealing larger operating voltages for high-k than for SiO 2 based transistors.

We report, for the first time, a comprehensive study on various capping integration options for WF engineering in MuGFET devices with TiN gate electrode: HfSiO/cap/TiN, cap/HfSiO/TiN and HfSiO/TiN/cap/TiN vs. reference deposition sequence HfSiO/TiN (cap = Al2O3 for pmos, and Dy2O3 or La2O3 for nmos). We show that: 1) low-VT values (Lt 0.3 V) are achieved for both nmos and pmos, with excellent process control and device behavior down to Lg ap 50 nm and WFIN ap 20 nm, for optimized gate stack configurations; 2) inserting a cap layer in-between TiN layers instead of HfSiO/cap/TiN leads to improved mobility, reduced CET without impacting JG, similar noise response and improved BTI behavior, with correction of the abnormal PBTI degradation seen for HfSiO/DyO/TiN. Is also enables simplified and more robust CMOS co-integration of low- and med-VT devices in the same wafer, avoiding loss in CET and damage of the host dielectric with the cap removal process.

This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (WF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: a) deposition of a Dy2O3 capping layer on the host dielectric (SiON or HfSiON), or b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: 1) both cases result in dielectric modification with gate leakage (JG) reduction; 2) adding a cap has no significant impact on Tinv (

The authors demonstrate high-performing n-channel transistors with a HfO2/TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 Aring, a leakage current of 1.5 A/cm2 at VG=1 V, a peak mobility of 190 cm2/Vmiddots, and a drive-current of 815 muA/mum at an off-state current of 0.1 muA/mum for VDD=1.2 V. Identical gate stacks processed with a 1000-degC spike anneal have a higher peak mobility at 275 cm2/Vmiddots, but a 5-Aring higher EOT and a reduced drive current at 610 muA/mum. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 degC) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V

The migration of Ta atoms from a transistor gate electrode into the percolated high-κ (HK) gate dielectrics is directly shown using transmission electron microscopy analysis. A nanoscale metal filament that formed under high current injection is identified to be the physical defect responsible for the ultrafast transient breakdown (BD) of the metal-gate/high-κ (MG/HK) gate stacks. This highly conductive metal filament poses reliability concerns for MG/HK gate stacks as it significantly reduces the post-BD reliability margin of a transistor.

Results from an extensive reliability characterization of HfLaSiO(N) devices, with TaN gate electrodes, are reported. It is shown that the effect of the lanthanum, initially deposited as La2O3, on a SiO2/HfSiO(N) stack, permeates the Si/SiO2 interface. A lower midgap interface state density is observed at this interface, but increased densities are seen towards the band edges. The presence of lanthanum in the dielectric results in defects in the interface layer and in the high-κ dielectric. A profile of defects in the gate stack is suggested, inferred from a combination of electrical measurements. From the location of the defects, it is argued that the reliability of lanthanum-incorporated devices is not compromised by its presence, thus enabling a reliable route to Vt tuning of n-type metal oxide semiconductor devices.

Ultrafast progressive breakdown has been observed in a TaN∕TiN metal gate metal-oxide-semiconductor field effect transistor (MOSFET) compared to a polycrystalline silicon gate MOSFET. Physical analysis by transmission electron microscopy and electrical characterization shows that the ultrafast progressive breakdown is likely to be associated with a metal-like filament formation of the breakdown path. It has been observed that the metal-like filament of the breakdown path is detrimental to the metal gate MOSFET progressive breakdown lifetime.

The degradation and time-to-breakdown characteristics of thin (1.38 to 2.14 nm EOT) MOCVD HfSiON dielectrics with poly-Si gate were studied. We demonstrate that at elevated temperature the conduction mechanism remains direct tunneling and that for EOT below 1.5 nm charge trapping is no reliability issue. It is shown that similar to the case of SiON dielectrics, the degradation process is dominated by the formation of single localized conductions paths and that the total time-to-failure consists of two parts: the time-to-creation of a conductive path and the time until the wearout of this path has reached a critical threshold. The degradation rate of the progressive wearout is strongly voltage dependent. For thin (1.38 nm EOT) HfSiON we demonstrate that the time-to-creation even at operating condition is very small, but the overall TDDB reliability is guaranteed because of the large time-to-wearout.