Reliability-Aware FinFET Design

Authors :: M. Toledano-Luque
B. Zhu
B. Min
T. Nigam
P. Srinivasan
P. Paliwoda
S. Cimino
Z. Chbili
M. Iqbal Mahmud
A. Gupta
T. Shen
T. Kauerauf
Source :: 2019 Electron Devices Technology and Manufacturing Conference (EDTM).
Publication Year :: 2019
Publisher :: IEEE, 2019.
Abstract: The endless demand for high performance and low power CMOS devices at extremely scaled cell dimensions led the semiconductor industry to migrate to FinFET structures. This evolution has brought higher integration complexity and has forced the reliability engineers to be aware of interrelation among process conditions affecting electrical degradation and failure. In this work, major integration steps which impact FEOL/MOL reliability are discussed, and guidance is provided for reliability-aware FinFET design.

Subjects :: Semiconductor industry
CMOS
Computer science
Logic gate
Process conditions
Reliability engineering

Database :: OpenAIRE
Journal :: 2019 Electron Devices Technology and Manufacturing Conference (EDTM)
Accession number :: edsair.doi...........b0a6f5a0299168bfd30c0e08ab0b1f42
Full Text :: https://doi.org/10.1109/edtm.2019.8731235