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Vertically-stacked horizontal gate-all-around (GAA) Nanosheet structures have been recognized as good candidates for beyond the 7nm technology node to achieve improved power-performance and area scaling compared to FinFET technologies. Full realization of device-performance entitlement in high-performance and high-density chip designs is, therefore, of critical importance. In this paper, we present a quantitative performance evaluation of horizontal Nanosheet structures focused on key design styles as well as unique Nanosheet challenges such as gate-resistance. This analysis was performed with a fully developed design kit over a wide range of sub-7nm design, including various cell heights, as well as design features such as M1 power staples and performance-aware designs for smaller track cells.

This paper demonstrates the first reliable and low cost airgap BEOL technology, generated at extremely tight dimensions (48 nm pitch) in Cu/ULK. This provides 20% nested-line capacitance reduction relative to the ungapped Cu/ULK baseline. This result is of critical importance, as it validates that airgaps can be extended down to ultrafine wire levels, such as for the 10 nm technology node. Current technologies implement airgaps only at fat-wire levels; however, a significant enhancement in chip performance can be gained by including airgaps in the finest wiring levels as well. To achieve this, we benefitted from several elements which address various process, integration, and reliability challenges associated with airgap formation at such small dimensions. We present data and explanations of these solutions, and their impacts on yield, performance, defectivity and reliability (EM and TDDB).

SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1–4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1–4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.

The promise of improved electrostatics and the ability to increase the amount of effective width (Weff) available in a given device footprint drove the semiconductor industry from planar CMOS transistors to the FinFET transistor starting at the 22 nm node [1]. Numerous manufacturers are in large-scale production of 16 and 14 nm node FinFET technologies [2-3] and there is no indication that a change in device architecture is planned for the 10 or 7 nm nodes [4]. Looking beyond 7 nm, the scaling challenges of the FinFET are expected to increase dramatically. In particular, continued scaling of the fin width and fin pitch may reach a physical limit due to a combination of quantum effects, patterning process [5] realities and contact architecture limitations [6]. It is well known that gate-all-around (GAA) devices demonstrate improved electrostatics over double or triple-gated FinFET devices [7]. In view of the impending difficulties occasioned by FinFET scaling, it is necessary to take a critical look at the possibility of a GAA CMOS device technology. In this paper, I will explore this topic by presenting relevant TCAD and experimental work on single and stacked GAA devices. The TCAD illustrates that a properly designed stacked GAA device architecture can show superior performance over a scaled FinFET reference. I will conclude by presenting experimental work to substantiate this claim.

FinFET has become the mainstream logic device architecture in recent technology nodes due to its superior electrostatic and leakage control [1,2,3,4]. However, parasitic capacitance has been a key performance detractor in 3D FinFETs. In this work, a novel low temperature ALD-based SiBCN material has been identified, with an optimized spacer RIE process developed to preserve the low-k value and provide compatibility with the down-stream processes. The material has been integrated into a manufacturable 14nm replacement-metal-gate (RMG) FinFET baseline with a demonstrated ∼8% performance improvement in the RO delay with reliability meeting the technology requirement [4]. A guideline for spacer design consideration for 10nm node and beyond is also provided based on the comprehensive material properties and reliability evaluations.

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.

We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive device performances are achieved with effective drive currents of I eff (N/P) = 621/453 μA/μm at I off = 10 nA/μm at V DD = 0.8 V. The BOTS process results in a sloped fin profile at the fin bottom (fin tail). By extending the gate vertically into the fin tail region, the parasitic short-channel effects due to this fin tail have been successfully suppressed. We further demonstrate the extension of the BOTS process to the fabrication of strained SiGe FinFETs and nanowires, providing a path for future CMOS technologies.

A first time rigorous experimental study of effective current (Ieff) variability in high-volume manufacturable (HVM) 14nm Silicon-On-Insulator (SOI) FINFETs is reported which identifies, threshold voltage (Vtlin), external resistance (Rext), and channel trans-conductance (Gm) as three independent sources of variation. The variability in Gm, Vtlin (AVT=1.4(n)/0.7(p) mV-μm), and Ieff exhibit a linear Pelgrom fit indicating local variations, along with non-zero intercept which suggests the presence of global variations at the wafer level. Relative contribution of Gm to Ieff variability is dominant in FINFETs with small number of fins (Nfin); however, both Gm and Rext variations dominate in large Nfin devices. Relative contribution of Vtlin remains almost independent of Nfin. Both n and p FINFETs show the above mentioned trends.

Threshold voltage variability in Fully Depleted MOSFETs transistors is usually much better than in bulk devices because of the suppression of channel doping. This paper reviews in details the specificities of variability in such devices and highlights that SOI boosters (such as back bias or embedded strain in the substrate) do degrade the matching properties.

Recent UTBB device data at sub-25nm gate length demonstrate good performance, small V T variation and excellent low power operation. In addition, very uniform Soitec Xtreme SOI™ product substrates are now available and compliant with device requirements. Thus the level of maturity of UTBB devices and substrates makes it possible for introduction at 20nm node. Multiple options at the substrate level to further boost the performance open up the path to improve performance for future nodes.

A common platform technology at 65 nm is described. The platform consists of a low-power CMOS base technology with a broad menu of optional features including high- performance passive devices, standard cell libraries, SRAM compilers and a process design kit enabling custom design. These elements enable competitive leadership technology for ASICs and Foundry applications, resulting in a highly competitive technology that is an excellent choice when performance and cost must be balanced.

We present transistor and technology design considerations specific to low power applications from 90mn to 45nm and beyond. We discuss static power and Low Standby Power (LSTP) transistors, and also touch on dynamic power dissipation and Low Operating Power (LOP) transistors. As semiconductor transistor technology is encountering several intransigent limits (voltage scaling and overdrive, and gate leakage in particular), cost-effective means of producing superior chips will be enhanced by chip design techniques as much or more than by silicon technology elements.

The polysilicon gate linewidth manufacturing control strategy typically includes an electrical resistance measurement to extract the gate dimension. The extraction method usually assumes that wide (reference) and narrow (gate dimension) resistors have the same absolute sheet resistance. However, upon deeper examination, we found that this assumption is frequently invalid, submicron resistors do not necessarily have the same sheet resistance as wide resistors. Moreover, N-type and P-type narrow resistors exhibit quite divergent behaviors.

Understanding the reliability implications for silicon-on-insulator (SOI) is crucial for its use in ULSI technology. The fabrication process of SOI material and the device operation, due to the buried oxide (BOX) layer, could present additional concerns for meeting reliability requirements. In this paper, we discuss the reliability issues with silicon-on-insulator (SOI) technology. We focus on partially depleted (PD) SOI CMOS technology using SIMOX and bonded substrate material. We compare the reliability mechanisms, namely channel hot electron (CHE), gate oxide time dependent dielectric breakdown (TDDB), bias temperature stress (BTS) and plasma-induced charging damage, to bulk CMOS. In addition, results from high performance microprocessors subjected to burn-in stress are presented. Finally, we discuss the circuitry implications for electrostatic discharge (ESD).

The objectives and functions of payments systems in centrally planned economies are described and analyzed. These are compared to those of payments systems in market economies and to the characteristics of an ideal payments system. The dominant role of the state in the centrally planned economies meant that the state underwrote virtually all payments risk. With the withdrawal of the state, however, participants became exposed to credit, liquidity, and operational risks. In the transition, the central bank has a key role to play in payments systems. Areas where rapid improvements are possible are: accounting, clearing, settlement, netting and standardization.

The stimulus for this review and study was the report of experimentally produced esophageal burns in animals secondary to Clorox® ingestion which was reported by previous investigators in Chicago. Twenty-six children have been admitted to Children's Memorial Hospital since 1969 with “bleach ingestion” as the diagnosis. All but six underwent esophagoscopy in compliance with a “Pediatrics-Otorhinolaryngology Study Protocol” in an attempt to diagnose esophageal burns. Chemical burn of the esophagus was found in only one case; however, the exact content of ingested material was not definitely identified. In the one case of chemical burn, treatment was performed per protocol, and the patient is free of symptoms of stricture eighteen months postingestion. None of the other twenty-five patients have returned for treatment of ingestion sequelae. A laboratory study was conducted which utilized cats to simulate Clorox® ingestion by children. The cats were sacrificed at varying periods of time following ingestion with gross and microscopic exam of each esophagus being performed. Results showed the potential of chlorine bleach to cause chemical burns and superficial ulceration, but no stricture or residual sequelae when ingested in a manner simulating physiologic swallowing. Appropriate conclusions were made in respect to treatment of future patients with the diagnosis of “bleach ingestion.”

The author presents a brief survey of the uses of copper alloys as welding materials in industrial applications. In general, the survey includes three distinct fields: (a) Joining of copper alloys by various brazing and welding methods; (b) joining of ferrous and other metals by copper-alloy weld metal; and (c) building up wear- and corrosion-resisting surfaces of copper alloys. The discussion is confined principally to the use of copper-alloy welding. Several of the applications cited are taken from published reports of different investigators, and references are given where details involved in copper-alloy welding may be found.

Composite materials are often used as damping treatments or structural materials to mitigate the effects of unwanted vibration and sound. Recent work on materials displaying a negative Poisson’s ratio, known as auxetic materials, indicate that composite materials consisting of a lossy matrix containing auxetic inclusions may lead to improved vibro-acoustic absorption capacity compared to composites containing positive Poisson’s ratio inclusions. This work presents ultrasonic measurements of an epoxy matrix material (Epon E828/D400) containing volume fractions of α-cristobalite inclusions ranging from 5% to 25% by volume. The effective frequency dependent speed of sound and attenuation coefficient of each sample is measured from 1 to 10 MHz using ultrasonic immersion techniques. Ultrasonic test results are compared with Dynamic Mechanical Thermal Analysis and modal damping measurements of stiffness and loss behavior. This material is based upon work supported by the U. S. Army Research Office under grant number W911NF-11-1-0032.