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The performance of a hardware accelerator is often limited by the communication bandwidth between local on-chip memories and DRAM across on-chip bus. In this paper, a system-level performance estimation algorithm is newly proposed for evaluating the communication performance of direct memory access (DMA) controlled accelerators. The proposed algorithm can estimate the communication performance accurately for both DRAM-limited and bus-limited cases. In detail, the communication performance for the DRAM-limited case is estimated using dynamic prediction of DRAM command patterns whereas the communication performance for the bus-limited case is estimated based on the maximum bus burst latency. Depending on whether the communication bandwidth is limited by the bus protocol overhead or the DRAM latency, the proposed algorithm estimates the communication bandwidth of a DMA-controlled accelerator according to the performance bottleneck. It is shown that the proposed algorithm significantly improves the estimation accuracy when it is applied to CNNs and wireless communications. Also, when the proposed algorithm together with a full-system simulator is used to explore a design space defined by a set of tile sizes and bus-related parameters, it speeds up conventional algorithms by more than a factor of 100 by filtering out a large number of unpromising design points. It is also shown that the proposed algorithm alone can approach the maximum accelerator performance with a performance degradation of less than 5%. An ablation study is applied to prove the efficacy of individual steps of the proposed algorithm.

A digital front-end with digital compensation is designed and implemented for low-complexity 4G radio transceivers targeted for wearable devices such as smart watches. The proposed digital front-end in the radio receiver consists of an anti-drooping filter, a decimation chain, a DC offset cancellation circuit, and an in-phase and quadrature estimation and compensation circuit whereas the digital front-end in the radio transmitter includes an anti-drooping filter, a root raised cosine filter, and an interpolation chain. The proposed DC offset cancellation circuit is based on both infinite-duration impulse response filter and moving average. The proposed in-phase and quadrature estimation and compensation circuit attains lower complexity with negligible performance loss, compared with an existing circuit. A systematic top-down strategy is taken to design and implement the proposed digital front-end from the algorithm level to the application-specific integrated circuit or ASIC hardware level. The inter-symbol interference in the transmitter and the receiver is analyzed and the unwanted emission in the transmitter is simulated as well. For all the seven bandwidths or modes in 3G and 4G, the digital front end receiver ASIC satisfies all the interference requirements, namely, in-band blocker, narrowband blocker, and adjacent channel selectivity requirements whereas the digital front end transmitter ASIC meets all the unwanted emission requirements, namely, spectrum emission mask, spurious emission, and adjacent channel leakage ratio requirements. The proposed multimode 4G digital front end receiver and transmitter ASICs exhibit a >40dB mean signal-to-noise ratio for all the seven modes and are implemented in a 180nm CMOS process technology.

To effectively compute convolutional layers, a complex design space must exist (e.g., the dataflow techniques associated with the layer parameters, loop transformation techniques, and hardware parameters). For efficient design space exploration (DSE) of various dataflow techniques, namely, the weight-stationary ( WS ), output-stationary ( OS ), row-stationary ( RS ), and no local reuse ( NLR ) techniques, the processing element (PE) structure and computational pattern of each dataflow technique are analyzed. Various performance metrics are calculated, namely, the throughput (in giga-operations per second, GOPS), computation-to-communication ratio ( CCR ), on-chip memory usage, and off-chip memory bandwidth, as closed-form expressions of the layer and hardware parameters. In addition, loop interchange and loop unrolling techniques with a double-buffer architecture are assumed. Many roofline model-based simulations are performed to explore relevant dataflow techniques for a wide variety of convolutional layers of typical neural networks. Through simulation, this paper provides insights into the trends in accelerator performance as the layer parameters change. For convolutional layers with large input and output feature map ( ifmap and ofmap ) widths and heights, the GOPS of the NLR dataflow technique tends to be higher than that of the techniques. For convolutional layers with low weight and ofmap widths and heights, the RS dataflow technique achieves optimal GOPS and on-chip memory usage. In the case of convolutional layers with small weight widths and heights, the GOPS of the WS dataflow technique tends to be high. In the case of convolutional layers with small ofmap widths and heights, the OS dataflow technique achieves optimal GOPS and on-chip memory usage.

With a target to maximize the throughput, a fast link rate adaptation algorithm for IEEE 802.11a/b/g/n/ac is proposed, which is basically preamble based and can adaptively compensate for the discrepancy between transmitter and receiver radio frequency performances by exploiting the acknowledgment signal. The target system is a 1 &times, 1 wireless local area network chip with no null data packet or sounding. The algorithm can be supplemented by automatic rate fallback at the initial phase to further expedite rate adaptation. The target system receives wireless channel coefficients and previous packet information, translates them to amended signal-to-noise ratios, and then, via the mean mutual information, selects the modulation and coding scheme with the maximum throughput. Extensive simulation and wireless tests are carried out to demonstrate the validity of the proposed adaptive preamble-based link adaptation in comparison with both the popular automatic rate fallback and ideal link adaptation. The throughput gain of the proposed link adaptation over automatic rate fallback is demonstrated over various packet transmission intervals and Doppler frequencies. The throughput gain of the proposed algorithm over ARF is 46% (15%) for a 1-tap (3-tap) channel over 10 m&ndash, 250 m (16 m&ndash, 160 m) normalized Doppler frequencies. Assuming a 3-tap channel and 30 m&ndash, 50 m normalized Doppler frequencies, the throughput of the proposed algorithm is about 31 Mbps, nearly the same as that of ideal link adaptation, whereas the throughput of ARF is about 24 Mbps, leading to a 30% throughput gain of the proposed algorithm over ARF. The firmware is implemented in C and on Xilinx Zynq 7020 (Xilinx, San Jose, CA, USA) for wireless tests.

A low-power mixed-signal phase-locked loop (PLL) is modelled and designed for the DigRF interface between the RF chip and the modem chip. An assisted-GPS or A-GPS multi-standard system includes the DigRF interface and uses the split automatic frequency control (AFC) technique. The PLL circuitry uses the direct AFC technique and is based on the fractional-N architecture using a digital delta-sigma modulator along with a digital counter, fulfilling simple ultra-high-resolution AFC with robust digital circuitry and its timing. Relative to the output frequency, the measured AFC resolution or accuracy is

A composite radio receiver back-end and digital front-end, made up of a delta-sigma analog-to-digital converter (ADC) with a high-speed low-noise sampling clock generator, and a fractional sample rate converter, are proposed and designed for a multi-mode reconfigurable radio. The proposed radio receiver architecture contributes to saving the chip area and thus lowering the design cost. To enable inter-radio access technology handover and ultimately software-defined radio reception, a reconfigurable radio receiver consisting of a multi-rate ADC with its sampling clock derived from a local oscillator (LO), followed by a rate-adjustable fractional sample rate converter for decimation, is designed. Clock phase noise and timing jitter are examined to support the effectiveness of the proposed radio receiver. A fractional sample rate converter is modeled and simulated with a cubic polynomial interpolator based on Lagrange method and its spectral-domain view is examined in order to verify its effect on al...

A novel latency-insensitive controller architecture is proposed for a convolutional neural network (CNN) accelerator. It is shown that the proposed architecture not only guarantees the correct operation, regardless of memory latency, but also maximizes the performance. The implementation results show that the latency-insensitive controller occupies only a negligible fraction of the total area.

Sparse CNN (SCNN) accelerators tend to suffer from the bus contention of its scatter network. This paper considers the optimizations of the scatter network. Several network topologies and arbitration algorithms are evaluated in terms of performance and area.

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embeddedsystems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, externalmemory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASICfront-end gate netlist level using a 0.18μm digital CMOS technology with 1.8V supply, resulting in a gate count ofmerely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and appliedto deeply embedded IoT applications.

In this letter, the accuracy of the reference signal received power (RSRP) measurement carried out by an LTE user equipment (UE) is analyzed. Assuming the measurement based on the averaged frequency-domain maximum likelihood estimate (FD-MLE), the closed-form expressions of the mean-error and mean-squared-error (MSE) are obtained to show the impact of the channel parameters, the cell ID, the subset size, and the signal-to-interference-plus-noise ratio (SINR). The numerical calculation results based on the closed-form expressions show that the optimum subset size tends to decrease with the SINR and delay spread.

A decimation chain for multi-standard reconfigurable radios is presented for 900-MHz and 1,900-MHz dual-band cellular standards with a data interpolator based on the Lagrange method for adjusting the variable data rate to a fixed data rate appropriate for each standard. The two proposed configurations are analyzed and compared to provide insight into aliasing and the signal bandwidth by means of a newly introduced measure called interpolation error. The average interpolation error is reduced as the ratio of the sampling frequency to the signal BW is increased. The decimation chain and the multi-rate analogto-digital converter are simulated to compute the interpolation error and the output signal-to-noise ratio. Further, a method to operate the above-mentioned chain under a compressed mode of operation is proposed in order to guarantee continuous packet connectivity for inter-radio-access technologies. The presented decimation chain can be applied to LTE, WCDMA, GSM multi-mode multi-band digital front-end which will ultimately lead to the software-defined radio.

Frequency detector is a circuit that converts the frequency to a digital representation and finds its application in various fields such as modulator and synchronization circuitry. In this paper, a couple of first-order and second-order frequency discriminator structures are modeled and analyzed with their quantization noise sources. Also a delta-sigma frequency detector architecture is proposed. Through theoretical analysis and derived equations, the output noise is obtained, which is validated by simulation. The proposed all-digital frequency discriminator may be applied in the feedback path of the all-digital phase-locked loop.

In this paper, a study on the demagnetization of ferromagnetic materials is conducted based on both experiments with magnetic treatment facility (MTF), which is a miniaturized experimental model, and numerical analysis methods in which the static magnetic finite-element method and Preisach model are combined. The magnetic hysteresis phenomenon inside ferromagnetic materials is effectively mimicked by means of Preisach model. However, owing to the use of $M\hbox{-}H$ variables, Preisach model generally bears numerical instability during repetitive computations. A Preisach model with $M\hbox{-}B$ variables is proposed in this paper to resolve the numerical instability. From the proposed Preisach model with $M\hbox{-}B$ variables, analysis results that were tantamount to those from the general Preisach model with $M\hbox{-}H$ variables were obtained. Numerical instability was also resolved by the proposed model. Furthermore, the discrepancy was practically negligible between the experimental result from a practical demagnetization process and the numerical analysis result from the proposed Preisach model with $M\hbox{-}B$ variables, under the same conditions.

Summary The application of the single-file technique using the reciprocating motion is gaining concern in root canal preparation. The purpose of this research is to compare the efficiency of the reciprocating motion-employing files (RECIPROC and WaveOne) by measuring the working time for complete canal shaping, and to evaluate their reusability under scanning examinations. One hundred curved root canals of the extracted molars were used. The working length was determined and the glide path was confirmed using a #15 K-file. Canals shaping was completed to the length either with RECIPROC R25 file (n = 50), or with WaveOne Primary file (n = 50). The time taken for the file to reach the working length was also measured. Each file was repeatedly used in a maximum of 10 canals for comparing the change of the efficiency (shaping time) according to the working length, canal curvature, and number of file re-use. The deformations or surface defects of the files after the in vitro use were observed using a scanning electron microscope (SEM). There was no difference under the SEM between the 2 file groups with no initiation of micro-cracks until they were re-used up to 5 canals. WaveOne Primary file showed significantly shorter working time than RECIPROC R25 (p

This tutorial paper presents the design methodology of system-level simulators targeted for code division multiple access (CDMA) cellular standards such as EV-DO (Evolution-Data Only) and broadcast multicast service (BCMCS). The basic structure and simulation flow of system-level simulators are delineated, following the procedure of cell layout, mobile drops, channel modeling, received power calculation, scheduling, packet error prediction, and traffic generation. Packet data transmissions on the forward link of CDMA systems and EV-DO BCMCS systems are considered for modeling simulators. System-level simulators for cellular standards are modeled and developed with high-level languages and utilized to evaluate and predict air interface performance metrics including capacity and coverage.

A high-speed electronic dispersion compensator (EDC) with adaptation functionality is proposed in this article. Adaptation is needed to adjust the compensation ratio adequately according to the time-varying polarisation-mode dispersion (PMD) which varies relatively slowly and leads to temporal intersymbol interference (ISI) and distortion. Assuming moderate ISI, the adaptation function is based on the modified LMS or sign-data LMS. The EDC is utilised in a 10-Gbps OC-192 fibre-optic receiver. Through removal or alleviation of the ISI, the EDC enables longer repeater-less span and higher data rates or lowered ISI penalty in Gbps-range fibre-optic communication systems. Experimental results are given using a 0.13 µm CMOS process with 1.2 V supply. The power drain of the overall circuitry is on the low side of 16 mW.

In this brief, design of a gigabit link CMOS analog interface composed of a transmitter, a receiver, and clocking circuits is addressed with focus on high-performance signaling in terms of interference and jitter. The low-cost, low-power interface is targeted at parallel link applications. The transmitter adopts one-tap preemphasis to mitigate the intersymbol interference (ISI) problem. The receiver samples two adjacent bits and stores the difference of them to a capacitor, so it is more immune to timing uncertainties caused by nonideal sampling clocks and it is dependent only on the direction or difference of two consecutive bits, not on the absolute values of them. With these circuits, robust clocking circuits to multiplex and demultiplex the data on the transmit and receive side, respectively, are designed. Pseudo-differential-type delay elements are used in the oscillator and delay line to enable high power supply rejection ratio and low jitter. The delay locked loop (DLL) is designed to prevent harmonic locking. The transceiver performance is tested at 1 Gbps and 2 Gbps for double and quadruple interleaving, respectively. The maximum operating speed is about 1.7 Gbps for double interleaving and about 3 Gbps for the quadruple-interleaving receiver under a 3.3 V, 0.35 ?m CMOS process.

A high-conversion-rate high-resolution oversampling digital-to-analog converter (DAC) for direct digital modulation is addressed in this paper. A new type of switching scheme, called differential-quad switching, is presented. To verify the feasibility of this scheme, essential parts with some auxiliary circuitry for interfacing were fabricated in a 0.8-/spl mu/m CMOS technology. Measured results show that the switching scheme provides 11-b resolution at 100 MSamples/s and 6-b at 1 GSamples/s. The degradation in signal-to-noise ratio is not observed for the variation of the supply voltage down to 1.5 V, which means the proposed scheme is suitable for low-voltage applications.

Deeply embedded applications demand small area, low power, high code density, and low design complexity for high adaptability. Both a 16-bit microprocessor with a 4G byte linear memory space and a 4-bit processor are proposed and designed to achieve these goals. Hardware reuse and sharing, multicycle architecture, compact instruction set architecture, and counter-based instruction decoder are utilized to reduce gate count. As a result, gate count and power dissipation of the synthesized ASIC gate-level netlists of 16-bit and 4-bit processors are less than 14,000, 1,490, 0.5[Formula: see text]m W, and 0.06[Formula: see text]m W, respectively, at 10[Formula: see text]MHz in a 0.18[Formula: see text][Formula: see text]m digital CMOS technology. The proposed 16-bit and 32-bit processors are extendable instruction set computers whose high code density is demonstrated to reduce code bytes by 40% over a reduced instruction set computer. The pipelined EISC processor only consumes 50[Formula: see text][Formula: see text]W/MHz with 10,800 gates in a 0.18[Formula: see text][Formula: see text]m CMOS process.

CMOS technologies are widely exploited now in the area of a few-GHz-range radio frequency (RF) circuits as well as in the area of baseband circuits. Accordingly, the CMOS low-noise amplifier (LNA) is gaining its popularity, tailored to the applications such as GSM, PCS, IMT-2000, and wireless LAN. In this paper, compact and comprehensive design strategies for CMOS LNA are presented. Basic topologies are compared and analyzed using key equations newly derived. Using these strategies, an LNA based upon LC resonance using on-chip spiral inductors is designed and investigated. This LNA, targeted for 1.8 GHz PCS, exhibits power gain of about 18 dB and noise figure (NF) of about 2.1 dB by both theory and post-layout simulation under a 0.8-/spl mu/m CMOS process and 3-V supply.

All-digital phase-locked loops (ADPLLs) based on the time-to-digital converter (TDC) and the frequency discriminator (FD) are modeled and analyzed in terms of quantization effects. Using linear models with quantization noise sources, theoretical analysis and simulation are carried out to obtain the output phase noise of each building block of the TDC-based ADPLL. It is newly derived that the TDC noise component caused by the delta-sigma modulator (DSM) and the finite resolution of the digitally controlled oscillator is not white. Namely, the in-band phase noise caused by the DSM-induced TDC is not white, which is due to the integrate-and-dump and subsampling operations of the TDC. This can give some insight into the design of low-noise ADPLLs. Some structures of delta-sigma FDs, which can serve as an alternative to the TDC, are also newly analyzed in terms of quantization noise, using the derived linear noise model.

Frequency dividers are used in frequency synthesizers to generate specific frequencies or clock (CK) waveforms. As consequences of their operating principles, frequency dividers often produce output waveforms that exhibit duty cycles other than 50%. However, some circuits and systems, including dynamic memory systems and data converters, which accommodate frequency divider outputs, may need symmetric or 50%-duty-cycle clock waveforms to optimize timing margins or to obtain sufficient timing reliability. In this review paper, design principles and methods are studied to produce symmetric waveforms for the in-phase (I) and quadrature (Q) outputs of high-speed CMOS frequency dividers with design considerations from the logic gate level down to the transistor level in terms of speed, reliability, noise, and latency. A compact and robust multi-gigahertz frequency divider with moduli 12, 14, and 16 to provide I and Q outputs with 50% duty cycle is proposed and designed using a 90-nm digital CMOS process technology with 1.2-V supply.

This paper proposed a detection process of effectively detecting an unknown frequency hopping signal in practical environments. For the detection process, the scanning receiver and direction finding receiver are used, and the frequency histogram, azimuth histogram and frequency versus azimuth diagram analyses are performed. The simulation results show that an unknown frequency hopping signal can be successfully extracted by the proposed detection process in practical environments.

This in vitro study monitored MMP-8 production on PMN by stimulated with the following three groups; Sonicated extracts of E. faecalis (SEF), SEF treated with Ca(OH)2 (12.5㎎/㎖) for 7 days, and lipopolysaccharides (LPS) of E. coli. The level of MMP-8 in each group was immediately measured by ELISA. The data were analyzed with Kruskal-Wallis test and Mann-Whitney U test. In the SEF group, the level of production of MMP-8 was higher than the negative control group in low concentration (0.05㎍/㎖) of SEF (p 0.05). All of the levels in E. coli LPS were increased with increasing concentrations (p < 0.05). According to this study we could summarize as follows: 1. MMP-8 was expressed at low level in untreated PMN group and the levels of MMP-8 were upregulated in PMN stimulated by E. coli LPS groups. 2. In the SEF groups, the level of production of MMP-8 decreased with an increase in the concentration of SEF (p < 0.05). So E. faecalis may have suppressive effect on the production of MMP-8 by PMN. 3. In the case of SEF treated with Ca(OH)2, all of the MMP levels at different SEF concentrations were higher than untreated PMN group (p < 0.05), but no statistical difference was found among the differ

A phase-locked loop (PLL) that is highly robust to supply/substrate noise is described. A new type of voltage-controlled oscillator (VCO) based on pseudo-differential delay elements is presented. The proposed circuit is implemented using a 0.35 /spl mu/m CMOS process technology with a 3.3 V supply. It generates 16 clock phases at 250 MHz, tailored to gigabit link applications.