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This paper describes the influence of water-related species contained in intermetal dielectric layer on the interpoly dielectric properties of nonvolatile memory devices. P-TEOS layer used as an intermetal dielectric enhances degradation of interpoly dielectric of nonvolatile memory devices due to the water-related components contained in the layer.

A fully calibrated 3-D simulation of a NAND flash string is used to characterize the source/drain hot carrier disturbance phenomenon for the first time. Through the word line 31 (WL31) program voltage (Vpgm) disturbances simulation with various pass voltage (Vpass) for other word lines, we conclude that the source/drain hot carrier injection contributes to an abnormal Vpgm disturbance not only at a 14-V Vpass, but also at 4-V Vpass condition. Instead of the well-known FN programming disturbance due to insufficient boosting potential at low Vpass, the GIDL-induced electron-hole pair generation at the source side (WL30) of WL31 and electron injection into the Vpgm-biased WL31 are the dominant mechanisms of the WL31 Vpgm disturbance in the ‘01’ state cell string at a 4-V Vpass condition. This hot carrier disturbance phenomenon is similar to that of the 14-V Vpass condition, even though it occurs on the drain side (SSL) of WL31.

Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (V/sub th/) distribution of the fabricated FinFET SONOS cells is fairly better than that of conventional flash cells thanks to both the widening effective channel width of FinFET structure and negligible coupling interference of SONOS device. New two-step channel implantation process has been introduced for the compensation for the boron out-diffusion of a three-dimensional silicon fin structure. The measured FinFET SONOS cells with a two-step channel doping profile show the improved program and erase characteristics. For the improvement of program/erase and retention characteristics all together, we have investigated the modulation of erase bias condition with respect to back tunneling effect.

A physically separated 2-bit SONOS memory with a single gate is fabricated for the first time. By forming physically separated 30-nm twin ONOs with an inverted sidewall spacer patterning method and damascene process under a merged-triple gate, the decrease of charge distribution and diffusion during and after CHEI (channel hot electron injection) program in 2-bit operation of the localized trap memory is observed in devices with the gate length of 90 nm. The inverted amorphous silicon spacer and the damascene gate process does not suffer from unit-cell size increase, lithographic resolution limit, and miss-alignment between gate and ONOs. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory (TSM) cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better 2-bit operation, endurance and retention than SSM, and absence of disturbance can be obtained in the short (sub 90 nm) gate length devices. � 2004 Elsevier Ltd. All rights reserved.

In this paper, we have fabricated nanoscale silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices by means of the sidewall patterning technique. The fabricated SONOS devices have a 30-nm-long and 30-nm-wide channel with 2.3/12/4.5-nm-thick oxide/nitride/oxide film on fully depleted-silicon-on-insulator (FD-SOI) substrate. The short channel effect is well suppressed though devices have very short channel length and width. Also, the fabricated SONOS devices guarantee good retention and endurance characteristics. In 30-nm SONOS devices, channel hot electron injection program mechanism is inefficient and 2-b operation based on localized carrier trapping in the nitride film is difficult. The erase speed is improved by means of band-to-band (BTB) assisted hole injection mechanism. In 30-nm SONOS devices, program and erase operation can be performed efficiently with improved erase speed by combination of Fowler-Nordheim (F-N) tunneling program and BTB assisted hole injection erase mechanism because the entire channel region programmed by F-N tunneling can be covered by two-sided hole injection from source and drain.

The island size dependence of the capacitance components of single-electron transistors (SETs) based on gate-induced Si islands was extracted from the electrical characteristics. In the fabricated SETs, the sidewall gate tunes the electrically induced tunnel junctions, and controls the phase of the Coulomb oscillation. The capacitance between the sidewall gate and the Si island extracted from the Coulomb oscillation phase shift of the SETs with sidewall depletion gates on a silicon-on-insulator nanowire was independent of the Si island size, which is consistent with the device structure. The Coulomb oscillation phase shift of the fabricated SETs has the potential for a complementary operation. As a possible application to single-electron logic, the complementary single-electron inverter and binary decision diagram operation on the basis of the Coulomb oscillation phase shift and the tunable tunnel junctions were demonstrated.

A patterning technique to define nanoscale multiple lines is developed and optimized using sidewall structure. About 50 nm poly-Si multiple lines, which have 70 nm as one of the narrowest space, are defined by sidewall multi-line patterning technique. These patterns have a good uniformity (deviation 1.5–4.7 nm). In addition, we can control line/space of patterns very easily by sidewall width control in this technique. And this is free from the proximity effect because of the process using sidewall hard mask. So, it is expected that the sidewall multi-line patterning technique can be applied to fabricate single electron devices, quantum devices, and other nanoscale devices.

Novel single-electron transistors with sidewall depletion gates on a silicon-on-insulator nano-wire have been fabricated by the conventional very large-scale integration technologies. The fabricated SETs show the controllable characteristics, which can be estimated from the device geometry. The electrically induced quantum dot is well defined in the intended spot and the fabricated SETs show reliable single-dot characteristics eliminating unintentionally formed potential barriers in a silicon-on-insulator nano-wire. Also, it shows multiple Coulomb oscillation peaks with a constant period, overcoming the drawbacks of the previously reported SETs based on electrically induced quantum dot. The Coulomb oscillation phase control and voltage gain larger than unity are the promising properties of our devices for practical circuit application.

The room temperature-operation of a single-electron metal-oxide-semiconductor (MOS) memory with a defined quantum dot fabricated by sidewall patterning technique based on conventional VLSI technologies has been demonstrated without the aid of electron beam (EB) lithography for the first time. Sidewall patterning technique shows a good uniformity and controllability as well as high throughput. The fabricated memory devices show quantized threshold voltage shifts at room temperature. Time-dependant measurement of drain current shows discrete electron injection to the quantum dot. In addition, fabricated devices have good subthreshold swing and retention characteristics.

Novel single-electron transistors (SETs) with side-wall depletion gates on a silicon-on-insulator nanometer-scale wire are proposed and fabricated, using the combination of the conventional lithography and process technology. Clear Coulomb oscillation originated from the two electrically induced tunnel junctions and the single Si island between them is observed at 77 K. The island size dependence of the electrical characteristics shows the good controllability and reproducibility of the proposed fabrication method. Furthermore, the device characteristics are immune to gate bias conditions, and the position of Coulomb oscillation peak is controlled by the sidewall depletion gate voltage, without the additional gate electrode. Based on the current switching by sidewall gate voltage, the basic operation of the dynamic four-input multifunctional SET logic circuit is demonstrated at 10 K. The proposed SET offers the feasibility of the device design and optimization for SET logic circuits, in that its device parameters and circuit parameters are controllable by the conventional VLSI technology.

We investigate the retention reliability of a 51-nm-node 16-GB nand Flash cell transistor comprising SiO2/AlxOy/SiO2 inter-poly dielectric (OAO IPD). Despite the fact that OAO IPD retains low trapping rate being beneficial to retention reliability, the trap sites are located on shallow energy level, yielding a large amount of trap-assisted tunneling current at high temperature. Therefore, experimental results show two incompatible data retention characteristics of OAO IPD, namely, 33% worse V TH shift at 200°C 2-h bake and 53% improved V TH shift after one week at 25°C, when compared to the case of ONO IPD.

The effects of trap layer on NAND flash performances have been described in this paper. In order to overcome the slower programming speed of the discrete trap memory than conventional floating-gate device, nitride and silicon nanocrystal have been assembled together so as to provide the higher trap density for the improved device performance. This hybrid trap layer technology has been applied to the fin-type field-effect transistor (FinFET) NAND flash, and the results show ~5 V of program/erase window with reasonable device reliabilities.

A first multilevel vertical-channel silicon-oxide-nitride-oxide-silicon (MLVC-SONOS) memory cell is proposed and fabricated using 0.12-μm silicon-on-insulator (SOI) standard logic process for Flash memory cell with ultrahigh density. If NAND array structure is used, the unit cell size of MLVC-SONOS is 4F2. Further reduction of cell size is possible by using the multilevel concept which is originated from the steady states by two carrier transports from both the substrate and the gate. The program threshold voltages and their windows are uniform and controllable depending on the negative gate bias conditions. In addition, we propose a new endurance measurement method for multilevels and report the retention characteristics for multilevel memory operation.

Negative-differential transconductance characteristics at room temperature with a peak-to-valley ratio of about two were observed in 30-nm square-channel silicon-on-insulator nMOSFETs with degenerately doped bodies. High channel-doping concentration creates the degeneracy in the p-type body of the self-aligned SOI MOSFET and consequently, enables band-to-band tunneling between degenerate body and source-drain. I/sub DS/-V/sub DS/ curves in the negative drain bias region also show band-to-band tunneling current as in the case of forward-biased p-n tunnel junctions.

A highly manufacturable multi-level NAND flash memory with a 27nm design rule has been successfully developed for the first time. Its unit cell size is 0.00375um2 (with overhead). Self Aligned Reverse Patterning is used to improve initial Vth distribution induced from DPT (Double Patterning Technology) process. By using advanced channel doping technique, the channel junction leakage is minimized and the Vpass window is improved. The optimized doping structure and cell operation scheme are evaluated. And finally 2 and 3bit per cell operation are successfully demonstrated with flash cells of 32Gb density with reasonable reliability.

Gate-all-around (GAA) MOSFET with single silicon nanowire is fabricated and applied to SONOS memory as a cell transistor for NAND flash string. Driving current over 1 uA, which is sufficient to NAND string, is obtained with single nanowire of ~7 nm width. Using FN tunneling conditions, VTH window of 4.5 V and fast program/erase (P/E) speed of ~10 us are obtained, respectively. The smaller nanowire width is, the faster program speed and the larger VTH shift are achieved. P/E operations in NAND string with GAA SONOS nanowire are demonstrated for the first time.

In this paper, we report the enhanced performance of multi-giga bit NAND flash memory through the combined effects of uniaxial compressive stress and -oriented channel engineering. Using this method, cell current increased more than 29% owing to the mobility enhancement of the narrow width (60 nm) flash cell. Reduced interface trap with the active edge of channel resulted in the endurance characteristic improvement ~5%.

In terms of nonvolatile memory device characteristics, the optimal device parameters for the TWISTOR (twin SONOS transistor) structure are investigated. Through this study, we show the best performance of 80nm gate TWISTOR device, which are very promising solution of future 2-bit/cell SONOS technology

This paper presents the trap layer engineered body-tied FinFET device for MLC NAND flash application. The device design parameters for high density NAND flash memory have been considered, and the advantages of FinFET structure and high-k blocking dielectric in such device have been demonstrated. Based on the WN nano-dot memory device, the trap layer engineering using nitride layer has been performed, and the results show that the memory window is improved from 2.6 V to 7.8 V by utilizing engineered trap layer at 14 MV/cm F-N programming, and it is proposed as a possible MLC NAND device structure

The lateral charge distribution on 2-bit SONOS memory can be readily characterized using physically separated twin SONOS structure. The damascene gate and outer sidewall process successfully contribute to make the twin SONOS structure down to 80nm gate regime. Its lateral charge distribution is estimated through the SS and V/sub th/ shifts for forward and reverse reading and confirmed by the comparison with a conventional (non-separated) SONOS structure.

For the multi-gigabit NAND flash memory, SONOS-type FinFET device with p+ gate and high-k blocking dielectric has been integrated both on the cell array and GSL/SSL for the first time. The advantages of the FinFET structure for the NAND flash application have been theoretically and experimentally demonstrated, and the results show that the 85 % improved on-cell current is achievable using FinFET device. The enhanced programming and retention characteristics of FinFET have been also presented, and modeled by the potential changes on fully-depleted body of the sub-40 nm ultra-narrow fin

This paper presents the retention reliability of the FinFET SONOS Flash memory. By understanding the charge loss mechanisms of the SONOS structure, a new approach for the prediction of long term retention lifetime have been proposed. The comparison between the thermal-accelerated and field-accelerated lifetime has been demonstrated.

In this paper, we fabricated a BT-FinFET SRAM device with the smallest cell size of 0.46 /spl mu/m/sup 2/. And a hot carrier generation mechanism in the FinFET is thoroughly evaluated by measuring the I/sub sub/ of the BT-FinFET for various Si fin widths (20/spl sim/70 nm). For the first time, we revealed the mechanism of improved hot carrier immunity of sub 50 nm fin type MOSFETs.

The 3D MOSFET have been recognized as the main technology to substitute planar MOSFET beyond 50 nm. The development of various test structures is required to evaluate the characteristics of the new dimension. FinFET having 0, 45/spl deg/ rotated active directions from flat zone were evaluated, because those are critical for Si orientation of surface channel on the fin. In this paper, the performance and the reliability evaluation of 3D FinFET were performed by using two different test structures. The body tied FinFET having two different rotation angles /spl theta/=0, 45/spl deg/ were designed. The "/spl theta/" indicates the angle between the channel direction of the FinFET and the flat zone. The electrical characteristics and reliability of the FinFET /spl theta/(45/spl deg/) were measured and compared to those of the FinFET /spl theta/(0/spl deg/).

We report for the first time on 256Mb NOR-type body tied FinFET flash memory using Hf silicate IPD (inter poly dielectric) and compare with FinFET flash memory using traditional ONO IPD. An enlarged coupling ratio through Hf silicate IPD enhanced a CHEI (channel hot electron injection) programming speed and made the operation voltage down. And we could obtain a higher erasing speed resulted from HHI (hot hole injection) erase than that of F-N tunneling without degrading endurance characteristics.

We successfully demonstrate highly scaled damascene gate FinFET SONOS memory implemented on bulk silicon wafer. The FinFET SONOS devices show extremely high program/erase speed, large threshold voltage shifts over 4V at 1/spl mu/s/12V for program and 50/spl mu/s/-12V for erase, good retention time, and acceptable endurance. Thus, in sub-50nm regimes, ultra high speed operation becomes possible by using FinFET SONOS structure without sacrificing retention time.

80nm damascene-finFET (d-finFET) 512M DRAM is fabricated on bulk channel directional wafer (CW). We adopted damascene technology to form the fin only to the channel region of cell array transistor with self-aligned LCI (local channel ion implantation). From the reduced contact resistance, surface treatment, and electron mobility improvement of CW, 50% increased on-current is achieved in d-finFET. Utilizing LCI to d-finFET, junction leakage of the storage node has been reduced. The characteristics of d-finFET and conventional finFET (c-finFET), and CW and CW were compared. Using the d-finFET scheme with LCI, data retention time is further improved from the previous work of c-finFET (Lee et al., 2004).

We present a 2-bit/cell SONOS memory transistor and investigate its scalability and reliability beyond 50nm NVM technology. This new memory, which is implemented by the damascene gate and our newly developed outer sidewall spacer processes, shows not only stable 2-bit operation but also high reliabilities (>10/sup 5/ endurance and good retention at 150/spl deg/C) down to 80nm gate length that applies to next-generation NVM technology. In addition, dimensional effect (the lateral distance between two storage nodes) on the memory operation is reported to estimate the ultimate scaling limit of 2-bit/cell SONOS memory transistor.

For the breakthrough of scaling limit, simple structure memories are developed and also multi-bit operation memories are introduced concurrently. A new TSM-ISP cell which has 30 nm local twin SONOS memory separated by the inverted sidewall patterning method under the 90 nm merged-triple gate. This new cell structure provides perfect 2-bit program, excellent endurance, erase characteristics and retention compared with the conventional single ONO type SONOS in the sub-90-nm regime.

A new VC-SONOS (vertical channel SONOS) memory cell structure is proposed and fabricated using a 0.12 /spl mu/m SOI standard logic process for a next generation flash memory cell with ultra high density. This fabricated VC-SONOS memory cell, which has 57 nm wide vertical channels and 15 /spl Aring/ tunnel gate oxide, shows not only scaling breakthrough beyond 0.10 /spl mu/m flash memory but also multi-level operation with negative programming voltages.

For practical application to multi-functional nanoelectronic devices, single electron transistors (SETs) should have controllable and reproducible characteristics. For high temperature operation, recently proposed SET structures have depended on somewhat contingent phenomena such as unintentional potential barriers in quantum wires, e-beam irregularity or randomly distributed nanocrystal arrays, so that their device characteristics couldn't be predicted. In this work, SETs with sidewall depletion gates on a silicon-on-insulator (SOI) quantum wire have been fabricated by the combination of conventional lithography and VLSI technology, and their properties were investigated.

A patterning technique to define nanoscale multiple lines is developed and optimized using sidewall structure. In this experiment, sidewall multi-line patterning technique makes it possible to realize about 50nm poly-Si lines which have 70nm as the narrowest space. This technique is a proximity effect free fabrication process, so it is expected that the sidewall multi-line patterning technique can be applied to fabricate single electron devices, quantum devices, and other nanoscale devices.

A nonlinear feedback system is designed and analyzed for a surface micromachined resonant accelerometer. For this, a brief illustration of the plant dynamics is given. In the analysis, the periodic signal in the nonlinear feedback loop is obtained by the limit cycle point, which is best approximated via the describing function method. This approach is reasonable in that the describing function method gives the optimal quasi-linearization for a sinusoidal input under an adequate filtering condition. In the sequel, it is possible that the nonlinearity form in the loop is determined by the graphical analysis in complex plane. Considering the characteristic feature of plant dynamics, a simple phase shifted relay with finite slope is found for the nonlinearity implementation. Also is concisely illustrated the stability of limit cycle. Finally, simulation and experimental result is given to show the properness of the designed loop.

Novel single-electron transistors with sidewall depletion gates on a silicon-on-insulator nano-wire have been fabricated by the conventional very large-scale integration technologies. The fabricated SETs show the controllable characteristics, which can be estimated from the device geometry. The electrically induced quantum dot is well defined in the intended spot and the fabricated SETs show reliable single-dot characteristics eliminating unintentionally formed potential barriers in a silicon-on-insulator nano-wire. Also, it shows multiple Coulomb oscillation peaks with a constant period, overcoming the drawbacks of the previously reported SETs based on electrically induced quantum dot. The Coulomb oscillation phase control and voltage gain larger than unity are the promising properties of our devices for practical circuit application.

Thanks to the combination of damascene gate and outer poly-Si sidewall spacer process, we have successfully fabricated twin silicon–oxide–nitride–oxide–silicon (SONOS) memory (TSM) transistors with 20-nm twin nitride storage nodes under an 80-nm gate. In terms of device manufacturability, the damascene gate process makes it possible to realize physically separated structure and the outer poly-Si sidewall spacer scheme contributes to realization of 20-nm long nitride storage node. Compared with conventional SONOS transistor, the fabricated TSM transistor maintains its threshold voltage margin between the forward and reverse reads down to 80-nm long gate. The TSM transistor also shows stable and reliable characteristics: up to 105 program/erase cycles endurance and fairly good bake retention at 150°C.

We have developed a patterning technique to define ultrafine lines with high density and good uniformity using sidewall structures. Approximately 50 nm multiple lines, which have 70 nm as the narrowest space between the lines, are defined by the pattern multiplication technique. Linewidths are measured at several points on wafers and their uniformity is verified. These patterns have a good uniformity (deviation 2.26–4.35 nm). Also, die-to-die uniformity is very good. The advantage of this technique is the easy control (using sidewall width control) of the line and space of patterns. This technique is free from the proximity effect because of the process using a sidewall hard mask. Thus, it is expected that the pattern multiplication technique can be applied to fabricate single electron devices, quantum devices, and other nanoscale devices.

Basic operation of a dynamic exclusive-OR gate implemented by a field effect transistor and a single-electron transistor is experimentally demonstrated, for the first time. Logic output voltage shows full swing operation at a supply voltage of 20 mV. Fabricated single-electron transistors are advantageous for implementing a multi-gate single-electron logic circuit.