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Damascene gate FinFET SONOS memory implemented on bulk silicon wafer

Authors :
J.-D. Choe
Donggun Park
Min Sang Kim
Ming Li
Yong Kyu Lee
Kyoung Hwan Yeo
Suk Kang Sung
Sung Dae Suk
Chang Woo Oh
Dong-Won Kim
Dong-uk Choi
Sung-min Kim
Sung-young Lee
Eun-Jung Yoon
Sung Hwan Kim
Kinam Kim
Byung-Il Ryu
Source :
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
Publication Year :
2005
Publisher :
IEEE, 2005.

Abstract

We successfully demonstrate highly scaled damascene gate FinFET SONOS memory implemented on bulk silicon wafer. The FinFET SONOS devices show extremely high program/erase speed, large threshold voltage shifts over 4V at 1/spl mu/s/12V for program and 50/spl mu/s/-12V for erase, good retention time, and acceptable endurance. Thus, in sub-50nm regimes, ultra high speed operation becomes possible by using FinFET SONOS structure without sacrificing retention time.

Details

Database :
OpenAIRE
Journal :
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.
Accession number :
edsair.doi...........5cc5e5efa9f87341f4aaf5e3febd0f48
Full Text :
https://doi.org/10.1109/iedm.2004.1419324