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Linarity analysis of nanoscaled devices is a vital issue as nonlinearity behaviour is exhibited by them when employed in circuits for microwave and RF applications. In this work a junctionless surrounded gate graded channel MOSFET (JLSGGC MOSFET) is investigated thoroughly to analyse its linearity performance with the help of ATLAS tool of technology computer aided design (TCAD). The proposed device is compared systematically with the conventional junstionless surrounded gate MOSFET(JLSG MOSFET) to investigate their linearity. To evaluate the linearity, the figure of merits (FOMs) such as higher order tranconductances (Gm1 ,Gm2), intercept points(VIP2, VIP3, IIP3), IMD3 and 1 dB– compression point(P1 dB) are considered. The linearity of our proposed device improves by 35.5% in the view of the compression point in comparison to JLSG MOSFET before threshold voltage region of operation. The simulation results reveal a substantial enhancement in the linearity performance of the JLSGGC MOSFET. Improved linearity behaviour of JLSGGC MOSFET make it suitable for wireless RF and system on chip applications.

In this Paper, we have studied and compared the performance of two different configurations of simulation model advanced MOSFET devices which can be used for biosensor application. The bio-molecules like protein, biotin, streptavidin, APTES, etc., undergo label free electrical detection with the help of dielectrical modulation technique in order to overcome the limitations of short channel effect in a more efficient way. The bio-molecules trapped inside the cavity region change the electrical parameters of the MOSFET. Biosensors based on MOSFETs have certain issues, like short channel effects (SCEs) and problems related to scaling and power supply. Therefore the proposed device is better withstand to SCEs and can be consider as an alternative for biosensing applications. For channel material, silicon is used for both the configurations i.e. with stack and without stack model and we have also studied the performance of the device based on the analog as well as RF parameters by considering the protein as bio-molecule in the cavity. Two different oxide materials are used to design the device structure such as HfO2 (K = 25) and SiO2 (K = 3.9) and for simulation purpose the 2D Sentrausu TCAD simulator has been used. The sensing capability of this proposed dielectric modulated device can be applicable for IOT based applications. They can also be uses in health IOT systems for medical research applications and as bio chip sensor in wearable device so as to study the protein content of the human body.

Short channel effects (SCEs) along with mobility degradation has a great impact on CMOS technology below 100 nm. These effects can be overcome by using gate and channel engineering techniques which will improve mobility of the charge carriers, thus eventually improving drain current and trans-conductance of the device. In this work, the speed of operation for DG MOSFET is improved by reducing the channel length where dual-material gate-stack is deployed to avoid the drain-induced barrier lowering (DIBL) and hot carrier effects. In the presented device, the metal closer to the source and drain has higher and lower work function, respectively which causes a significant decrement in the peak electric field at the drain side and so the SCEs. The carrier mobility is also increased due to enhanced electric field in the channel, near the source, caused by higher work function gate material which, in turn, increases the MOSFET’s driving current. The screening effect reducing SCEs and an increment in the acceleration of the charge carriers in the channel are mainly attributed due to higher and lower threshold voltage found near the source and drain, respectively.

As short-channel effects (SCEs) are a major issue in the nanoscale regime, investigation of the subthreshold behaviour of nanometer-scale devices is critical. Here, we have developed an analytical model for a cylindrical gate junctionless accumulation-mode MOSFET (Cyl-JLAM MOSFET) to analyse its behaviour in the subthreshold region. The two-dimensional Poisson equation is solved to develop the analytical model by approximating the potential profile along the channel to be parabolic. We have formulated the expression for potential at the centre and electric field along the channel from the developed model. The key performance factors of SCEs including threshold voltage (VTH) roll-off, drain-induced barrier lowering and subthreshold slope are explored with respect to the geometry of the device parameters, i.e. body thickness of the cylindrical silicon pillar, length of the channel and thickness of the oxide layer. The results of our model are in good agreement with numerical simulations. The TCAD ATLAS 3D device simulator accounts for all the physical models required during the simulation. In this paper, the simple and distinctly formulated analytical model supports the application of the Cyl-JLAM MOSFET in integrated circuit design and optimization.

This paper explores the potential advantage of surrounded gate junctionless graded channel (SJLGC) MOSFET in the view of its Analog, RF performances using ATLAS TCAD device simulator. The impact of graded channel in the lateral direction on the potential, electric field, and velocity of carriers, energy band along the channel is investigated systematically. The present work mainly emphasises on the superior performance of SJLGC MOSFET by showing higher drain current (ID) , transconductance (gm) ,cut off frequency (fT) , maximum frequency of oscillation (fmax) , critical frequency (fK) .The drain current is improved by 10.03 % in SJLGC MOSFET due to the impact of grading the channel. There is an improvement in fT, fmax, fK by 45%, 29% and 18% respectively in SJLGC MOSFET showing better RF Performance. The dominance of the SJLGC MOSFET over SJL MOSFET is further elucidated by showing 74% improvement in intrinsic voltage gain (gm / gds) indicating its better applications in sub threshold region. But the transconductance generation factor of SJLGC MOSFET is less than SJL MOSFET in the subthreshold region. The intrinsic gate delay (ζD) of SJLGC MOSFET is less in comparison to SJL MOSFET due to the impact of lower gate to gate capacitance (CGG) suggesting better digital switching applications. The simulation results reveal that SJLGC MOSFET can be a competitive contender for the coming generation of RF circuits covering a broad range of operating frequencies in RF spectrum.

In this work, we have made a relative assessment of lattice-matched In 0.17 Al 0.83 N/AlN/GaN normally off HEMT device with AlGaN back-barrier (BB) and without back-barrier by using device simulator. The utility of AlGaN BB on the said E-HEMT relaxes the channel, which reduces the short channel effects. It also reduces the total gate capacitance and simultaneously improves the cut- off frequency. The numerical modelings are done by the 2Dimenssional TCAD by means of HD mobility and matched with the previously accepted experimental result. Different device parameters are analyzed and compared with BB and without BB with the help of the numerical modeling. AlGaN back-barrier has further benefits in device parameters with comparison to without back-barrier i.e. less total gate capacitance and higher cut-off frequency. These outcomes prove the utility of proposed BB in such E-Mode GaN HEMTs can be a substitute way out in support of high power along with high-frequency purposes.

In this paper, the performance of FinFET has been examined by changing the fin width which affects the device performance. The fin width has been changed by keeping the device width fixed and varying the width of the oxide layer by electrical characterization and simulation. The device width is fixed at 50nm and the oxide layer width is varied from 10nm to 3nm. Here five different parameters such as drain current (ID), transconductance (g m ), cutoff frequency (f T ), gain bandwidth product (GBW), and power (P) are computed to study the effect of oxide layer width of the device. It has been observed from the simulation that at lower oxide layer width ID and g m show maximum value, and at medium value of oxide layer width f T and GBW give better performance. The power consumption of FinFET is lesser when the oxide layer width reduces.

This paper presents the comparative study on linearity and analog/radio frequency presentation of an III–V staggered hetero-junction nanowire (NW) TFET with Si and InAs based NW TFET of same dimension. The device parameter of analog/RF performance for low power application such as transconductance (gm), output resistance (RO), intrinsic gain (gmR0), cut-off frequency (fT), maximum frequency of oscillation (fmax), gain bandwidth product (GBW), VIP2, VIP3 as well as 1-dB compression point has been explored. There is a better improvement in analog/radio frequency presentation obtained from heterojunction NW TFET over Si and InAs TFET. The result reveals that heterojunction TFET provides superior intrinsic gain, higher cutoff frequency, higher GBW better linearity performance as compared to Si and InAs TFET.

The analog/radio frequency (RF) and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor (JL DGMOS) is investigated using the numerical TCAD device simulator. JL DGMOSs have shown great promise for high-performance digital applications due to their superior short channel effect performance and ease of fabrication. In analog and RF circuit applications, linearity testing and RF performance is a major issue that is encountered due to non-linear behavior of the devices. Therefore, in this paper, different RF/analog and linearity performance figures of merits such as transconductance, intrinsic gain, the transconductance generation factor, the cut off frequency, the maximum frequency of oscillation, the gain bandwidth product, the variable intercept point of second order, the variable intercept point of third order, inter modulation distortion, the third-order intercept point, and 1-dB compression have been presented. Moreover, the effect of gate-length downscaling on these performance parameters has been carried out. The results indicate that the down scaled JL DGMOS shows great promise to become a competitive contender for analog/mixed signal system on chip applications by demonstrating a significant improvement in its RF performance with gate-length downscaling.

In the work purposed, the behavior of JLTMCSG MOSFET has been investigated by incorporating Dual Metals and Single Metal Gate with respect to different device parameters. The conclusion derived from the investigation reveals that DIBL can be suppressed and transportation capability of carrier can be improved by combining the advantages of junction-less architecture, gate terminal with three different material, and Cylindrical Surrounding Gate. We explore the radio frequency (RF) performance for JLTMCSG MOSFET taking in to account various figure of merits (FOMs) such as cutoff frequency fT, C-V curve, current gain, unilateral power gain and the simulated results are compared with JLDMCSG MOSFET.

In this work, we have analyzed the novelty of the Gate Stack Double Gate (DG) MOSFET with respect to different spacer variations in order to reduce the short channel effect challenges and simultaneously increasing the device performance. Silicon is used as the channel material along with the gate stacked technology for studying the analog performance and Radio Frequency (RF) performance of the device. For gate stacking, two types of oxides are used- one denoting low-K i.e SiO 2 and the other as high-K i.e- HfO 2 . Spacers with various permittivities were used to understand their effects on the performance of the device. The simulation result shows that the use of spacer material affected both the analog and RF behavior of the device significantly. The computer aided design (TCAD) simulations have been carried by SILVACO International.

This paper presents the performance of SRG Tunnel FET biosensor. Here the different device parameters are deliberate to meet the requirement of the technological development. Focus is made on how TFET can be a substitute ahead of CMOS characteristics for biosensor mean and to more enhance the low power design policy to facilitate it for IOT purpose. There is a experimentally demonstration has been done for nanogap cavity A nanogap cavity region. Investigation of the staggered gap hetero junction SRG TFET was done. The results are obtained using Silvaco software.

The modern electronics gadget has influenced tremendously every aspects of life. The demand to add more and more functionality has forced to increase the performance of the processor. To ensure a robust data supply to the processor a high performance, stable and low power SRAM is also of utmost necessity. An indirect read SRAM cell is proposed here which eliminates the read noise insertion to increase the data stability. It also consumes 41% less energy compared to the conventional SRAM cell. The SRAM cell is designed to be written single ended using only one write access transistor. The cell reduces the energy consumption by reducing the short circuit current and also reducing the number of leakage path. The cell also has a high write speed since the storage data node is a floating node and not connected to the ground.

Power theft is normally done by two methods that is bypassing or hooking. So to detect it, a system (current measuring and comparing) is proposed in which the household distribution of current is done indirectly from the electric pole to an intermediate distributor box and then to the individual houses. The current is measured periodically in the distributor box and is posted to the server database for each house using GSM/GPRS module. Similarly, for each house electric meter is designed which can measure the value of the current and post the same to the server database periodically using GSM/GPRS module. At the time of the installation of the electric meter the details of the users are stored in the database through a user friendly mobile application including the address, latitude, longitude using mobile GPS and the photograph of the user's house/area. Upon successful comparison between the current values from distributor box and electric meter in the server if we get a marginal difference between the currents then the theft is detected. Finally, the details of the user are shared with the authorized mobile application including the address and photograph of the area. The latitude and longitude are also used to show the area of theft in Google maps. And hence the required steps are taken. The same process is used for hooking but on the individual electric poles.

This paper presents the performance of non-uniformed doped double gate (DG) MOSFET with different spacer variations with an aim to analysis the effects of short channel and various performance metrics. In this work we have taken silicon as the channel material with non-uniform doping for studying the analog and RF performances. Spacer's materials having different permittivities were used to understand their effect on the device performance. Based on the simulations, we can conclude that analog and Radio Frequency performance of the device shows an significant improvement with addition of spacer layer. We have used computer aided design (TCAD) simulations by SILVACO International.

With time the design of RF and Analog application based circuits in MOSFET industry is changing and day by day it's becoming more and more difficult as device modeling has now entered the deep-subnanometer regime. Performance of junction less transistor is remarkable in digital application due to their ease of fabrication and superior SCEs. This paper highlights the DC, ANALOG, RF and LINEARITY performance of a Junction less Double Gate MOSFET (JL DG MOSFET) by downscaling the Channel length with the help of numerical TCAD device simulator (SILVACO). The figure of merits for DC, ANALOG, RF & LINEARITY parameters for example Transconductance $(\mathrm{g}_{\mathrm{m}})$ , Gain transconductance frequency product (GTFP), output resistance $(\mathrm{R}_{\mathrm{o}\mathrm{u}\mathrm{t}})$ , cut-off frequency $(\mathrm{f}_{\mathrm{T}})$ , Gain bandwidth product (GBW), Transconductance generation factor $(\mathrm{g}_{\mathrm{m}}/\mathrm{I}_{\mathrm{d}})$ , maximum frequency $(\mathrm{f}_{\max})$ , Intermodulation distortion (IMD), variable intercept point (VIP) are studied and impact of downscaling in gate length have been recorded. The results conclude that down scaled junction less DG MOSFET show a great pledge to turn out to be a feasible competitor for use in SOC application.

Here in this paper the design of a low power low noise amplifier (LNA) is presented which works for very wideband of frequency known as UWB signals. This method uses current reused technique which helps in reducing the power consumption while maintaining the same conversion gain and NF. No inductor is used in this circuit which reduces the complexity. Here a power gain of 12.6 dB, a NF of 2.1 dB at 3.5 GHz and 8.5 GHz is achieved, while consuming very less power nearly 7.6mW. It is clear from the observations that this technique solves the major problem of power consumption that was present in the previously existing techniques.

In this paper, we present a simulation study to report the effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire (NW) Tunnel FET (TFET). The different RF/analog and linearity figure of merits such as gm, RO, gm*RO, fT, fmax, GBW and 1-dB compression point of a NW TFET are extracted and the influence of gate-length downscaling on these parameters is analyzed. The RF/analog performance parameters obtained from InAs TFET is compared with an InAs MOSFET of identical dimension. Results reveal that superior RF and Linearity performance was obtained with gate-length downscaling for both devices under consideration. However, advantages of achieving improved RF performance with gate-length downscaling diminishes in terms of poor analog performance with gate-length downscaling for both the devices. This clearly indicates a trade-off between the analog and RF performance of a down-scaled InAs-based NW TFET and MOSFET. The results reveal that InAs TFET provides better fT, fmax and linearity performance in the saturation region than its MOSFET counterpart. It provides a reasonable RO, gm*RO at lower values of gate-overdrive voltage as compared to the InAs MOSFET. Therefore, this paper concludes that InAs NW TFETs have enormous potential to be a promising contender to the conventional bulk MOSFETs for realization of future generation low-power analog/RF applications.

In this work, we have studied the effect of variation in length of GaN gate with p-type doping concentration on the DC performances of AlGaN/GaN normally-off HEMT using 2D Atlas TCAD simulator. A comprehensive simulation is undertaken on the proposed device to examine different performance parameters such as drain current, transconductance factor, energy band diagram, and surface potential with respect to change in p-type GaN gate lengths. The gate lengths are varied from 60 to 90 nm, and it is noticed from the simulation results that with a decrease in gate length the drain current increases and transconductance increases. A proper optimization of gate length is indispensable to preserve the normally-off mode operation and at the same time enhancing certain performance parameters.

In this paper, current starved voltage controlled oscillators (CSVCO) using CMOS 180 nm technology are designed and their performances are evaluated. Then, a comparative study of different topologies of CSVCO like five-stage and seven-stage CSVCO is performed on the basis of power consumption, phase noise, center frequency, and tuning range. The simulation results reveal the better performance of the proposed design as compared to existing current starved VCO in terms of phase noise and power consumption.

In this work, a thorough inspection of DC, Analog, RF, Linearity and SCE's parameter analysis of Gate-Engineered TM-DG heterostructure MOSFET is carried out taking in to account the effect of changing the thickness of the barrier layer. The performance of the proposed device is investigated by evaluating some standard figure of merits (FOMs) like transconductance (g m ), Output resistance (R OUT ), Intrinsic Gain (g m R out ), Transconductance Generation factor (g m /I D ), gate capacitance, cutoff frequency(f T ), maximum frequency of oscillation (f max ), Gain Bandwidth Product (GBW), VIP2, VIP 3 and 1 dB compression. All these FOMs are analyzed by varying the thickness of the barrier from 1 nm to 4 nm using TCAD simulation. The simulation results clarifies that performance of TM-DG heterostructure Metal field effect transistor (1:2:3) is affected as thickness of the barrier is scaled down.

This work demonstrates a comparative analysis of various types of Double-Gate MOSFET, aims at enhancing the analog, linearity performances and these devices are more protective to short-channel effects (SECs). We have studied the linearity performance of DG-MOSFET by considering channel material as InAs and simultaneously incorporating gate stack technique. Variations oxide materials by considering channel as InAs and finally their comparison were thoroughly studied to have a better understanding of different linearity parameters. Various Figure-of-merits(FOMs) such as trans-conductance factor, VIP2, VIP3, IIP3 are thoroughly analysed for various high-K oxide materials along with gate stack technology. From the simulation results it is found that the performances of the device changes with respect to change in different oxide materials and it is also inferred that gate stack technology has also significant effect in the linearity performances. In this work, we have used the (TCAD) simulations by 2D ATLAS, Silvaco International to carry out the simulations.

A Si based SRG Tunnel FET is investigated to review its RF/Performance and Linearity. ATLAS, the 2D device simulator is used to examine the impact on the device parameters such as transconductance(g m ) transconductancegeneration factor(TGF), intrinsic gain (g m /g ds ) output resistance (R 0 ) unity gain cut-off frequency (f T ) and Maximum Frequency of Oscillations (f max ) with respect to the continual downscaling of channel length for analog and RF performance.. Results shows that superior RF performance and poor analog performance were achieved as per th scaling down of gate length. Linearity FOM such as 1-dB compression point, VIP2, VIP3, IMD3 are explored to enquire the linearity performance of the proposed device. Hence, this work will be benificial for new generation of RF circuits needed for wireless communication systems and for system on chip applications.

In this paper, we propose a new two-dimensional (2-D) analytical model of dual material junctionless surrounding gate MOSFET (DMJLSRG MOSFET). The expressions of potential and Electric Field of the gate engineered MOSFET structure have been obtained by solving the 2-D Poisson’s equation in subthreshold regime using a parabolic potential approximation considering effective conduction path effect (ECPE). The developed potential model accurately predicts the perceivable step function in the potential profile, responsible for effective screening of the drain potential variation in order to reduce DIBL and threshold voltage roll-off. In this work, effectiveness of dual material gate engineered (DM) design for junctionless MOSFET was scrutinized by comparing the results with a single material gate junctionless surrounding gate MOSFET (SMJLSRG MOSFET) of same dimension. From the developed potential model, a simple and accurate analytical expression of threshold voltage is also derived. Results reveal that DMJLSRG devices offer superior performance as compared to SMJLSRG devices. An improvement of hot-carrier effects (HCEs) and a reduction of short-channel effects (SCEs) have been demonstrated for gate-engineered DMJLDG device over the corresponding conventional (SMJLDG) device. The proposed model can be used as a basic design guideline for gate-engineered junctionless surrounding gate MOSFETs.

In this paper, the analog/radio frequency and linearity performance of staggered heterojunction nanowire tunnel FET is studied and compared with Si and InAs based NW TFET of same dimension. Different analog/RadioFrequency and linearity parameters like transconductance (gm), intrinsic gain (gmR0), cut-off frequency (fT), as well as 1-dB compression point has been studied. There is a better enhancement in the analog/RF performance obtained from heterojunction NW TFET over Si and InAs TFET. To improve ION and subthreshold swing, a considerable advance in the analog/RadioFrequency performance parameters obtain by the HETJ Nanowire TFET in comparision to Si and InAs Nanowire tunnel FET for use in analog/mixed signal low power applications is reported. The result reveals that heterojunction TFET provides superior intrinsic gain, higher cutoff frequency, better linearity performance as compared to Si and InAs TFET.

The Analog/Radio Frequency and Linearity analysis of a III-V Heterostructure Underlap Double Gate MOSFET is done using the numerical TCAD device simulator. Heterostructure Underlap DGMOS has evolved as a strong contender for various digital application. In analog and RF circuit application, linearity testing and RF performance confronts as a major problem which develops due to non linearity of the devices. In this paper, different figure of merits like Transconductance(gm), Transconductance Generation Factor (gm/ID), Cut off frequency(fT), Variable Intercept Point of Second order(VIP2)are analyzed. The comparative study with Junctionless Double Gate MOSFET has been carried out. The results reveal that Heterostucture DGMOS shows great promise to become a competitive contender for Analog/Mixed signal System-On-Chip (SOC) application by demonstrating a significant improvement in its RF performance.

The aim of this study was to investigate the physicochemical properties of glimepiride in SDs with PEG 20000. The phase solubility behavior of glimepiride in presence of various concentrations of PEG 20000 in pH 7.4 buffer was obtained at 37oC. The solubility of glimepiride increased with increasing amount of PEG 20000 in pH 7.4 buffer. Gibbs free energy (ΔGotr) values were all negative, indicating the spontaneous nature of glimepiride solubilization and ΔGotr decreased with increase in the PEG 20000 concentration, demonstrating that the reaction conditions became more favorable as the concentration of PEG 20000 increased. The SDs of glimepiride with PEG 20000 were prepared at 1:1, 1:3 and 1:5 (glimepiride: PEG 20000) ratio by melting method. Evaluation of the properties of the SDs was performed by using dissolution, Fourier-transform infrared (FTIR) spectroscopy and X-ray diffraction (XRD) studies. The SDs of glimepiride with PEG 20000 exhibited enhanced dissolution rate of glimepiride, and the rate increased with increasing concentration of PEG 20000 in SDs. Mean dissolution time (MDT) of glimepiride decreased significantly after preparation of SDs and physical mixture with PEG 20000. The FTIR spectroscopic studies showed the stability of glimepiride and absence of well-defined glimepiride-PEG 20000 interaction. The XRD studies indicated the amorphous state of glimepiride in SDs of glimepiride with PEG 20000.

Summary In this paper, the analog/radio frequency (RF) and linearity performance of an InAs-based nanowire (NW) tunnel field-effect transistor (TFET) is studied and compared with InAs-based NW MSFET of identical dimension. InAs-based NW TFETs shows a great promise for high performance digital application because of its superior subthreshold behavior. Different analog/RF and linearity key figure-of-merits like cut-off frequency (ft) and 1-dB compression point are extracted and the effect of gate length down scaling on those parameters has been studied. The results reveal that down scaled InAs-based NW TFET shows a significant improvement in its RF and linearity performance. However, this advantage diminishes in terms of poor analog performance with gate-length downscaling. This clearly indicates the necessity of a trade-off between analog and RF performance. Moreover, an in-depth comparison between InAs-based NW TFET and conventional MOSFET has also been provided in order to demonstrate the superiority of InAs-based NW TFET to become a competitive contender by replacing conventional MOSFET for Analog/Mixed signal System-on-Chip (SOC) applications. Copyright © 2016 John Wiley & Sons, Ltd.