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Due to the advances in the integrated circuit (IC) technology, more and more components are being fabricated into a tiny IC chip. Since the number of pins on each chip is limited by the physical size of the chip, the problem of testing becomes more difficult than ever, especially in the VLSI(Very Large Scale Integration) chips. This problem is aggravated by the fact that, in nearly all cases, integrated circuit manufacturers are not willing to release the detailed circuit diagram of the IC chip to the users. Yet, as users of the IC chips, to make sure that the implemented system is reliable, we need to test the IC chips and the systems made of the interconnection of these chips. The purpose of this project is to find efficient algorithms for testing LSI/VLSI chips and LSI/VSLI-based systems. As a result of the rapidly increasing complexity of modern digital LSI/VLSI systems, functional testing is attracting more attention than ever not only in the computer manufacturing industry but also in the diversified potential applications. Functional testing uses a representation of a digital system higher than the gate-level testing. In functional testing, functional faults with respect to the functional specification (e.g., addition operation in a processor) are tested instead of a signal faults (e.g., a line stuck-at logical 0) in the circuit representation. The purpose of functional testing is to validate correct functional operations of digital systems according to their specifications.

This paper presents three algorithms to test the instruction decoding function of microprocessors. The algorithms are based on the knowledge of some timing and control information available to users through microprocessor manuals and data sheets. The tests are functional in nature. The authors establish the order of complexity of the algorithms presented in this paper. As an example, the test complexity for a microprocessor is computed and the results are compared with a known algorithm.

Functional testing is a feasible solution for LSI/VLSI test generation and design verification. In this paper, we present a systematic way to perform functional testing using an advanced symbolic execution technique. Symbolic execution is a very useful and powerful software engineering technique mainly used in program analysis including test generation. Often a single symbolic execution of a program may represent a large number of normal test runs.

This paper presents a number of algorithms to test the instruction decoding function of microprocessors based on some timing and control information available to users. Keywords: Register Transfer Language; Digital Networks.

We started the project by initiating a study of available literature that is related to the scope of work for this project. Testing of high complexity LSI and VLSI components has become very important, and has been receiving considerable interest. The project involves a test-effectiveness measure. Because of the complexity of the problem, it has not yet been satisfactorily approached by others. Some work on information theoretic approach has been reported, but the approach does not appear to be suitable for testing digital system with high fault coverage. We feel that test-effectiveness measure should be related with physically possible failures, and thus the measure should be available to use detailed information of the circuitry if it is available.