305 results on '"Sturtevant, John"'
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2. Design for Manufacturing and Design Process Technology Co-Optimization
3. Impact of mask rule constraints on ideal sraf placement
4. EUV full-chip curvilinear mask options for logic via and metal patterning
5. Compact modeling of stochastics and application in OPC
6. Importance sampling in Gaussian random field EUV stochastic model for quantification of stochastic variability of EUV vias
7. Rapid full-chip curvilinear OPC for advanced logic and memory
8. Impact of mask rule constraints on ideal SRAF placement
9. Compact modeling of stochastics and application in OPC
10. EUV full-chip curvilinear mask options for logic via and metal patterning
11. Probability prediction of EUV process failure due to resist-exposure stochastic: applications of Gaussian random fields excursions and Rice's formula
12. Real-time full-wafer design-based inter-layer virtual metrology
13. Stochastic model prediction of pattern-failure
14. Implant layers: leading-edge noncritical lithography. (Feature)
15. Process window-based feature and die failure rate prediction
16. Enabling enhanced EUV lithographic performance using advanced SMO, OPC, and RET
17. Rapid full-chip curvilinear OPC for advanced logic and memory
18. Impact of aberrations in EUV lithography: metal to via edge placement control
19. Process window-based feature and die failure rate prediction.
20. Edge placement errors in EUV from aberration variation
21. Aerial image metrology for OPC modeling and mask qualification
22. Interlayer verification methodology for multi-patterning processes
23. Effective use of aerial image metrology for calibration of OPC models
24. Probability prediction of EUV process failure due to resist-exposure stochastic: applications of Gaussian random fields excursions and Rice's formula
25. Stochastic model prediction of pattern-failure
26. Impact of Aberrations in EUV Lithography: Metal to Via Edge Placement Control.
27. Bayesian analysis for OPC modeling with film stack properties and posterior predictive checking
28. Two-layer critical dimensions and overlay process window characterization and improvement in full-chip computational lithography
29. Multi-layer VEB modeling: capturing interlayer etch process effects for multi-patterning process
30. Modeling metrology for calibration of OPC models
31. Bayesian inference for OPC modeling
32. Source mask optimization using 3D mask and compact resist models
33. Aerial Image Metrology for OPC Modeling and Mask Qualification.
34. EUV full-chip curvilinear mask options for logic via and metal patterning.
35. Impact of mask rule constraints on ideal SRAF placement.
36. Importance sampling in Gaussian random field EUV stochastic model for quantification of stochastic variability of EUV vias.
37. Compact modeling of stochastics and application in OPC.
38. Process window-based feature and die failure rate prediction
39. The Scatter Chart as a Practical Tool. A Simple Means of Presenting Joint Two-Way Influence
40. Characterization and mitigation of relative edge placement errors (rEPE) in full-chip computational lithography
41. Practical DTCO through design/patterning exploration
42. Akaike information criterion to select well-fit resist models
43. Full chip two-layer CD and overlay process window analysis
44. Finding practical phenomenological models that include both photoresist behavior and etch process effects
45. 14-nm photomask simulation sensitivity
46. Rapid, accurate improvement in 3D mask representation via input geometry optimization and crosstalk
47. Impact of aberrations in EUV lithography: metal to via edge placement control
48. Impact of 14-nm photomask uncertainties on computational lithography solutions
49. Akaike information criterion to select well-fit resist models
50. Full chip two-layer CD and overlay process window analysis
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