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High current-carrying capacity and low resistivity are key parameters for power devices. In this paper a copper based terminal metallurgy scheme for wire- and wedge-bonding is described, which improves these properties. The method of choice for depositing thick copper wires is pattern plating. However the plating process has to be optimized in order to get a homogeneous thickness distribution. An electroless coating of NiP, Pd and Au on top of the Cu layers is used as bond interface. This process provides high reliable gold-wire and aluminum-wedge bonds. Index Terms--Copper, electroless plating, electroplating, texture.

A theory is developed that leads to the determination of the Hall voltage as a function of the position along the longitudinal direction of the device channel. The theory of this work correctly predicts in particular for devices with an aspect ratio W/L-0.3 or larger, the departure occurs on the whole channel length L, so that the use of standard theory of the Hall effect would lead to a gross underestimation of the Hall mobility.

An experimental investigation on high-temperature electron impact-ionization in silicon is carried out with the aim of improving the qualitative and quantitative understanding of carrier transport under electrostatic discharge conditions. A novel extraction methodology allowing for the determination of the impact-ionization coefficient against electric field and lattice temperature is used.

System integration and high power density of monolithic and multichip designs are the driving force for the progress in power electronic systems. The whole system has to be considered and optimized to meet this target and to keep the overall ruggedness, sensitivity toward electromagnetic interference and long term reliability, Silicon utilization system reliability and power units miniaturization are the key factors. In this paper new technologies, advanced devices concepts and future system aspect for system-integration in the automotive and industrial segments are discussed. In both fields of applications these are huge requirements toward system dynamic characteristic, overload capability, ruggedness behavior and reliability. In the automotive segment technologies working at high operating temperatures are required and in the industrial are high blocking voltage capabilities are needed. Index Terms--Coreless transformer, high voltage-integrated cir;cuits (ICs), silicon-on-insulator (SOI), smart power.

Integrated vertical DMOS transistors of a 90-V smart power technology have been studied under short-duration current pulses. The movements of current filaments and multiple hot spots have been observed by transient interferometric mapping under nondestructive snap-back conditions were reported.

The back heterodyne interferometry is a quantitative technique for nanosecond time and micrometer space resolution thermal and free-carrier concentration mapping in semiconductor devices subjected to high energy pulses. The interferometeric method is not only limited to the transient thermal mapping of ESD PDs, but can also be used in failure analysis.

We investigate the effect of elevated ambient temperature on thermal breakdown (TB) modes in linear-geometry electrostatic discharge (ESD) protection n-p-n transistors of smart power technology subjected to 0.5–1- \mu\s-long ESD pulses. The current transport in these devices has a form of traveling current filaments (CFs) where TB at room temperature occurs at one of the device ends. An increase in ambient temperature gives rise additionally to another failure mode, inside the device. For the failure mode at the device end, the increase of ambient temperature in the range up to 100 ^\circ\C causes shortening of the averaged time to TB \langle tTB\rangle by a duration that the CF needs for one round trip over the device width. At ambient temperatures up to 180 ^\circ \C, the TB may occur even at initial triggering CF position inside the device, before the CF starts to move. The ambient temperature at which the transition between CF modes with different \langle tTB\rangle occurs is investigated as a function of stress current. Furthermore, inspecting the failure current of devices with different widths shows that there is an equivalence between the effect of increased ambient temperature and the effect of the preheating at the device end by a previous CF passage. The experiments are supported by 3-D thermal simulation of temperature in moving and standing CFs. [ABSTRACT FROM PUBLISHER]

Intrinsic device temperature is one of the most important limits of the safe operating area and of the reliability of power double-diffused metal-oxide-semiconductor (DMOS) transistors. Therefore, precise knowledge of the temperatures throughout the device, up to the onset of thermal runaway is required. However, standard methods that measure the surface temperature, such as infrared thermography, usually cannot be applied to most advanced power technologies. Therefore, we propose to embed very small temperature sensors within the active DMOS cell array itself. These sensors are located very close to the heat-generating regions, having a tight thermal coupling, thus giving an accurate measurement of the intrinsic device temperature. Moreover, due to their small size, many sensors can be integrated into a power DMOS for a good spatial resolution. The sensors have been implemented in a smart power production technology. Calibration and verification up to 600^\circC, as well as further validation up to 400^\circC, by comparison to transient interferometric mapping measurements are discussed. The usefulness of the sensors is demonstrated by characterization of the thermal runaway, by measurements with a high spatial resolution achieved by 60 sensors in conjunction with an on-chip multiplexer, and by an assessment of the peak temperature reduction that can be obtained by using thick power metal layers for increased heat capacitance. [ABSTRACT FROM PUBLISHER]