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We present an area efficient test structure that allows measurement of the statistical distribution of SRAM cell read currents and write trip voltages for 1 million SRAM core cells. The data taken from measurements of wafers fabricated with a 90-nm and 65-nm CMOS process flow show that the device variations are Gaussian distributed for more than 1 million devices, covering more than 5 sigma of variation. The analysis of the measured SRAM performances validate Monte Carlo simulations. Index Terms--65 and 90 nm, low voltage, measurement structure, read current, SRAM, variation, write trip voltage.

This paper describes the design and VLSI implementation of a highly efficient, single-port SRAM-based deblocking filter. It can achieve 204 cycles/macroblock throughput for H.264/AVC real-time decoding. Several deblocking filter designs in the literature have been compared and the possibility of realizing them in a pipeline is studied. Eventually we came up with a completely new design which has a five-stage pipeline with gated clock to increase system throughput while reducing power. Data hazards and structure hazards, which are the two most critical issues for a pipelined filter, are analyzed and resolved. Efficient memory organization for both on-chip SRAM and transposition buffers is employed. By using innovative hybrid edge filtering sequence and out-of-order memory update scenario, we obtain zero stall cycle in normal pipeline flow, making the best out of a pipelined architecture. Compared with existing designs, our design achieves at least 18% clock cycle reduction, as well as 20% lower power consumption owing to its efficient pipeline and memory architecture. The total gate count is comparable to other designs in literature without using any expensive two-port or dual-port on-chip SRAMs. Index Terms--Deblocking filter, hazard, H.264/AVC, macroblock, pipeline, SRAM, throughput.

An efficient infrastructure is described for characterizing the various types of variation in transistor characteristics. The impact of the variability on static random access memory (SRAM), analog and digital circuit blocks used for designing system-on-chip is examined.

We report on experimental SEU studies using thermal and high-energy neutrons, conducted at the TRIUMF facility, Vancouver. Different SRAM samples were used and many samples showed to be highly susceptible to thermal neutrons. Moreover, a considerable part of the total SEU-rate, at high altitudes as well as down at sea level, may be attributed to thermal neutrons for RAM based devices. Index Terms--Semiconductor device radiation effects, semiconductor device reliability, semiconductor device testing, semiconductor memories.

We quantify the SEU rate induced by neutrons in current devices, from both low energy (thermal) and high energy neutrons. New measured SEU cross sections from both kinds of neutrons in SRAMs, DRAMs and microprocessors are included. Index Terms--Atmospheric neutron flux, avionics SEU, BPSG, neutron SEU, thermal neutrons.

Neutron test data on single event effects for a wide range of SRAMs, facilities (monoenergetic and continuum) and energies (thermal to 800 MeV) are compared. Many modern devices are found to be sensitive to thermal neutrons and rates from this source can dominate in many situations. A significant number of devices suffer latchup and the cross-sections increase with operating voltage and beam energy implying that most test facilities will understimate the problem for the natural atmospheric environment. Upset sensitivity at 3-5 MeV varies from 5 to 600 less than at high energies and will be of most significance for sources of fission neutrons. These results are related to current and developing standards. Index Terms--Neutrons, protons, single event effects, standards.

Accelerated alpha-Soft Error Rate (SER) measurements are carried out on regular and radiation-hardened SRAMs in a 65 nm CMOS technology. Results are first compared to previous experimental radiation data in 130 nm and 90 nm. Second, the SER increase measured in 65 nm is investigated through (i) Multiple Cell Upsets (MCU) counting and classification from experimental bitmap errors and (ii) full 3-D device simulations on SRAM bitcells to assess the PMOS-off sensitivity and the NMOS SEU threshold LET ([LET.sub.th]) of each tested technologies. Finally, process changes are also scanned to shed light on the 65 nm SRAM response to alpha particles. Index Terms--Alpha experiments, CMOS 65 nm, full 3-D device simulation, multiple cell upset, robust SRAM, soft error rate.

This paper presents a method to estimate the saturated proton upset cross section for 6 T SOI SRAM cells from layout and technology parameters. The calculated proton upset cross section based on this method is in good agreement with test results for our 6 T SOI SRAM cells processed using 0.15 and 0.35 [micro]m technologies. Index Terms--Heavy ion, proton, single event upset, upset cross section.

This paper discusses the practical limits of proton and heavy ion induced single event upset cross sections in SEU hardened deep submicron SOI SRAMs. Non-conventional 'double-hit' mechanisms are hypothesized to explain test results. Index Terms--SEU, SOI, SRAM, upset mechanism.

The probability of proton-induced multiple-bit upset (MBU) has increased in highly-scaled technologies because device dimensions are small relative to particle event track size. Both proton-induced single event upset (SEU) and MBU responses have been shown to vary with angle and energy for certain technologies. This work analyzes SEU and MBU in a 130 nm CMOS SRAM in which the single-event response shows a strong dependence on the angle of proton incidence. Current proton testing methods do not account for device orientation relative to the proton beam and, subsequently, error rate prediction assumes no angular dependencies. Proton-induced MBU is expected to increase as integrated circuits continue to scale into the deep sub-micron regime. Consequently, the application of current testing methods will lead to an incorrect prediction of error rates. Index Terms--Energy deposition cross section, multiple-bit upset (MBU), MRED, single event upset (SEU), SRAM, proton effects.

The radiation hardness of nominally identical SRAM test chips fabricated in five commercial foundries is examined. Large variations in single-event latchup and total dose response are observed. The softest SRAMs fail functionally at ~200 krad(Si[O.sub.2]) and have a fairly large single-event latchup cross section. This is in contrast to the hardest foundry split which is nearly immune to single-event latchup at room temperature, and remains functional to a total dose of 400 krad(Si[O.sub.2]). Three of the splits show a similar increase in radiation induced leakage current, which is dependent on both the characterization bias as well as the pattern written to the memory array. The other two splits show neither a pattern nor a bias dependence on the leakage current. Heavy-ion microbeam experiments confirm that the most latchup sensitive area of these SRAMs is the peripheral circuitry, not the memory array itself. Qualification and hardened-by-design integrated circuit implications are discussed. Index Terms--Commercial foundry, COTS, heavy-ion, leakage current, neutron, proton, radiation effects, radiation response, SEL, SEU, single event, SRAM, total-dose.

Neutron SEE data for memories shows that the distribution of MBU's is a geometrical progression. We demonstrate that this permits the proportion of MBU's to be calculated from the mean and variance of the errors per read-cycle. Index Terms--Multiple bit upset (MBU), neutrons, SDRAM, single event effect (SEE), SRAM, statistical technique.

The effect of proton angle of incidence on proton-induced single-event latchup (SEL) is investigated in detail at room and elevated temperatures in present-day SRAMs. SRAMs from seven different vendors were irradiated at proton energies from 50 to 200 MeV, at temperatures of 25 [degrees]C and 75 [degrees]C, and at angles of incidence from 0[degrees] (normal) to 85[degrees] (grazing). The effects of angle of incidence were also investigated for neutron-induced SEL. The angle of incidence can significantly impact SEL hardness. For one SRAM at a temperature of 75 [degrees]C, characterizing SEL cross section at grazing angle resulted in a 16 times increase in SEL cross section. Large increases in SEL cross section with angle were also observed for other SRAMs characterized at room temperature. These increases in SEL cross section with angle of incidence are much larger than those measured previously for older SRAM technologies. The mechanism for the effect of angle of incidence on SEL cross section is not due simply to the deposition of more energy in the sensitive volume caused by an increase in path length as the angle of incidence is increased. To investigate possible mechanisms nuclear scattering calculations were performed and combined with device simulations. Simulation results suggest that the mechanism is a consequence of the linear energy transfer (LET) and range distributions of secondary ions produced by proton-material (or neutron-material) interactions coupled with an increase in SEL sensitivity (decrease in LET threshold) as angle of incidence is increased. These results have significant impact on SEL hardness assurance testing, especially for system applications where latchups cannot be tolerated. To best ensure that SEL hardness requirement are met, SRAMs should be characterized at both grazing and normal angles of incidence, and at maximum temperature, voltage, and proton energy. Index Terms--Hardness assurance, proton radiation effects, single-event effects, single-event latchup.

ROM cell architectures are proposed that have roughly 20% greater storage density in the cell array compared to that of a conventional ROM. Increased density is achieved by exploiting the multiple interconnect layers now available in common logic processes and by using multiple ROM cell types in combination. The storage density of arrays of these hybrid ROM cells increases further as more interconnect layers become available. In addition, a new SRAM-ROM architecture is presented that capitalizes on these techniques to add ROM capability to a conventional SRAM cell with no additional transistors in the memory cell and little or, in some cases, no impact on the cell area. Index Terms--Memory architecture, multiple bitlines (BLs), read-only memory, ROM, SRAM, SRAM-ROM, stacked BLs.

This work presents a fault-tolerance method able to deal with the combination of open and shortcut faults in SRAM-based FPGA routing connections, which may affect one or more redundant domains of a given protected design. The method is based on duplication of the internal critical connections, creating a local redundancy in the routing whenever needed. Therefore, when the critical connection fails, the redundant routing enforces the propagation of the original value. Preliminary results, performed by fault injection, show the efficiency of this method to improve reliability in the routing. Index Terms--Fault injection, fault tolerance, field programmable gate arrays.

The charge sharing quantification in the case of neutron induced SEUs in a 130 nm bulk SRAM is presented. Conclusions on its contribution to the soft errors sensitivity evaluation using Monte-Carlo codes are underlined. Index Terms--Bulk, charge sharing, diffusion, neutron, SEU, SRAM, TCAD simulations.

The effect of proton energy on single-event latchup (SEL) in present-day SRAMs is investigated over a wide range of proton energies and temperature. SRAMs from five different vendors were irradiated at proton energies from 20 to 500 MeV and at temperatures of 25[degrees] and 85[degrees]C. For the SRAMs and radiation conditions examined in this work, proton energy SEL thresholds varied from as low as 20 MeV to as high as 490 MeV. To gain insight into the observed effects, the heavy-ion SEL linear energy transfer (LET) thresholds of the SRAMs were measured and compared to high-energy transport calculations of proton interactions with different materials. For some SRAMs that showed proton-induced SEE the heavy-ion SEL threshold LET was as high as 25 MeV-[cm.sup.2]/mg. Proton interactions with Si cannot generate nuclear recoils with LETs this large. Our nuclear scattering calculations suggest that the nuclear recoils are generated by proton interactions with tungsten. Tungsten plugs are commonly used in most high-density ICs fabricated today, including SRAMs. These results demonstrate that for system applications where latchups cannot be tolerated, SEL hardness assurance testing should be performed at a proton energy at least as high as the highest proton energy present in the system environment. Moreover, the best procedure to ensure that ICs will be latchup free in proton environments may be to use a heavy-ion source with LETs [greater than or equal to] 40 MeV-[cm.sup.2]/mg.

Partially depleted (PD) 0.15 [micro]m CMOS silicon-on-insulator (SOI) SRAMs were exposed to heavy ions, 14 MeV neutrons, and protons. The upset threshold and saturated cross section LET values were determined from heavy ion exposures. The SRAMs were then exposed at various angles of incidence with respect to a 14 MeV neutron source to a total fluence of 4 x [10.sup.13] n/[cm.sup.2]. The number of upsets from front exposure was more than double the number from back exposure. Following neutron exposure, proton upset measurements were performed. For a given fluence, the number of proton induced upsets was essentially identical to the number of neutron induced upsets. Index Terms--Random access memories, silicon-on-insulator technology, single event upset.

This paper provides a methodology for estimating the proton and heavy ion static saturation cross-sections for multi-bit upsets (MBUs) in Xilinx field-programmable gate arrays and describes a methodology for determining MBUs' effects on triple-modular redundancy protected circuits. Experimental results are provided. Index Terms--Heavy ions, field programmable gate arrays, proton radiation effects.

The single-event upset response of a single-event hardened SRAM 10-transistor cell is mapped in two dimensions via carrier injection by two-photon absorption through the back (substrate) surface in a flip-chip mounted 4 Mb SRAM. Using through-wafer carrier injection, charge is deposited into the active regions of the device at well-defined locations in a reproducible manner, and the single-event upset sensitive region of the device is localized to within [+ or -]0.3 micrometers. Index Terms--Laser SEE, nonlinear absorption, single-event effects, SEE, SEU, silicon, SRAM.

This paper investigates the sensitivity of SOI and Bulk SRAMs to neutron irradiations with energies from 14 to 500 MeV. The technology sensitivity is analyzed with both experiments and Monte Carlo simulations. In particular, simulations include the nuclear interactions of neutrons with both silicon and oxygen nuclei In-St and n-O), in order to investigate the influence of isolation upper layers on the device sensitivity. The device cross-sections are analyzed for mono-energetic neutron irradiations and discussed in terms of nuclear interaction type (n-St and n-O) and distribution of the secondary ion recoils. We also investigate the dimensions of the interaction volume around the sensitive cell as a function of the device architecture. Index Terms--Bulk technologies, SOI technologies, neutron effects, soft error rate (SER), single-event upset (SEU), Monte Carlo methods.

Angular dependence of proton-induced Multiple-Bit Upsets (MBUs) in a synchronous SRAM is reported. Experiments showed that the cross section of MBU depended on proton energy, incident direction, and physical arrangement of sensitive transistors in adjacent cells. Also analysis clarified that there was a special condition which MBU could be caused by a mechanism of Single-Event Upsets (SEUs), not by that of MBUs. Index Terms--Angular irradiation, GEANT4, Multiple-Bit Upset (MBU), proton, Single-Event Upset (SEU), SRAM.

In order to deploy successfully commercially-off-the-shelf SRAM-based FPGA devices in safety- or mission-critical applications, designers need to adopt suitable hardening techniques, as well as methods for validating the correctness of the obtained designs, as far as the system's dependability is concerned. In this paper we describe a new analytical approach to estimate the dependability of TMR designs implemented on SRAM-based FPGAs that, by exploiting a detailed knowledge of FPGAs architectures and configuration memory, is able to predict the effects of single event upsets with the same accuracy of fault injection but at a fraction of the fault-injection's execution time. Index Terms--Dependability evaluation, FPGA, single event effects.

Heavy ion irradiation was simulated using a Geant4 based Monte-Carlo transport code. Electronic and nuclear physics were used to generate statistical profiles of charge deposition in the sensitive volume of an SEU hardened SRAM. Simulation results show that materials external to the sensitive volume can affect the experimentally measured cross-section curve. Index Terms--Cross section, Geant4, MRED, single event upset.

A low-power embedded SRAM for a large range of applications has been implemented in a standard digital 0.18-1[micro]m process. The leakage current in the cells is reduced by using a source-body bias not exceeding the value that guaranties safe data retention, and less leaking nonminimum length transistors. Locally short-circuiting this bias, speed and noise margin loss in active mode is avoided, especially for low supply voltages. The bias is generated internally at the carefully designed equilibrium between cell, switch, and diode limiter leakages averaged over the array. The leakage of the full SRAM, including an optimized periphery, is reduced more than 20 times. Used in an industrial RF transceiver, the measurements confirm its performances. Index Terms--CMOS memory, limiting, low leakage, low power, source bias, SRAM, subthreshold current.

This paper presents experimental ASER on SOI and BULK SRAMs for the 250-, 130-, and 90-nm technologies. The key parameters controlling soft error rate (SER) in these technologies are modeled with Monte Carlo simulations to predict SER to the 65-nm node. Index Terms--Alpha particles, atmospheric neutrons, commercial technologies, Monte Carlo simulations, SER testing, soft error rate, SOI.

The static random acces memory (SRAM) array discussed in this brief is based on a four-transistor SRAM cell. A new method of writing the cell together with an associated array structure is proposed. The advantages are a significant reduction in power and an increase in cell reliability over previous designs. The noise margin of the cell under various conditions is investigated, as this is an effective method of designing the control mechanism of the cell. Index Terms--Reduced-area static random acces memory (SRAM), static noise margin.

A loadless complementary metal-oxide semiconductor (CMOS) four-transistor (4T) cell for very-high-density embedded static random-access memory (SRAM) applications is described.

The effect of a gate-all-around thin-film transistor (GAT) with a lightly doped drain structure on the reduction of the off-current is studied. The off-current of the GAT is found to be almost the same as that of a single-gate TFT with an LDD structure although the GAT's channel area is about twice as big as that of the SGT. The suppression mechanism of the individual performance variations in the GAT is also investigated by thinning the channel poly-Si.

This paper reports on the ellipsometric monitoring of SRAM gate patterns in KrF lithography. Results showed that ellipsometry is practical for monitoring repetitive patterns. A multivariable regression analysis was applied to predict gate lengths by using ellipsometric parameters. A good agreement (3[Sigma] = 8.7 nm) between the measured width by CD-SEM and the predicted ones was achieved. Standard deviation of the predicted width (repeatability) was 0.5 nm. This suggests that ellipsometry is superior to CD-SEM in arriving at the average values.

An asymmetric memory cell, a single-bit-line static random access memory cell, was designed using a complementary thin-film transistor (C-TFT). The structure of the C-TFT was constructed with n-channel and p-channel TFTs which share the same gate. The proposed cell size can be reduced to 88% as compared with the conventional one using 0.4 micrometer design rules. The cell was found to be capable of stable read and write operations with further decreases cell size.

The role of neutron-induced soft errors (SE) in logic applications is examined through an experimental and analytical study of neutron-induced SE in sub-half-micron complementary metal oxide semincoductors (CMOS) SRAM and Latch circuits. Findings show that the cosmic ray neutrons affect CMOS circuits at ground level and SE rates (SER) in Latch circuits were dominated by neutrons. Moreover, neutron-induced SER in CMOS SRAM were on the same order as alpha-induced SER.

The first simultaneous microbeam mapping of single event upset (SEU) and latchup (SEL) in the CMOS RAM HM65162 is presented. We found that the shapes of the sensitive areas depend on [V.sub.DD], on the ions being used and on the site on the chip being hit by the ion. In particular, we found SEL sensitive sites close to the main power supply lines between the memory-bit-arrays by detecting the accompanying current surge. All these SELs were also accompanied by bit-flips elsewhere in the memory (which we call 'indirect' SEUs in contrast to the well known SEUs induced in the hit memory cell only). When identical SEL sensitive sites were hit farther away from the supply lines only indirect SEL sensitive sites could be detected. We interpret these events as 'latent' latchups in contrast to the 'classical' ones detected by their induced current surge. These latent SELs were probably decoupled from the main supply lines by the high resistivity of the local supply lines.

This paper presents the results from in-flight measurements of single event upsets (SEU) in static random access memories (SRAM) caused by the atmospheric radiation environment at aircraft altitudes. The memory devices were carried on commercial airlines at high altitude and mainly high latitudes. The SEUs were monitored by a Component Upset Test Equipment (CUTE), designed for this experiment. The in flight results are compared to ground based testing with neutrons from three different sources.

This work determines experimentally and by simulation the SEU sensitive depth in a 0.6 [[micro]meter] SRAM technology. A good correlation is obtained between the two studies in the case of heavy ions deposing energy close to the critical energy. Other simulation results complete the first investigation by studying the minimum sensitive depth for ions deposing higher energies (at greater LET).

The radiation hardness (RadHrd) of semiconductor devices is important in space, military, nuclear power plant and high energy physics detector applications. The RadHrd test of static random-access-memory (SRAM) has been undertaken using the Co-60 gamma ray and does-to-failure parameter. The number of error-bytes vs dose, was found to provide a clear dose-to-failure. Test conditions of dose rate, temperature and power supply voltage have to be specified to ensure meaningful test results.

This work presents SEU phenomena in advanced SRAM memory cells. Using mixed-mode simulation, the effects of scaling on the notions of sensitive area and critical charge is shown. Specifically, we quantify the influence of parasitic bipolar action in cells fabricated in a submicron technology.

Individual ionizing heavy ion events are shown to cause two or more adjacent memory cells to change logic states in a high density CMOS SRAM. A majority of the upsets produced by normally incident heavy ions are due to single-particle events that causes a single cell to upset. However, for grazing angles a majority of the upsets produced by heavy-ion irradiation are due to single-particle events that cause two or more cells to change logic states. Experimental evidence of a single proton-induced spallation reaction that causes two adjacent memory cells to change logic states is presented. Results from a dual volume Monte-Carlo simulation code for proton-induced single-event multiple upsets are within a factor of three of experimental data for protons at normal incidence and 70 degrees.

Reactor neutron environments can be used to test/screen the sensitivity of unhardened commercial SRAMs to low-LET neutron-induced upset. Tests indicate both thermal/epithermal (< 1 keV) and fast neutrons can cause upsets in unhardened parts. Measured upset rates in reactor environments can be used to estimate the upset rates from thermal and fast portions of arbitrary neutron spectra.

Hard errors or 'stuck bits' observed in a single memory can occur over a broad range of macroscopically measured doses. It is shown here that a major contributing factor to this is the microscopic variation of deposited dose across the large array of gate oxides composing the memory. In addition, processing variations also contribute to the spreading of hard error doses. A statistical model of these factors is presented and compared to Co-60 data. Comparisons are then made between the hard error dose distribution for Co-60 and that expected in the heart of the proton belts. It is shown that even though the average hard error dose in the proton belts is greater, the onset hard error dose can be less. Thus, the relations between the onset dose for hard errors in the two environments should be thoroughly understood before qualifying parts for space applications.

The CMOS SRAM radiation and postirradiation functional upsets are investigated as a function of total dose, dose rate, annealing time and functional tests. Local and conventional X-ray as well as LINAC and Sr-90 irradiation procedures were performed. A model explaining the experimental results is discussed.

Total-dose tests have been performed on an advanced commercial 4-Mb static RAM (SRAM) that uses thin film p-channel transistors in a six-transistor (6-T) cell design in 0.35-[[micro]meter] technology. These results are compared with other results obtained on similar test structures and also with other results on commercial SRAMs using the more typical four-transistor, two-resistor (4-T) design.

The impact of technology trends on the SEU hardness of epitaxial CMOS SRAMs is investigated using three-dimensional simulation. We study trends in SEU susceptibility with parameter variations across and within technology generations. Upset mechanisms for various strike locations and their dependence on gate-length scaling are explored. Such studies are useful for technology development and providing input for process and design decisions. An application of SEU simulation to the development of a 0.5-[[micro]meter] radiation-hardened CMOS SRAM is presented.

Multiple Bit Upsets (MBU) have been studied in a 256k CMOS static RAM irradiated at normal incidence and grazing angle. In normal incidence the sensitive areas have been identified with pulsed laser irradiation. The laser power thresholds have been determined for single to quadruple upsets in adjacent cells. Both experimental data and 3D simulations emphasize the role of delayed charge collection, by diffusion, and charge sharing between sensitive areas. Upset tracks have been recorded at grazing angle and used to determine the charge collection depth. These data revealed the existence of an LET threshold for MBU at grazing angle. As the ion LET increases different types of tracks are observed and correlated to the topological pattern in adjacent memory cells. This phenomenon is due to an unexpected charge collection mechanism, which couples adjacent sensitive areas and results in charge transfer between memory cells. The comparison with previous data on the same device indicates a strong influence of both ion energy and angle of incidence on the cross section, emphasizing the intrinsic limitation of standard characterizations with low energy ions. These results indicate that the basic assumption of a rectangular parallelepipedic volume does not take into account coupling phenomena, such as occurs in MBUs, and is no longer valid at grazing angle.

Beam Blanking SEM (Beam Blanking Scanning Electron Microscope) was successfully used to measure and to map soft error sites on 64kbit memory cells. Cross-section versus beam current and LET curves derived from BBSEM and heavy ion tests, respectively, have been compared. A linear relation between BBSEM current and heavy ion LET has been suggested.

Results of an experiment providing initial validation of the use of charge-collection spectroscopy to measure the over-layer and epitaxial thickness and substrate diffusion length are given for several CMOS SRAM test devices.

A closed-form propagation delay expression developed for the complementary metal-oxide semiconductor static random access memory (SRAM) chip predicts delay time for high density, high speed SRAM's with computational ease and sufficient accuracy. The model is based on a delay approximation for a SRAM cell capacitively loaded with multilayer interconnections and hence, can be extended to branched transmission lines. The expression-predicted absolute maximum error is smaller than 4.8% in comparison with actual measurements.

Single event upset cross sections exhibit a clock frequency dependence, the origins of which have been investigated in a CMOS SRAM, both with a pulsed laser synchronized to the operation of the circuit and with a circuit simulator modeling program.