Search

Gradient-recalled echo (GRE) echo-planar imaging (EPI) is an efficient MRI pulse sequence that is commonly used for several enticing applications, including functional MRI (fMRI), susceptibility-weighted imaging (SWI), and proton resonance frequency (PRF) thermometry. These applications are typically not performed in the mid-field (<1 T) as longer T2* and lower polarization present significant challenges. However, recent developments of mid-field scanners equipped with high-performance gradient sets offer the possibility to re-evaluate the feasibility of these applications. The paper introduces a metric "T2* contrast efficiency" for this evaluation, which minimizes dead time in the EPI sequence while maximizing T2* contrast so that the temporal and pseudo signal-to-noise ratios (SNRs) can be attained, which could be used to quantify experimental parameters for future fMRI experiments in the mid-field. To guide the optimization, T2* measurements of the cortical gray matter are conducted, focusing on specific regions of interest (ROIs). Temporal and pseudo SNR are calculated with the measured time-series EPI data to observe the echo times at which the maximum T2* contrast efficiency is achieved. T2* for a specific cortical ROI is reported at 0.5 T. The results suggest the optimized echo time for the EPI protocols is shorter than the effective T2* of that region. The effective reduction of dead time prior to the echo train is feasible with an optimized EPI protocol, which will increase the overall scan efficiency for several EPI-based applications at 0.5 T. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive design tutorial for four types of single-stage operational transconductance amplifiers (OTAs): (1) five-transistor OTAs, (2) telescopic cascode OTAs, (3) folded cascode OTAs, and (4) current mirror OTAs. These OTAs serve as fundamental building blocks in analog circuits. The operational principles of each OTA are reviewed, and the key performance metrics are derived through a hand analysis. These performance metrics encompass most crucial parameters, including small-signal parameters, frequency response, input and output swing ranges, rising and falling slew rates, nonidealities, and bias circuit simplicity. All of these metrics are verified and compared using the simulation. Furthermore, the practical applications of each OTA are summarized, and a case study demonstrates the enhancement of a neural recording amplifier's performance through appropriate OTA selection. A thorough review of the essential building blocks will become a stepping stone to design high-performance analog amplifiers across diverse applications. [ABSTRACT FROM AUTHOR]

The focus of an amplifier's design engineer is always on its high gain and bandwidth. While larger transistors can produce higher gains, the trade-off is a narrower bandwidth. On the other hand, increasing an amplifier's DC biassing current results in an increase in its bandwidth, but at the expense of higher power consumption. In order to resolve these conflicts, a new structure for dual output operational transconductance amplifier (DOOTA) using current splitting technique has been proposed in this paper. Current splitting concept has been introduced to obtain two different paths for signal current. The proposed current-splitter DOOTA (CS-DOOTA) requires considerably lower count of circuit components. It shows significant increase in bandwidth, while requiring lower operating current, leading to considerable improvements in small-signal figure of merit. Furthermore, to obtain higher transconductance and slew rate, an improved current splitter-DOOTA (ICS-DOOTA) is proposed. The parameters of this ICS-DOOTA can be improved by increasing the splitting ratio (K) of the MOSFETs. This architecture shows improvements in large-signal figure of merit, due to improvement in its slew rate with higher values of K, while possessing the same dimensions and biasing current. All these results have been verified using Ltspice, in 0.18 µm technology. A high gain CDTA has been implemented using ICS-DOOTA, which is further used in the realization of current-mode KHN filters with different current splitting factors. [ABSTRACT FROM AUTHOR]

Versatile and often used operational amplifier (op-amp) architecture, the two-stage op-amp is appropriate for a variety of analogue circuits and applications, including high-precision amplification and signal conditioning. It offers high gain, which is essential, good frequency response and stability, especially when used with cutting-edge hardware like Complementary Metal-Oxide Semiconductor (CMOS). For high-speed applications that require more bandwidth, this can be a drawback. The CMOS op-amp circuit may produce a consistent output dc offset voltage if improperly built. Modeling of transistors has become an important design procedure to obtain a better op-amp for greater performances. Here we proposed an op-amp compensated with miller capacitance to gain high parametric values such as Gain (AV), unity-gain frequency, Power dissipation, a supply voltage of 1.2V, Slew Rate (SR), Phase margin (PM). The op-amp is simulated using OrCAD Capture to obtain the improved stability and enhance the parameters. The proposed op-amp can be used in high-speed applications and signal conditioning. [ABSTRACT FROM AUTHOR]

An efficient implementation of low-voltage low power two stage fully differential transconductance amplifier using CMOS technology is proposed. In this work, the dynamic threshold voltage MOSFET (DTMOS) and unique adaptive biasing technique are used to obtain the enhanced slew-rate with minimized power supply overhead. This dynamic threshold MOS based fully differential OTA operates at ±0.5 V dual supply voltage. It provides average slew-rate as168 V/μS with 0.104 mW static power consumption. The dc gain of the circuit is calculated as 73.86 dB with a 72° phase margin. The figure of merit of proposed OTA is 16.15 [(V/µs).pF/µW] for the load capacitor of 10 pF, which shows significant improvement compared to prior work. To validate the robustness of the proposed design universal voltage mode filter is designed and simulated as its application. Mentor Graphics Eldospice with 0.18 μm TSMC level 53 CMOS technology has been used to verify the performance of the proposed circuit and its application. [ABSTRACT FROM AUTHOR]

In blood-oxygen-level-dependent (BOLD)-based resting-state functional (RS-fMRI) studies, usage of multi-echo echo-planar-imaging (ME-EPI) is limited due to unacceptable late echo times when high spatial resolution is used. Equipped with high-performance gradients, the compact 3T MRI system (C3T) enables a three-echo whole-brain ME-EPI protocol with smaller than 2.5 mm isotropic voxel and shorter than 1 s repetition time, as required in landmark fMRI studies. The performance of the ME-EPI was comprehensively evaluated with signal variance reduction and region-of-interest-, seed- and independent-component-analysis-based functional connectivity analyses and compared with a counterpart of single-echo EPI with the shortest TR possible. Through the multi-echo combination, the thermal noise level is reduced. Functional connectivity, as well as signal intensity, are recovered in the medial orbital sulcus and anterior transverse collateral sulcus in ME-EPI. It is demonstrated that ME-EPI provides superior sensitivity and accuracy for detecting functional connectivity and/or brain networks in comparison with single-echo EPI. In conclusion, the high-performance gradient enabled high-spatial-temporal resolution ME-EPI would be the method of choice for RS-fMRI study on the C3T. [ABSTRACT FROM AUTHOR]

This paper presents a 2 × VDD mixed-voltage digital output buffer where its slew rate (SR) is automatically adjusted based on PVT (process, voltage, and temperature) detection. The developed buffer is the first to be fabricated using TSMC 16-nm CMOS Logic FinFET Compact (Shrink) LL ELK Cu 1P13 M process. Since slew rate is one of the major required parameters in many interfacing protocols, it is really hard to meet if the mixed-voltage output buffer is needed in FinFET processes. The major reason is the low VDD in these advanced processes. However, our buffer's SR is improved by implementing low threshold voltage (V th) type of device for always-on driving transistors in the Output Stage, thereby increasing the output current. Moreover, since FinFET devices were used in the buffer, the stability of the gate drives of the said driving transistors must be ensured so that noise interference will be avoided. Lastly, the buffer's Timing Shifters used non-overlapping signaling control directly implemented at the transistor level to eliminate the errors caused by delay variations. Based on silicon measurement results, at a load capacitance of 20 pF, the said circuit can be operated at a maximum data rate of 250 MHz for both supply voltages of 0.8 and 1.6 V (namely external VDD or VDDIO), respectively. When the SR auto-adjustment is activated, the SR improvement is at least 49.2% and 37.5% for 0.8 and 1.6 V, respectively. • First mixed-voltage output buffer fabricated using a 16-nm FinFET CMOS process. • Gate driving stabilizer and non-overlapping signaling control are implemented to reduce process variations at high frequencies on the slew rate of the output buffer. • By PVT detection, the slew rate is auto-adjusted to 49.2% and 37.5% for 0.8 and 1.6 V, respectively. • The proposed mixed-voltage buffer matches the requirements of USB 2.0 and DDR3 applications. [ABSTRACT FROM AUTHOR]

In this paper, Astable Multivibrator (AMV) circuits are designed and simulated using pure Carbon Nanotube Field Effect Transistors (CNTFETs) as well as hybrid CNT-CMOS technology, and simulation results are compared with conventional CMOS technology by varying the value of resistor- 'R', capacitor- 'C', supply voltage- 'Vdd' and temperature- 'T'. It has been found that novel CNT-based AMV outperforms conventional CMOS-based AMV and the performance of hybrid circuits exists between PURE-CNT-AMV and CMOS-AMV. The rise time and fall time of PURE-CNT-AMV are improved by 97.2% and 96.5% respectively as compared to CMOS-AMV, which increases the speed of operation of the circuit. A significant improvement of approximately 3515% is observed in the slew rate of PURE-CNT-AMV and also, the amplitude of the output square wave is increased by 0.91%. In addition, the maximum usable frequency for PURE-CNT-AMV is increased by 656.96% as compared to CMOS-AMV. Furthermore, the behavior of CNT-based AMV circuits is also analyzed by varying the number of CNTs- 'N', inter CNT pitch- 'S' and CNT diameter- 'DCNT' at R = 50kΩ, C = 1 pf and Vdd = 0.9 V. However, the power dissipation of PURE-CNT-AMV is 3.7% higher than CMOS-AMV which can be improved by adjusting the value of 'R–C' delay network, operating the circuit at lower supply voltage, and choosing the optimum value of N, S and DCNT. [ABSTRACT FROM AUTHOR]

In this paper, we address the problem of false turn-on effects in a half-bridge GaN power converter in terms of circuit and device parameters. The model shows that the inherent false turn-on problem is caused by slew rates d v ds dt and d v gs dt during the switching transients occurring at the turn-on and off phases. A higher slew rate propagates the gate driver voltage to overshoot beyond the threshold voltage causing it to accidentally turn on This study shows that d v ds dt is dependent on the internal device parameters such as g fs (transconductance) and C oss (output capacitance). From the CV characteristics, it is pretty much evident that the internal capacitances C oss and C rss (reverse transfer capacitance) are reduced with higher drain voltage enabling higher slew rates which increases the probability of false turn-on problems. Experimental results at numerous operating points at 400 V with the variation in different gate drive parameters support the analysis. The highlights of this work are: • Modeling the problem of false turn-on reliability effects in a Half Bridge GaN power converter in terms of circuit and device parameters. • Inherent false turn-on problem is caused by dvds dt and dvgs dt during the switching transients. A higher slew rate propagates the gate driver voltage to overshoot beyond the threshold voltage causing it to accidentally turn on. • d V ds /d t is dependent on internal device parameters like transconductance and output capacitance. • Input capacitances and reverse transfer capacitance are reduced with higher drain voltage enabling higher slew rates which increases the probability of false turn-on problems. [ABSTRACT FROM AUTHOR]

In this paper, a single-stage Super Class-AB operational transconductance amplifier (OTA) using current reuse technique is presented. It is based on two scaled current mirrors located at the tail current nodes of input pairs, reusing the current through the cross-coupled input pairs by a current gain factor of α, and delivering new currents to the output branch, enhancing the overall transconductance (G m) by a factor of (1+α). With adaptive biasing and local common mode feedback (LCMFB), slew rate (SR), open loop gain (A OL) and gain-bandwidth product (GBW) are improved. An prototype has been designed in TSMC 0.18-μm CMOS process. Post-simulation shows the positive and negative slew rate of 22V/μs and −38.3V/μs, respectively, a GBW of 3.72 MHz, a DC gain of 65.6 dB with a phase margin of 69.2° for a capacitive load of 70 pF. The proposed OTA consumes a total power of 16.2 μW under a 1.8V supply voltage. • Transconductance is enhanced through current reuse by a factor of (1+α). • Slew rate, open loop gain and gain-bandwidth of the OTA are simulated and analyzed. • Adaptive biasing and local common mode feedback are utilized. [ABSTRACT FROM AUTHOR]

In this paper, optimum transistor sizing of CMOS differential amplifier using tunicate swarm algorithm (TSA) is proposed. The designing of CMOS differential amplifier is activated to determine the best feasible design parameter values. This work proposes the optimized values of various parameters of a CMOS differential amplifier for better performance. TSA is chosen to optimize the circuit area. TSA has the ability to solve complex functions, like MOS transistor size and bias current. TSA is employed to optimize the parameters of circuit design, like area, power dissipation MOS transistor size, and also used to enhance other circuit specifications, while fulfilling circuit design criteria. The design objectives of CMOS differential amplifier are considered the fitness function of TSA algorithm. Then, weight parameters of CMOS differential amplifier design are optimized using TSA. By CMOS differential amplifier using TSA algorithm, we can optimize circuit design parameters with higher probability of yielding optimal results regarding circuit area lessening, lesser power dissipation and MOS transistor sizes. The proposed method is implemented in the MATLAB platform. The proposed CMOS-DA-TSA method attains 52.01%, 50.29% and 44.30% minimum slew rate, 64.61%, 75.30% and 55.92% minimum power dissipation compared to the existing methods like CMOS-ACD-SOA, CMOS-PAI-FOPSO and CMOS-PSO-MOL, respectively. [ABSTRACT FROM AUTHOR]

A novel operational transconductance amplifier (OTA) having high gain and high bandwidth for high-speed analog communication techniques and precision filtering is designed in this paper. The designed OTA uses β-multiplier-based current biasing scheme with folded cascode amplifier scheme in order to improve the small signal models and the DC gain of circuit. The OTA design was carried out using TSMC 65 nm CMOS technology using Cadence Virtuoso tool with 1 V supply voltage and 10 pf capacitive load. The output DC gain was found to be approximately 75.3 dB. In addition, the unity gain frequency for the designed OTA was found to be around 200 MHz. Superior common mode rejection ratio, power supply rejection ratio and slew rates along with compact chip area and low power are other salient features of the designed OTA. The designed OTA can be employed in order to design high performance analog circuits like data converters, phase-locked loops, etc. [ABSTRACT FROM AUTHOR]

We consider noisy communications and storage systems that are hampered by varying offset of unknown magnitude such as low-frequency signals of unknown amplitude added to the sent signal. We study and analyze a new detection method whose error performance is independent of both unknown base offset and offset’s slew rate. The new method requires, for a codeword length $n\geq 12$ , less than 1.5 dB more noise margin than Euclidean distance detection. The relationship with constrained codes based on mass-centered codewords and the new detection method is discussed. [ABSTRACT FROM AUTHOR]

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode gm-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4 MHz and 132 dB, respectively. The amplifier is operated at 0.6 V dual supply with 89 μ W power consumption and has a nearly symmetrical average slew rate of 51.5 V/ μ s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools. [ABSTRACT FROM AUTHOR]

To improve the transconductance of operational transconductance amplifier (OTA), various architectures namely recycling folded cascode (RFC), Improved recycling folded cascode (IRFC), modified recycling folded cascode (MRFC) and high recycling folded cascode (HRFC) are existing in the literature. In this paper, further improvement in the transconductance of MRFC OTA can be achieved by shorting two nodes of its current mirror and is proposed as high modified recycling folded cascode (HMRFC) amplifier. The performance of the proposed HMRFC OTA is compared with the existing state of art OTAs. To validate the progressions in the specified parameters, recycling folded cascode (RFC), modified recycling folded cascode (MRFC) and high modified recycling folded cascode (HMRFC) OTAs are realized and implemented in UMC 180 nm process technology using Cadence Spectre for a bias current of 1.2 mA. Simulation results indicate that the proposed amplifier exhibits a DC gain of 79.47 dB, the slew rate of 194.2 V/µSec, UGB of 285.85 MHz and phase-margin of 77.12o for a load capacitance of 5 pF and also observed that the CMRR and FoMs of the proposed amplifier are better by a factor of 1.3 and 1.5 in comparison to RFC, and by a factor of 1.27 and 1.41 in comparison to MRFC OTAs respectively.

In this work, we propose a rail-to-rail output buffer with low static-power and high speed for OLED display applications. To guarantee low static power consumption, low tail-current is designed in the buffer's first stage and the output stage is cut off in the static operation. To improve the transient response, dynamic-current-bias technique is used, and it also improves the system stability by pushing away the non-dominant pole. Meanwhile, we balance the large-signal slew-rate and system stability with dual-output buffer structure. Placing compensation resistor across the dual outputs creates zero for suitable phase margin, while the real output still behaves with low ON resistance and keeps high slew rate. The proposed design has been verified by a 0.18 μm 1.8 V/5 V CMOS process, which shows that the buffer only draws 2.8-μA static current. Under a 1-nF capacitance load and a 5-V power supply, the buffer achieves 1.18-μs settling time, which is only 41% of the single-output-stage structure with the same chip size (52 μm × 59 μm). [ABSTRACT FROM AUTHOR]

This brief presents a more detailed model for the slewing behavior of self-biased ring amplifiers and outlines the factors which affect the large signal operation. A set of analytical expressions derived for the self-biased ring amplifier are presented which are valid for a larger portion of a design space than prior expressions. The equations presented are well matched with simulation results and the accuracy of the derived equations is reported. Finally, the paper examines the proposed equations and simulation results to provide insight about design parameter dependence. [ABSTRACT FROM AUTHOR]

In this paper, a class-AB flipped voltage follower cell with high current driving capability is proposed. The proposed flipped voltage follower (FVF) cell offers increased current sourcing capability and large input/output voltage swing due to the use of bulk-driven and level shifter techniques, respectively. Further, it uses an additional NMOS transistor connected between output and ground terminals to increase the current sinking capability and to reduce the output resistance. The stability analysis has been performed by using Routh–Hurwitz stability criteria which confirms that the proposed FVF cell is stable. The proposed FVF cell also offers a high symmetrical slew rate. The proposed FVF cell has been simulated in Cadence virtuoso analog design environment using BSIM3v3 180 nm CMOS technology and simulation results are presented to validate the effectiveness of the proposed circuit. [ABSTRACT FROM AUTHOR]

This paper proposes a unique method of an error detection and correction (EDAC) circuit, carried out using arithmetic logic blocks. The modified logic blocks circuit and its auxiliary components are designed with Boolean and block reduction technique, which reduced one logic gate per block. The reduced logic circuits were simulated and designed using MATLAB Simulink, DSCH 2 CAD, and Microwind CAD tools. The modified, 2:1 multiplexer, demultiplexer, comparator, 1-bit adder, ALU, and error correction and detection circuit were simulated using MATLAB and Microwind. The EDAC circuit operates at a speed of 454.676 MHz and a slew rate of -2.00 which indicates excellence in high speed and low-area.

This paper presents a new architecture for three-stage operational transconductance amplifiers (OTAs) with a class AB input stage to improve the slew rate. The nested Miller compensation scheme is utilized to stabilize the proposed OTA. A nonlinear current mirror in the first-stage is used to implement the class AB operation. Details of the proposed OTA are described and the circuit level simulation results are provided using HSPICE and a 90 nm CMOS technology to verify the usefulness of the proposed OTA. In comparison with the conventional class A OTA, it achieves 284.1% enhancement in the slew rate and the settling time is reduced from 15.7 ns to 9.1 ns with approximately the same power dissipation. [ABSTRACT FROM AUTHOR]

A sub-sampling phase-locked loop (SSPLL) with loop bandwidth calibration is presented. By using a sub-sampling phase detector with gain calibration and a pulse width control circuit, the loop bandwidth deviation of the SSPLL can be reduced. This SSPLL is fabricated in a 40 nm CMOS process and its core area is 0.15mm2. The power consumption of the SSPLL is 5.81mW from a supply of 1.1V. The reference frequency is 75 MHz and the output frequency range of the SSPLL is 2.4~3.0GHz. The measured rms jitter is 2.02ps at the output frequency of 3.0GHz. With the calibration, the largest loop bandwidth deviation from 3.5MHz among five samples is reduced from −71.4% to −18.5% at 3.0GHz. [ABSTRACT FROM AUTHOR]

Ever since the reliability issues caused by I/O (input/output) compatibility among chips fabricated using different processes were raised during mid-2000, on-silicon mixed-voltage I/O buffer with wide voltage tolerance has been considered a better solution than using signal level converters to shrink PCB size, number of discretes, and power consumption. However, various external voltages on I/O pad result in body effect, leakage, hot-carrier degradation, and gate-oxide overstress in stacked transistors of mixed-voltage I/O. What even worse is that slew rate (SR) was also found deteriorated by PVT (Process, Voltage, Temperature) variations. A complete mixed-voltage I/O buffer design flow using nano-scale CMOS processes will be introduced in this tutorial based on previously developed buffers. Besides circuit design methodology, the reliability design consideration for the buffers, including ESD, PVT detection, and slew rate auto-adjustment will be discussed as well. [ABSTRACT FROM AUTHOR]

This brief proposes a $2\times $ VDD I/O buffer featured with precharge timing control to auto-adjust the slew rate. The stacked PMOS and NMOS transistors are widely used in the output stage of the $2\times $ VDD I/O buffer to avoid the gate oxide overstress issue. However, it is hostile to the slew rate besides facing the hot carrier problem in the transient state. The precharging technique is proposed in this brief to improve the SR and avoid the hot carrier problem. The proposed design is carried out using a typical 40 nm CMOS process. The core area is 0.014 mm2. The measured SR is improved to 2.81 V/ns. The measured eye height and eye width are 0.929 V and 0.904 ns, respectively, for VDDIO at 1.8 V. [ABSTRACT FROM AUTHOR]

Purpose. Investigate the nature of the dynamics of changes in the criteria used for interpreting the results of DGA, in serviceable high-voltage transformers, leaky performance. Methodology. Theory of time series, regression analysis, the theory of pattern recognition, the method of reference levels, metric methods of recognition, diagnostics by distance to the standard. Findings. According to the results of the research, it is established that in normal functioning transformers, the values of all the diagnostic features used to interpret DGA results are changed randomly. Emergency actions on the part of the power grid lead to a short-term occurrence of a systematic component in the dependencies of the concentrations and rates of gas build-up on the duration of operation, and to a short-term stabilization of the values of the gas ratios at the level corresponding to this energy impact, as well as to the similarity of the graphic images. Originality. The performed analysis showed that in transformers of leaky performance, the appearance and development of a defect is accompanied not only by a change in the numerical values of the diagnostic criteria, which is known and used in the diagnosis, but also to a significant change in the nature of the dependencies of the diagnostic criteria versus time. Practical value. The obtained results make it possible to detect developing defects in transformers of non-germetic execution at an early stage of their development, even before the values of gas concentrations exceed the boundary values, which will help to avoid the destruction of insulation, and also to recognize the growth of concentrations of gases dissolved in oil, caused by the influence of emergency operation of electrical networks.

The component values and transistor dimensions of a single stage amplifier are the only designable parameters which can be adjusted to achieve optimum performance. The resulting parameters can be set to form an objective function and constraint equations to graphically shape a feasible region which is a polytope. The required optimum value of design parameters is then derived by navigating over each of the corner and internal points of the polytope shaped. Accordingly, the amplifier design problem is conveyed as an optimization problem termed Non Linear Programming (NLP) enlisting decipherable global optimization methods. The present technique yields an automatic analysis of single stage amplifiers inferred from the specification values. In this paper, the proposed technique is first used to express the design problem of a particular amplifier circuit as NLP and then applied to a varied amplifier designs. Comparison of result with existing work implies a superior outcome with respect to achievement of required small signal gain (Av) and unity gain frequency (UGF). The optimal trade-off curves related to performance metrics such as Av, power and UGF are derived in order to observe the corresponding dependencies.

To improve the transconductance of operational transconductance amplifier (OTA), various architectures namely recycling folded cascode (RFC), Improved recycling folded cascode (IRFC), modified recycling folded cascode (MRFC) and high recycling folded cascode (HRFC) are existing in the literature. In this paper, further improvement in the transconductance of MRFC OTA can be achieved by shorting two nodes of its current mirror and is proposed as high modified recycling folded cascode (HMRFC) amplifier. The performance of the proposed HMRFC OTA is compared with the existing state of art OTAs. To validate the progressions in the specified parameters, recycling folded cascode (RFC), modified recycling folded cascode (MRFC) and high modified recycling folded cascode (HMRFC) OTAs are realized and implemented in UMC 180 nm process technology using Cadence Spectre for a bias current of 1.2 mA. Simulation results indicate that the proposed amplifier exhibits a DC gain of 79.47 dB, the slew rate of 194.2 V/µSec, UGB of 285.85 MHz and phase-margin of 77.12o for a load capacitance of 5 pF and also observed that the CMRR and FoMs of the proposed amplifier are better by a factor of 1.3 and 1.5 in comparison to RFC, and by a factor of 1.27 and 1.41 in comparison to MRFC OTAs respectively. [ABSTRACT FROM AUTHOR]

Summary: The paper presents a class‐AB flipped voltage follower (FVF) cell based on quasi‐floating gate and bulk‐driven techniques. The quasi‐floating gate technique is used to increase the current sinking capability, whereas the bulk‐driven technique is used to enhance the current sourcing capability by reducing the threshold voltage. Using these two techniques, the proposed class‐ AB FVF cell offers high current sinking and sourcing capabilities. Also, it provides high symmetrical slew rate without any additional circuitry. The physical layout of the proposed class‐ AB FVF cell has been designed in Cadence Virtuoso Layout XL editor using BSIM3v3 180‐nm CMOS technology, and post‐layout simulation results have been presented to validate its performance. The corner analysis of the proposed class‐ AB FVF cell has also been performed with temperature and supply voltage as design variables to show its performance under extreme conditions. [ABSTRACT FROM AUTHOR]

While trying to represent the performance metrics of a single-stage amplifier as a function of designable parameters, it is observed that the corresponding metrics form a polytope-type feasible region. Indeed, the polytope so formed is made up of performance metrics which can either be objectives or constraints. Initially, the simplex method is used to obtain an objective value that satisfies a set of constraints. Once the objective is available, the interior point-based method is used to check whether any objective lies inside the feasible region or not. The proposed design flow examines both the periphery and the interior of the polytope so generated. Henceforth, the design of an amplifier can be pointed out to be a distinctive type of optimization concern, called Nonlinear Programming (NLP). Furthermore, efficient global optimization methods have been established to yield an automated synthesis of amplifiers derived from the requirements. In this work, the formulation of the design problem for a cascode amplifier as NLP is described and analyzed. Thereafter, the optimal trade-off curves related to the performance metrics such as small signal gain (Av), unity gain frequency (UGF) or gain bandwidth product (GBWP), and power are derived in order to observe the corresponding dependencies. [ABSTRACT FROM AUTHOR]

The energy range of transition-edge sensor (TES) X-ray microcalorimeters with a multiplexed readout depends upon the width and shape of the TES superconducting transition, and also on the dynamic range of the readout. In many detector systems, the multiplexed readout slew rate capability will be the limiting factor for the energy range. In these cases, if we are willing to accept some energy resolution degradation, we can significantly extend the energy range by increasing the bath temperature of operation, essentially creating a second "extended energy range" mode of operation. For example, if we require the very highest energy resolution up to 7 keV, and wish to optimize the design up to this energy, for some measurements it could be very beneficial to have a mode where we can extend the energy range to 15–20 keV even if some energy resolution is sacrificed. In this paper, we explore the trade-off between dynamic range and energy resolution from changing the bath temperature of the TES. We present measurements of TES resolution and slew rate as a function of bath temperature and compare to numerical simulations. [ABSTRACT FROM AUTHOR]