A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique.

This brief proposes a $2\times $ VDD I/O buffer featured with precharge timing control to auto-adjust the slew rate. The stacked PMOS and NMOS transistors are widely used in the output stage of the $2\times $ VDD I/O buffer to avoid the gate oxide overstress issue. However, it is hostile to the slew rate besides facing the hot carrier problem in the transient state. The precharging technique is proposed in this brief to improve the SR and avoid the hot carrier problem. The proposed design is carried out using a typical 40 nm CMOS process. The core area is 0.014 mm2. The measured SR is improved to 2.81 V/ns. The measured eye height and eye width are 0.929 V and 0.904 ns, respectively, for VDDIO at 1.8 V. [ABSTRACT FROM AUTHOR]