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DFM rule based scoring is associated with manufacturability rules checking and applying the scoring to predict the yield entitlement for an IC chip design. Achieving high DFM score is one of the key requirements to get high yield. The DFM scoring methodology is currently limited to DFM recommend rules and their associated failure rates. In contrast to failure mechanism, chemical-mechanical polishing (CMP) step topography variations places an important role to it. In this paper, we present an advanced DFM analysis flow to compute DFM score that incorporate topography variation along with recommend rule scoring using complex scoring model to increase silicon yield correlation.

Chemical Mechanical Polishing (CMP) is the essential process for planarization of wafer surface in semiconductor manufacturing. CMP process helps to produce smaller ICs with more electronic circuits improving chip speed and performance. CMP also helps to increase throughput and yield, which results in reduction of IC manufacturer’s total production costs. CMP simulation model will help to early predict CMP manufacturing hotspots and minimize the CMP and CMP induced Lithography and Etch defects [2]. In the advanced process nodes, conventional dummy fill insertion for uniform density is not able to address all the CMP short-range, long-range, multi-layer stacking and other effects like pad conditioning, slurry selectivity, etc. In this paper, we present the flow for 20nm CMP modeling using Mentor Graphics CMP modeling tools to build a multilayer Cu-CMP model and study hotspots. We present the inputs required for good CMP model calibration, challenges faced with metrology collections and techniques to optimize the wafer cost. We showcase the CMP model validation results and the model applications to predict multilayer topography accumulation affects for hotspot detection. We provide the flow for early detection of CMP hotspots with Calibre CMPAnalyzer to improve Design-for-Manufacturability (DFM) robustness.

CMP effects on manufacturability are becoming more prominent as we move towards advanced process nodes, 28nm and below. It is well known that dishing and erosion occur during CMP process, and they strongly depend on pattern density, line spacing and line width [1] . Excessive thickness or topography variations can lead to shrinkage of process windows, causing potential yield problems such as resist lifting or printability issues. When critical patterns fall into regions with extreme topography variations, they would be more sensitive to defects and could potentially become yield limiters or killers. Scanner tools compensate and correct topography variations by following the given profile [2] . However the scanner exposure window size is wider compared to local topography variations in design. This difference would generate new lithography focus sensitive weak points which may be missed. Experiments have been conducted as shown in Fig 1. Design under manufacturing has been subjected to scanner tool topography focus corrections. Despite of the corrections, Site B topography height has worsened while site A and C shown some improvements. As a result, additional improvements need to be done to meet manufacturability requirements.

This record was migrated from the OpenDepot repository service in June, 2017 before shutting down.

The shrinking dimensions with advanced technologies pose yield challenges which require continuous enhancement of yield methodologies to quickly detect and fix the marginal layout features. In this paper, we present a practical approach to enhance the DFM and DEM capabilities suite provided by GLOBALFOUNDRIES for 28nm technology and beyond. The MDRT system has been implemented in the Product Lifecycle Management (PLM) system within GLOBALFOUNDRIES.

To provide fabless designers the same advantage as Integrated Device Manufacturer (IDMs), a design-oriented litho model has been calibrated and an automated lithography (litho) hotspot detection and fixing flow has been implemented during final routing optimization. This paper shows how a design-oriented litho model was built and used to automate a litho hotspot fixing design flow. The model, calibrated and validated against post-OPC contour data at 99%, was embedded into a Litho Physical Analyzer (LPA) tech file. It allowed the litho contour of drawn layouts to be simulated at full chip level to detect litho hotspots and to provide fixing guidelines. Automated hotspots fixing was hence made possible by feeding the guidelines to the fixing tools in an industry based integrated flow. Post-fixing incremental checks were also performed to converge to a clean design.