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Triaxial HTS AC power cables, that incorporates three HTS phases wound around a single core within a single cable is considering the optimal solution for low and medium voltages. Such a design permits to save expensive HTS conductor and to increase the power density transmitted. It is difficult to increase the transmission capacity of a triaxial cable by increasing its operating voltage and therefore, insulation thickness between phases. The other way is to increase the operation current by using a multilayer structure in each phase of the triaxial cable. This task demands a complicated optimization analysis and a precise manufacturing technology. Following our previous studies, we developed and tested the triaxial cable prototype with two layers per phase made of ReBCO wire. The optimal parameters of the cable (twist pitch, diameters of phases, etc.) have been determined using the numerical simulation methods developed. DC and AC tests of the cable has been performed. In the result, the feasibility to provide a uniform current distribution in a triaxial cable, each phase of which consists of two layers, has been demonstrated. With the outer diameter of ∼24 mm only, this is the most compact triaxial HTS power cable manufactured and tested up to date with currents up to 4 kA per phase. The anticipated power transfer with three phases of this cable can be as large as ∼34 MW.

We have proposed and demonstrated novel twin-hole and dual-core optical fiber. We used the normal MCVD technology to fabricate a single core fiber preform with a thin cladding. Then, two small holes were drilled in the center and on the side of the pure silica rod, the fabricated single-core fiber preform was inserted into the two holes, and then the combined preform was heated until three parts were fused. Finally, two larger holes were drilled close the center core and twin-core and dual-hole are vertically distributed. In order to retain the shape of air hole, we filled nitrogen gas in the two holes to against the ambient pressure, which made the holes collapse during the fiber drawing. The dual-hole microstructure may be used as micro-containers to inject modulation medium and aside the center core, and to induce accumulated interaction between flow material and evanescent field of the center core, therefore, it can be used as a modulation function fiber to fabricate a very compact in-fiber integrated device.

At present, research of cable fault diagnosis based on artificial intelligence mainly takes statistical characteristics as inputs, which means the appropriateness of statistical characteristic selection is directly related to the diagnosis accuracy and the identification results may have certain contingency. Further, most of these methods do not consider the correlation of signals in time. Therefore, this paper proposes a novel diagnosis method for 10 kV single-core cable based on Double-Layer Long Short Term Memory (D-LSTM) network considering timing relationship of multiple observable electrical quantities. Firstly, analysis object is expanded from single electrical quantity to multiple observable electrical quantities, and the relationships among these quantities are analyzed. Secondly, characteristic matrix of combined time series is constructed by time series pairs extracted from multiple observable electrical quantities. Thirdly, the D-LSTM network for processing sequenced input is established according to the features of characteristic matrix. Then, adaptive moment estimation (Adam) method is applied to model training under supervised learning and the model of fault diagnosis is obtained. Finally, recognition experiments are carried out by the proposed method with sample data obtained by simulation of three cable faults and load disturbance. Results show the diagnosis accuracy of proposed method can achieve 99.06%.

Belt conveyors are used for transporting bulk materials over distances. The core of the belt, by transferring the longitudinal stresses and ensuring proper frictional coupling of the belt, enables belt movement and transportation of materials on its surface. As the belt cover and edges are used, the belt becomes abraded, and the core is subject to fatigue. The result is the development of cracks in rubber covers across the belt, which leads to the development of damage not only along the cables (the natural direction of water migration and corrosion) but also in the direction transverse to the belt axis. Conducting a series of scans of the St-type belt operating in one of the underground copper ore mines in Poland allowed identifying the number of failures as well as their size and changes over time. These data were in turn used to determine the measures defining the condition of the belt such as the density of defects (the number of defects per 1 m of the belt), the density of the area of damage (the area of damage per 1 m of the belt) and the change in the average area of a single defect over time. By determining the regression of these measures in time and the rate of damage development in both directions (along the axis of the belt and across the belt), it was possible to forecast future states of the belt, as well as to evaluate the costs of different belt replacement strategies and the economic rationalization of the decision to replace them. This research has become possible owing to the development of the DiagBelt system for two-dimensional imaging of the damage to the core of steel-cord belts with resolution sufficiently high to allow tracking the development of single core defects.

In a gravity-free or microgravity environment, liquid metals without crystalline nuclei achieve a deep undercooling state. The resulting melts exhibit unique properties, and the research of this phenomenon is critical for exploring new metastable materials. Owing to the rapid crystallization rates of deeply undercooled liquid metal droplets, as well as cost concerns, experimental systems meant for the study of liquid metal specimens usually use low-resolution, high-framerate, high-speed cameras, which result in low-resolution photographs. To facilitate subsequent studies by material scientists, it is necessary to use super-resolution techniques to increase the resolution of these photographs. However, existing super-resolution algorithms cannot quickly and accurately restore the details contained in images of deeply undercooled liquid metal specimens. To address this problem, we propose the single-core multiscale residual network (SCMSRN) algorithm for photographic images of liquid metal specimens. In this model, multiple cascaded filters are used to obtain feature information, and the multiscale features are then fused by a residual network. Compared to existing state-of-the-art artificial neural network super-resolution algorithms, such as SRCNN, VDSR and MSRN, our model was able to achieve higher PSNR and SSIM scores and reduce network size and training time.

Beyond 5G systems are expected to approach 1 Tb/s throughput. This poses a significant challenge to the channel decoder. In this paper, we propose a multi-core architecture based on full row parallel layered LDPC decoder with frame interleaving. Compared with conventional partially parallel layered architectures, the proposed architecture increases the throughput by applying frame interleaving into the pipeline architecture and by using multi-core architectures. Two high rate medium size QC LDPC codes are designed with fast decoding convergence speed for this architecture. Both codes are implemented with single core and multi-core architectures to explore different trade-offs between code design, communication performance and implementation. The four decoders are implemented in 16 nm CMOS FinFET technology with a clock rate of 1 GHz. The placement and routing implementation results show that the single core decoder for the LDPC (1027, 856) code is able to provide 114 Gb/s throughput at maximum 3 iterations with an area of 0.173 mm2 and energy efficiency of 1.56 pJ/bit; the multi-core decoder for the (1032, 860) code is able to provide 860 Gb/s throughput at maximum 2 iterations with an area of 1.48 mm2 and energy efficiency of 3.24 pJ/bit. The multi-core decoder achieves the highest throughput in the literature for medium size (1–2k) LDPC codes. When compared with other state-of-the-art fully parallel high speed architectures, the proposed architectures bring a significant gain both in area efficiency and energy efficiency while keeping the ability to offer flexibility in code rate, number of iterations and early stop.

Stencil computations within a single core or multicores of an SMP node have been over-investigated. However, the demands on HPC’s higher performance and the rapidly increasing number of cores in modern processors pose new challenges for program developers. These cores are typically organized as several NUMA nodes, which are characterized by remote memory across nodes and local memory with uniform memory access within each node. In this paper, we conducted experiments of stencil computations on NUMA systems based on the two most typical processors, ARM and Intel Xeon E5. We leverage a hybrid programming approach by combining MPI and OpenMP to exploit the potential benefits among NUMA nodes and within a NUMA node. Optimizations of the two selected 3D stencil computations involve four-level parallelism: block decomposition for NUMA nodes and processes, thread-level parallelism within a NUMA node, and data-level parallelism within a thread based on SIMD extension. Experimental results show that we obtain a maximum speedup of 7.27 $${\times }$$ compared to the pure OpenMP implementations on the ARM platform and 11.68 $${\times }$$ on the Intel platform.

The performance of a double-core prefabricated vertical drain (PVD), which could reduce the well resistance via its large cross-sectional area and structural stability, was investigated experimenta...

We investigate high-throughput, multi-band transmission in a 4-core multi-core fiber (MCF) with the same 125 μm cladding diameter of standard single-mode fiber (SMF). A single wideband comb source is used to transmit up to 561 wavelength channels with 25 GHz spacing over a 120 nm bandwidth in S, C, and L bands. We demonstrate a maximum decoded throughput of 610 Tb/s in PDM-256QAM and PDM-64QAM signals over a 54 km fiber, transmitting more than 155 Tb/s in a single core and measuring a per-core average throughput exceeding record transmission demonstrations in SMF. In addition, we use noise loading measurements to characterize the achievable signal quality across the wideband transmitter. These results show that a single comb source can enable high-spectral efficiency modulation over wide bandwidths and further that low-core count homogeneous MCF technology can offer the same transmission performance as single-mode fibers without sacrificing mechanical reliability, and still offering the benefits of shared resources and greater efficiency that drives SDM technologies.

As multiple functions have been added to single-core-based engine electronic control units (ECUs) in vehicles, automotive researchers and manufacturers have actively studied multi-core architecture for engine ECUs. Multi-core architecture can provide load balancing and parallelism that can meet the requirements of international organization standard (ISO) 26262. However, since real-world engine ECUs have the most complex automotive open system architecture (AUTOSAR)-based control logic and datasets among automotive ECUs, developing multi-core-based engine ECUs is a substantial amount of work. Thus, automotive researchers and manufacturers will need new methodologies for multi-core-based engine ECUs. In this paper, we focus on designing a multi-core migration methodology and applying it to a real-world AUTOSAR-based engine ECU from HYUNDAI. We verify its practicability and enhanced performance. In conclusion, through connection with other automotive domain ECUs, it is demonstrated that a multi-core engine ECU using our migration technology can be applied in real-world automotive vehicles, leading to a significant improvement in performance.

Direction-of-arrival (DOA) estimation algorithm for uniform planar arrays has been applied in many fields. The multiple signal classification (MUSIC) algorithm has obvious advantage in high-resolution signal source estimation scenarios. However, the MUSIC algorithm has high computational costs, therefore it is hard to be used in real-time scenes. Many studies are dedicated to accelerating MUSIC algorithm by parallel hardware, especially by Graphics Processing Units (GPU). MUSIC algorithm based on Central Processing Unit (CPU) -GPU architecture acceleration is rarely investigated in previous literatures, and how well MUSIC Algorithm with CPU-GPU architecture could perform remains unknown. In this paper, we present and evaluate a model of search parallel MUSIC algorithm with CPU-GPU architecture. In the proposed model, the steering vector of each candidate incident signal and the corresponding value of 2D spatial pseudo-spectrum (SPS) function are sequentially calculated in a single core of the GPU, and the subsequent calculation of each elevation or azimuth is parallel in batches. Furthermore, in order to improve the peak search speed, we propose a new Coarse and Fine Traversal (CFT) peak search algorithm via CPU and a new parallel peak search algorithm based on GPU acceleration. Across strategy comparison, utilizing CPU-GPU architecture for processing, a 150-160x performance gain is achieved compared to using CPU only. Besides, the resolution of uniform planar arrays is also analyzed.

Recent studies on compact and lightweight electronic devices have demonstrated that the LLC resonant converter (LRC) can facilitate achieving high efficiency and high power density. Moreover, employing a planar transformer can further improve the overall system power density. Although the planar transformer can assist in reducing the size of the converter, its high magnetic coupling makes the leakage inductance too small for a resonant inductor in the LRC. Therefore, an extra inductor must be employed separately, leading a considerable decrease in the power density. From this reason, significant research on integrated magnetics has been conducted to combine a transformer and external inductor into a single core. However, they require additional wires or magnetic sheets, and their structures are complex and costly. To overcome these limitations, the integrated magnetics planar transformer (IMPT) for a high power density LRC is proposed in this paper. In the proposed approach, since the primary wire is split into each side leg of the EE-type magnetic core and each operates as a transformer and a resonant inductor alternatively, an external inductor or additional wires are unnecessary. In addition, since the magnetic flux density of the IMPT is approximately equivalent to that of conventional transformer, the core size and the number of turns are almost the same. Therefore, the proposed IMPT features higher efficiency and power density without additional size and costs. To confirm the validity of the proposed IMPT, the operational principles, theoretical analysis, design considerations, and experimental results from a 350 W prototype are presented.

Insulated underground cables have the potential to reduce power outages, maintenance costs, and transmission losses compared to overhead lines. On the other hand, they are exposed to several risks and physical damages, since they are buried in the ground. Though the cables are armoured in order to provide mechanical protection and achieve tensile strength, and also to provide effective conductance of earth fault currents. The main purpose of this paper is to introduce insulated underground cables, armouring process, and to analyze the induced currents in metallic parts such as sheath and armour that causeohmic losses which are categorized mainly in two groups as circulating current and eddy current. This paper presents a review on analytical techniques used to analyze the effect of magnetic fields, andcalculate the losses in the armour of the cables, besides providing the strategies and solutions used for armour loss reduction.

RISC-V has been experiencing explosive growth since its first appearance in 2011. Dozens of free and open cores developed based on this instruction set architecture have been released, and RISC-V based devices optimized for specific applications such as the IoT and wearables, embedded systems, AI, and virtual, augmented reality are emerging. As the RISC-V cores are being used in various fields, the demand for multicore platforms composed of RISC-V cores is also rapidly increasing. Although there are various RISC-V cores developed for each specific application, and it seems possible to pick them up to create the most optimized multicore for the target application, unfortunately it is very difficult to realize this in reality. This is mainly because most open cores are released in the form of a single core without cache coherence logic, which requires expensive design effort and development costs to address it. To tackle this issue, this paper proposes a method to solve the cache coherence problem without additional effort from the developer and to maximize the performance of the multicore composed of the RISC-V core selected by the developer. Along with a description of the sophisticated operating mechanisms of the proposed method, this paper details the architecture and hardware implementation of the proposed method. Experiments conducted through the prototype development of a RISC-V multicore platform involving the proposed architecture and development of an application running on the platform demonstrate the effectiveness of the proposed method.

In highly advanced real-time critical applications, the demand of multi-core processing is increasing as the tasks are assigned to cores in the most balanced manner. The balancing of tasks on the cores requires an efficient load balancing algorithm. To balance the loads amongst the cores, all harmonic tasks can be grouped together and shall be assigned on a single core. The concept of harmonic task set is effective as it tends to reach a utilization of one, and thus, the system achieves a higher utilization. The proposed paper is focused on harmonic-aware load balancing algorithm for a set of periodic real-time tasks having constrained deadlines, where the deadline of the tasks is less than the period of the tasks. The extensive analysis was performed to establish the superiority of harmonic task sets in real-time applications. The results of this analysis are reported in this paper. It was observed that by considering the tasks’ harmonic relationship, the proposed load balancing approach greatly improves the feasibility of real-time tasks on a multi-core processor to meet their deadlines.

Dynamic frequency scaling (DFS) is one of the most important approaches for on-the-fly power optimization in modern-day processors. Owing to the trend of chip size shrinkage and increasing the complexity of system design, the problem of achieving an efficient DFS depends upon multi-parametric, non-linear optimization. Hence, it becomes extremely important to identify an optimal underclocking frequency on-the-fly, which depends upon numerous parameters that do not share direct relationship amongst each other. This paper proposes a machine learning approach to DFS of a ubiquitous single-core processor. Several performance parameters of the processor were monitored under an application of a number of clocking frequencies. The dataset thus generated was used to train four artificial neural networks (ANNs) viz. generalized regression (GRNN), decision tree classifier, random forest classifier and backpropagation technique. Under changing parametric conditions of the proposed network, the modes were fit to data while running three applications, i.e. 64- and 1024-point fast fourier transform (FFT) and basicmath applications. The performance of all ANNs was found to be promising and good generalization was obtained with all datasets. In the view of optimizing both speed and power of a system, the results indicate towards suitability of trained GRNN for on-chip deployment for implementing DFS.

Geometric comparisons of binding sites and their electrostatic properties can identify subtle variations that select different binding partners and subtle similarities that accommodate similar partners. Because subtle features are central for explaining how proteins achieve specificity, algorithmic efficiency and geometric precision are central to algorithmic design. To address these concerns, this paper presents pClay, the first algorithm to perform parallel and arbitrarily precise comparisons of molecular surfaces and electrostatic isopotentials as geometric solids. pClay was presented at the 2019 Workshop on Algorithms in Bioinformatics (WABI 2019) and is described in expanded detail here, especially with regard to the comparison of electrostatic isopotentials. Earlier methods have generally used parallelism to enhance computational throughput, pClay is the first algorithm to use parallelism to make arbitrarily high precision comparisons practical. It is also the first method to demonstrate that high precision comparisons of geometric solids can yield more precise structural inferences than algorithms that use existing standards of precision. One advantage of added precision is that statistical models can be trained with more accurate data. Using structural data from an existing method, a model of steric variations between binding cavities can overlook 53% of authentic steric influences on specificity, whereas a model trained with data from pClay overlooks none. Our results also demonstrate the parallel performance of pClay on both workstation CPUs and a 61-core Xeon Phi. While slower on one core, additional processor cores rapidly outpaced single core performance and existing methods. Based on these results, it is clear that pClay has applications in the automatic explanation of binding mechanisms and in the rational design of protein binding preferences.

The growing share of medium voltage cable lines in distribution networks challenges distribution network operators in terms of proper mode of operation of these lines. It is related to the reduction of energy losses in cable conductors and metallic cable screens. The article focuses on energy losses in metallic cable screens of cable lines and substation busbar bridges composed of single-core cables with metallic screens and possible ways of their reduction. Simulation and measurement analysis of the level of energy losses in the metallic screens of cables is presented together with the economic analysis of various variants of losses reduction through the change of the way these screens are operated in relation to the traditional bilateral earthing at both ends of cable. Technical problems and threats connected with the use of considered modifications of metallic screens operation during earth fault disturbances in distribution networks are also presented

On top of the wear-out failures and external particle interventions, voltage scaling to mitigate the power consumption in multiprocessor makes cache more vulnerable to cell failures. For the indispensable voltage reduction to prolong the battery life of handheld devices, fault tolerance techniques are extremely important to ensure fault free execution in near-threshold voltage. Several fault tolerance techniques have been proposed and the remapping based techniques are found to be effective to address the issue of fault tolerance in single core systems. This work proposes an analytical model for remapping based fault tolerance techniques to evaluate the effectiveness of such schemes in multicore systems. The metrics Expected Miss Ratio in Multicore (EMRMC) and Expected Latency Ratio in Multicore (ELRMC), are introduced to characterize the behavior of remapping based techniques. The EMRMC and ELRMC are defined as the function of probability of cell failure (Pfail), block size, number of cores and threads. The system is simulated in Multi2sim 5.0, a multicore CPU-GPU simulator. The values of the metrics for different configuration parameters like probability of cell failure, number of cores, number of blocks, block size and number of threads are analysed for framing the guidelines of system configuration to deliver better performance in remapping based fault tolerance. It is observed that the EMRMC is proportional to Pfail and block size but inversely proportional to the number of cores and threads and it is not affected by the number of blocks. On the contrary, the ELRMC is inversely proportional to Pfail and block size and proportional to the number of cores and threads. It is also observed that the ELRMC is independent of the number of cores and blocks. EMRMC is best minimized for Pfail ≤ 1e-4, block size ≤ 64 bytes, number of cores ≥ 4 and number of threads ≥ 2. On the other hand, ELRMC is best observed for Pfail ≤ 1e-4, block size ≥ 64 bytes, number of cores ≥ 4 and number of threads 2.

The present study draw a bead on preparing single core osmotic pump with improved water transplant by employing Quality by Design (QbD) principles to achieve zero order drug release for prolonged period of time. QbD principles were employed in preparing single core osmotic pump by deriving quality target product profile (QTPP), critical quality attributes (CQA) followed by risk assessment using ishikawa diagram and risk estimation matrix. Box-Behnken Design was employed to study the effect of various independent parameters like concentration of Natrosol 250 HX (X1) and concentration of Xylitab (X2) no. of orifice (X3), on various dependent parameters like lag time (Y1) and time required for release 25%, 50%, 75% and 100% drug (Y2, Y3, Y4 and Y5). A controlled space was designed where each criteria or CQA was satisfied. Optimized formulation was further characterized for its efficiency. The results of design suggest the suitability of design for optimization of single core osmotic pump. In the initial period, drug release was driven by no. of orifice which on later stage depends on concentration of swellable polymer and concentration of osmogen. Optimized design was validated by preparing check point batch having less than 5% predicted error. Model fitting with drug release kinetics showed that optimized single core osmotic pump released drug in zero order. Stability data suggested that prepared formulation was stable for 3 month period without significant changes in the CQA. Single core osmotic pump using water transplant was successfully developed for a poorly soluble drug using QbD principles.

Single nanowire memory units are of particular interest in the design of high-density nanoelectronic circuits, but the performance due to weak contact state remains a major problem. In this paper, bonding between core/shell SiC/SiO2 nanowire and Au electrodes can be improved via local contact engineering with femtosecond (fs) laser irradiation. An optimized heterojunction (Au-SiO2-SiC) is possible since plasmonic enhanced optical absorption can be localized at the metal-oxide (Au-SiO2) interface. Electron transport across the barrier and charge accumulation at the oxide-semiconductor (SiO2-SiC) interface are improved in nanowire circuits. A fast and stable resistance change can be achieved after only one biasing cycle ('write') and the written state can be read/extracted at a low voltage (∼ 0.5 V). Unlike other as-built nanowire circuits, the resistance state can be retained for 10 min in the absence of external power, indicating that these devices can be used for short-term memory units. High current tolerance is also provided in the circuit by the surface oxide shell which acts to protect the inner SiC core. The current density carried by the single SiC/SiO2 nanowire circuit can be as high as ∼3 × 106 A cm-2 before break down, and that breakdown occurs as a two-stage process.

As the need for on-device machine learning is increasing recently, embedded devices tend to be equipped with heterogeneous processors that include a multi-core CPU, a GPU, and/or a DNN accelerator called a Neural Processing Unit (NPU). In the scheduling of multiple deep learning (DL) applications in such embedded devices, there are several technical challenges. First, a task can be mapped onto a single core or any number of available cores. So we need to consider various possible configurations of CPU cores. Second, embedded devices usually apply Dynamic Voltage and Frequency Scaling (DVFS) to reduce energy consumption at run-time. We need to consider the effect of DVFS in the profiling of task execution times. Third, to avoid overheat condition, it is recommended to limit the core utilization. Lastly, some cores will be shut-down at run-time if core utilization is not high enough, in case the hot-plugging option is turned on. In this paper, we propose a scheduling technique based on Genetic Algorithm to run DL applications on heterogeneous processors, considering all those issues. First, we aim to optimize the throughput of a single deep learning application. Next, we aim to find the Pareto optimal scheduling of multiple DL applications in terms of the response time of each DL application and overall energy consumption under the given throughput constraints of DL applications. The proposed technique is verified with real DL networks running on two embedded devices, Galaxy S9 and HiKey970.

The reduction of the overall budget of the project leads to the cost effective one and there should besuch criteria of reduction of the cost in different manner. To make economic structure without losing the stiffnesscriteria, the work has been performed in two stages. The former one is building with single shear wall core andthe latter one is building with dual core shear wall; the entire work has performed with four different phases. Infirst phase total 5 buildings that are modeled with different openings in single core types shear wall and thensecond phase performs the analysis procedures of the same. The third phases have total 6 buildings that aremodeled with different openings in dual core types shear wall and then fourth phase performs the analysisprocedures of the same. The result analysis has been performed and then conclusions are drawn. Building with25% opening area in single core type shear wall and 50% opening area in dual core type shear wall performswell to reduce the cost of the project.

The temperature distribution along the length of the termination of a single core cable as well as the maximum temperature location are calculated using an analytical method. Also, parameters affecting the maximum temperature along the length of the medium voltage cable termination such as the ambient temperature, the cable load current, insulation thermal conductivity, and termination dimensions (outer jacket length, length of the semi-conductor, length of the field regulator, thickness of the insulation, and thickness of the jacket) are discussed. The analytical method used is based on the heat flow produced by the cable conductor and heat transfer by conduction, convection, and radiation.

Recently, one type of mesoscale structure called core-periphery (CP) structure has received much attention in complex networks, as the algorithmic detection of such structures makes it possible to discover network features that are not apparent either at the local scale of nodes and edges or at the global scale of summary statistics. The core-periphery structure refers to that core nodes are densely interconnected, while periphery nodes are connected to core nodes to different extents, and periphery nodes are sparsely interconnected. Core-periphery structure containing a single core or multiple cores has been identified in various networks. However, investigation of the detection problems of the core-periphery has not been summarized in the literature. In this paper, we first introduce the definition of the core-periphery structure. The core-periphery structure has been paid more and more attention by researchers in various fields since its introduction, and it has been proved to be a powerful tool to analyze the theory of various topologies in our society, we briefly expounded the application of core-periphery structure in economics, sociology, medicine and other fields, and revealed the huge development potential of this theory. Then, we give a detailed overview of classical detection algorithms since the core-periphery structure theory was proposed. Finally, we give the development characteristics and the possible research directions of the core-periphery detection algorithm.

Motivation Fast, lightweight methods for comparing the sequence of ever larger assembled genomes from ever growing databases are increasingly needed in the era of accurate long reads and pan-genome initiatives. Matching statistics is a popular method for computing whole-genome phylogenies and for detecting structural rearrangements between two genomes, since it is amenable to fast implementations that require a minimal setup of data structures. However, current implementations use a single core, take too much memory to represent the result, and do not provide efficient ways to analyze the output in order to explore local similarities between the sequences. Results We develop practical tools for computing matching statistics between large-scale strings, and for analyzing its values, faster and using less memory than the state-of-the-art. Specifically, we design a parallel algorithm for shared-memory machines that computes matching statistics 30 times faster with 48 cores in the cases that are most difficult to parallelize. We design a lossy compression scheme that shrinks the matching statistics array to a bitvector that takes from 0.8 to 0.2 bits per character, depending on the dataset and on the value of a threshold, and that achieves 0.04 bits per character in some variants. And we provide efficient implementations of range-maximum and range-sum queries that take a few tens of milliseconds while operating on our compact representations, and that allow computing key local statistics about the similarity between two strings. Our toolkit makes construction, storage and analysis of matching statistics arrays practical for multiple pairs of the largest genomes available today, possibly enabling new applications in comparative genomics. Availability and implementation Our C/C++ code is available at https://github.com/odenas/indexed_ms under GPL-3.0. The data underlying this article are available in NCBI Genome at https://www.ncbi.nlm.nih.gov/genome and in the International Genome Sample Resource (IGSR) at https://www.internationalgenome.org. Supplementary information Supplementary data are available at Bioinformatics online.

Colloidosomes, also known as Pickering emulsion capsules, have attracted attention for encapsulation of hydrophilic and hydrophobic actives. However, current preparation methods are limited to single core structures and require the use of modified/engineered nanoparticles for forming the shell. Here, we report a fast, simple, and versatile method for producing multi-oil core silica colloidosomes via salt-driven assembly of purely hydrophilic commercial nanoparticles dispersed within an Oil-In-Water-In-Oil (O/W/O) double emulsion template. The internal structure and overall diameter of the capsules can be adjusted by altering the primary and secondary emulsification conditions. With this approach, 7 to 35 µm diameter multicore colloidosomes containing 0.9 to 4.2 µm large oil cores were produced. The capsules can easily be functionalized depending on the type of nanoparticles used in the preparation process. Here, metal oxide nanoparticles, such as Fe3O4, TiO2 and ZnO, were successfully incorporated within the structure, conferring specific functional properties (i.e. magnetism, photocatalysis) to the final microcapsules. These capsules can also be ruptured using ultrasound, enabling easy access to the internal core environments. Therefore, we believe this work offers a promising approach for producing multicore colloidosomes with adjustable structure and functionalities for the encapsulation of hydrophobic actives.

Anode saturable reactor (ASR) is an important part of the HVDC converter valve. Due to the surge current during the transient processes of thyristors, a sharp increase will occur in core losses and over temperature-rising of the reactor, which may cause premature failure and is difficult to estimate in the design optimization of the reactors. To investigate the single core loss of anode saturable reactor, during such operating conditions, this paper proposes an approach to calculate the core loss from the Jiles-Atherton ( J-A ) dynamic hysteresis model, which can be applied for various operating conditions with good accuracy. Finally, the model is incorporated into the finite element method (FEM) to investigate the core loss distribution of the iron core during the oscillation process at off-state.

Background The membrane potential of individual neurons depends on a large number of interacting biophysical processes operating on spatial-temporal scales spanning several orders of magnitude. The multi-scale nature of these processes dictates that accurate prediction of membrane potentials in specific neurons requires the utilization of detailed simulations. Unfortunately, constraining parameters within biologically detailed neuron models can be difficult, leading to poor model fits. This obstacle can be overcome partially by numerical optimization or detailed exploration of parameter space. However, these processes, which currently rely on central processing unit (CPU) computation, often incur orders of magnitude increases in computing time for marginal improvements in model behavior. As a result, model quality is often compromised to accommodate compute resources. New Method Here, we present a simulation environment, NeuroGPU, that takes advantage of the inherent parallelized structure of the graphics processing unit (GPU) to accelerate neuronal simulation. Results & comparison with existing methods NeuroGPU can simulate most biologically detailed models 10–200 times faster than NEURON simulation running on a single core and 5 times faster than GPU simulators (CoreNEURON). NeuroGPU is designed for model parameter tuning and best performs when the GPU is fully utilized by running multiple (> 100) instances of the same model with different parameters. When using multiple GPUs, NeuroGPU can reach to a speed-up of 800 fold compared to single core simulations, especially when simulating the same model morphology with different parameters. We demonstrate the power of NeuoGPU through large-scale parameter exploration to reveal the response landscape of a neuron. Finally, we accelerate numerical optimization of biophysically detailed neuron models to achieve highly accurate fitting of models to simulation and experimental data. Conclusions Thus, NeuroGPU is the fastest available platform that enables rapid simulation of multi-compartment, biophysically detailed neuron models on commonly used computing systems accessible by many scientists.

High-level, ab initio calculations find that the 4-body (4-b) interaction is needed to account for near-100% of the total interaction energy for water clusters as large as the 21-mer. Motivated by this, we report a permutationally invariant polynomial potential energy surface (PES) for the 4-body interaction. This machine-learned PES is a fit to 2119 symmetry-unique, CCSD(T)-F12a/haTZ 4-b interaction energies. Configurations for these come from tetramer direct-dynamics calculations, fragments from an MD water simulation at 300 K, and tetramer fragments in a variety of water clusters. The PIP basis is purified to ensure that the PES goes rigorously to zero in monomer+trimer and dimer+dimer dissociations. The 4-b energies of isomers of the hexamer calculated with the new PES are shown to be in better agreement with benchmark CCSD(T) results than those from the MB-pol potential. Tests on larger clusters further validate the high-fidelity of the PES. The PES is shown to be fast to evaluate, taking 2.4 s for 105 evaluations on a single core of 2.4 GHz Intel Xeon processor, and significantly faster using a parallel version of the PES.

ECDSA is a standard digital signature scheme that is widely used in TLS, Bitcoin and elsewhere. Unlike other schemes like RSA, Schnorr signatures and more, it is particularly hard to construct efficient threshold signature protocols for ECDSA (and DSA). As a result, the best-known protocols today for secure distributed ECDSA require running heavy zero-knowledge proofs and computing many large-modulus exponentiations for every signing operation. In this paper, we consider the specific case of two parties (and thus no honest majority) and construct a protocol that is approximately two orders of magnitude faster than the previous best. Concretely, our protocol achieves good performance, with a single signing operation for curve P-256 taking approximately 37 ms between two standard machine types in Azure (utilizing a single core only). Our protocol is proven secure for sequential composition under standard assumptions using a game-based definition. In addition, we prove security by simulation under a plausible yet non-standard assumption regarding Paillier. We show that partial concurrency (where if one execution aborts, then all need to abort) can also be achieved.

Simulation of quantum computing on supercomputers is a significant research topic, which plays a vital role in quantum algorithm verification, error-tolerant verification, and other applications. Tensor-network contraction based on density matrix is an important single-amplitude simulation strategy, but it is hard to execute on the distributed computing systems. In this paper, we studied the problem in detail, and propose a scheme based on cutting edges of undirected graphs. This scheme cuts edges of undirected graphs with large tree width to obtain many undirected subgraphs with small tree width, and these subgraphs contracted on different computing cores. The contraction results of slave cores are summarized in the master node, which is consistent with the original tensor-network contraction. Thus, we can simulate the larger scale quantum circuit than single core. Moreover, it is an NP-hard problem to find the global optimum cutting edges, and we propose a search strategy based on a heuristic algorithm to approach it. In order to verify the effectiveness of our scheme, we conduct tests based on the quantum approximation optimization algorithm (QAOA) and Shor's algorithm, and it can simulate a 120-qubit three-regular QAOA algorithm on a 4096-core supercomputer, which greatly exceeds the simulation scale on a single core of 100 qubits.

Analogue series play a key role in drug discovery. They arise naturally in lead optimization efforts where analogues are explored based on one or a few core structures. However, it is much harder to accurately identify and extract pairs or series of analogue molecules in large compound databases with no predefined core structures. This methodological review outlines the most common and recent methodological developments to automatically identify analogue series in large libraries. Initial approaches focused on using predefined rules to extract scaffold structures, such as the popular Bemis–Murcko scaffold. Later on, the matched molecular pair concept led to efficient algorithms to identify similar compounds sharing a common core structure by exploring many putative scaffolds for each compound. Further developments of these ideas yielded, on the one hand, approaches for hierarchical scaffold decomposition and, on the other hand, algorithms for the extraction of analogue series based on single-site modifications (so-called matched molecular series) by exploring potential scaffold structures based on systematic molecule fragmentation. Eventually, further development of these approaches resulted in methods for extracting analogue series defined by a single core structure with several substitution sites that allow convenient representations, such as R-group tables. These methods enable the efficient analysis of large data sets with hundreds of thousands or even millions of compounds and have spawned many related methodological developments.

This paper introduces parallel computation for spread options using two-dimensional Fourier transform. Spread options are multi-asset options whose payoffs depend on the difference of two underlying financial securities. Pricing these securities, however, cannot be done using closed-form methods; as such, we propose an algorithm which employs the fast Fourier Transform (FFT) method to numerically solve spread option prices in a reasonable amount of short time while preserving the pricing accuracy. Our results indicate a significant increase in computational performance when the algorithm is performed on multiple CPU cores and GPU. Moreover, the literature on spread option pricing using FFT methods documents that the pricing accuracy increases with FFT grid size while the computational speed has opposite effect. By using the multi-core/GPU implementation, the trade-off between pricing accuracy and speed is taken into account effectively.

The knowledge of multi-core programming helps in the utilisation of multiple cores at the same time to execute a task and thereby achieving scalability and increase in performance. Different parallelism models exist such as task-level parallelism, bit-level parallelism, instruction-level parallelism, unstructured parallelism depending on the data or control centric nature of tasks. The focus of this work is task-level parallelism. Programming languages such as Java provide APIs to divide tasks into subtasks and execute over multiple cores rather than on single core. Java provides three prominent APIs: Executor, Fork-Join and Parallel Streams frameworks to achieve task-level parallelism. Since each framework has its merits and demerits, the choice of a framework depends on the task and the interdependencies between the sub-tasks. This paper has surveyed the structure of the data and the algorithm underlying the task in the light of three aforementioned frameworks and provide guidelines to choose one that suits the task at hand. This study also provides insights into the features and APIs supported in Java to achieve parallelism.

With the development and progress of automobile industry, the automobile electronic control system has put forward higher and higher requirements to the controller. From the realization of the controller to vehicle test, all need hardware in loop test, and ensure the real test results of core is to run in real-time processor on the real-time operating system, at the same time with a single core processor in the operation of the real-time system bottlenecks, this paper USES the multi-core processor platform to build real-time problems of real-time system research. The Linux system is studied in this paper after the defects in real time, this paper proposes a by adding preemption patch solution to realize real- time Linux system, at the same time, using the advantages of multi-core processors, the CPU resources of real-time and non- real-time tasks are divided, and the number of interrupts on the CPU where the real-time task is located is reduced. Finally, a specific RTOS development case based on the PREEMPT_RT patch is given, and on this basis, the effectiveness of the proposed scheme in the real-time performance of the system is verified.