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A single-chip Bluetooth v2.1-compliant CMOS radio SoC that supports Enhanced Data Rates is implemented in standard 0.13 μm CMOS technology. All functions of a Bluetooth radio are integrated in the SoC, including RF, analog and digital parts. The RF transceiver features a polar transmitter, a two-point modulated fractional-N synthesizer, a 500 kHz IF receiver with first order low-pass analog filtering, and a Δ∑ ADC with 74 dB dynamic range. The total SoC die area is 9.2 mm2 with only 3.0 mm2 for analog and RF circuits. The basic-rate radio power consumption is below 30 mA for both receive and transmit. [ABSTRACT FROM AUTHOR]

A single-chip CMOS PHS cellphone, integrated in a 0.18-µm CMOS technology, implements all handset functions including radio, voice, audio, MODEM, TDMA controller, CPU, and digital interfaces. Both the receiver and transmitter are based on a direct conversion architecture. The RF transceiver achieves -106 dBm receive sensitivity and +4 dBm EVM-compliant transmit power. The local oscillator, based on a sigma-delta fractional-N synthesizer, has a phase noise of -118 dBc/Hz at 600 kHz offset and settling time of 15 µs. The current consumption for the receiver, transmitter and synthesizer are 32 mA, 29 mA, and 25 mA, respectively, from a 3.0 V supply. [ABSTRACT FROM AUTHOR]

A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25-μm CMOS technology and occupies a total silicon area of 23 mm2. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase noise is -105 dBc/Hz at a 10-kHz offset and the spurs are below -64 dBc when measured at the 5-GHz transmitter output. [ABSTRACT FROM AUTHOR]