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Here, the authors demonstrate the application of machine learning to optimize the device fabrication process for wafer-scale 2D semiconductors, and eventually fabricate digital, analog, and optoelectrical circuits.

In standard computing architectures, memory and logic circuits are separated, a feature that slows matrix operations vital to deep learning algorithms. Here, the authors present an alternate in-memory architecture and demonstrate a feasible approach for analog matrix multiplication.

This paper presents the analysis and design of a 35-GHz high-gain phase shifter with 360° continuous phase shifting. To enhance the phase shift range, a hybrid π-network realized by combining the electrical tuning through capacitors and magnetic tuning through transformers is developed. The phase shift modules are inserted between the vertically stacking transistors to achieve the embedded phase shifting with the minimum loss. Furthermore, the Gm stages offer additional signal gain to suppress attenuation in the passive phase shifter. The capacitive neutralization technique is utilized to further increase the gain and enhance stability. This prototype, fabricated in a 28-nm CMOS process, demonstrates a 360° continuous phase shift with a maximum gain of 25.6 dB and a minimum noise figure of 4.1 dB. It consumes 26-mW power with a supply voltage of 0.9 V and 1.25 mm × 0.75 mm chip area.

This paper presents a 12-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for low-power wireless and imaging systems. A split-capacitor digital-to-analog converter (CDAC) structure is adopted for reducing the core area and improving the sampling speed. The linearity of the CDAC is calibrated by programming the least-significant-bits (LSBs) dummy capacitor. The unit capacitor in the CDAC array is customized for higher symmetry and reducing their mismatch. Our SAR ADC is based on asynchronous logic, and its timing is controlled by a delaying block in the critical path. The prototype is fabricated in a 65-nm CMOS process with a 1.2 V supply and occupies an active area of 0.029 mm2. With a 100-MS/s sampling rate, the measured ENOB scores 10.17 bits for 1.5 MHz input with a figure-of-merit (FoM) of 6.94 fJ/conversion-step. It can achieve 8.83 bits for Nyquist input signal.

This paper presents a high-gain D-band power amplifier (PA) fabricated with 28-nm CMOS technology for a sub-terahertz frequency modulated continuous wave imaging system. It adopts two-channel power combining using artificial transmission lines to absorb the parasitic capacitance of the ground-signal-ground pad. The layout of the transistors and neutralization capacitors are optimized to improve the maximum stable gain, stability, and robustness. Asymmetrically magnetically coupled resonators are used in inter-stage and input matching networks to extend the operating bandwidth. The PA achieves a peak power gain of 21.9 dB and maximum output power of 11.8 dBm with 10.7% of power-added efficiency. Also, this PA can achieve higher than 10 dBm output power over the frequency range of 120–150 GHz.

Ferroelectric devices with dielectric layers to modulate channel conductance have limited endurance and miniaturization. Here, the authors demonstrate a 2D ferroelectric channel transistor that integrates memory and computation capabilities, that will support the development of memory and computing fusion systems.

In this article, accurate physical and SPICE model of wafer-level monolayer molybdenum disulfide (MoS2) device are developed to guide the devices and circuits design, which is the foundation of high-performance analog chip design. Moreover, the proposed model considers the non-ideality of thin films and the influence of Schottky contact with higher accuracy. The mean percentage error (MPE) of the physical model simulation and measurement results is 4.49%. Based on the SPICE model implemented in this article, the amplifier circuit and current amplifying circuits are implemented to verify the manufacturing process and accuracy of the device models, which shows the MoS2 is potential material to realize industrial applications. The MPE of the SPICE model simulation and measurement results is within 7.00% which can be utilized for our analog circuit design.

This article presents an accurate quadrature phase-locked loop (PLL) with quadrature phase mismatch calibration for 32 GS/s analog-to-digital converter (ADC). Due to the mismatches of clock distribution in layout and variations of the active devices, the quadrature phase of the sampling clock is significantly deteriorated. To solve the problem, a novel quadrature divider with phase calibration is induced in PLL loop. Moreover, a theoretical model of the quadrature divider is proposed to predict the performance and potential ability for phase calibration. Based on the theoretical and model analysis, the proposed PLL can realize accurate quadrature phase for high-speed real-time sampling system. The output frequency of PLL is 8 GHz with quadrature phases for 32 GS/s sampling rate. The proposed clock can realize 8-bit signal to noise ratio requirement with 16 GHz bandwidth. The proposed PLL was fabricated in 65-nm CMOS process with 28 mW dc power consumption under 1.2 V supply voltage. Testing results show that the phase noise of the clock is -127 dBc/Hz @10 MHz-offset frequency when the sampling speed is 27.4 GS/s. With proposed methods, the range of the phase error calibration is around ±20°.