Search

To consider STT-MRAM as an SRAM replacement, the reliability of the MTJ devices has to be demonstrated. A comprehensive study of degradation of STT-MRAM magnetic tunnel junction barrier under stress is presented in this paper. It is found that the breakdown mechanism of such devices follows a consistent path of soft breakdown (SBD) followed by hard breakdown (HBD). We discuss the strategy to improve the write margin by reducing the resistance area product (RA) of the tunnel barrier. Finally, we link our single device reliability studies to similar endurance studies performed on our fully functional chips.

Last-Level-Cache applications at OX technology nodes require devices switching reliably in less than 10ns at currents smaller than 50uA, while preserving data retention up to 85°C. In this paper, we show that both low Gilbert damping and low magnetic moment are the primary factors for efficient writing at nanosecond time scales. We report comprehensive device-level measurements of damping using both conventional free layer designs and an optimized free layer that combines low damping and low moment and meets LLC requirements.

We present for the first time STT-MRAM devices with ultra low operating voltage and power compatible with next generation 0x node logic voltages. By engineering the tunnel barrier and improving the efficiency of the devices we report a record low writing voltage of 0.17V for a 1ppm error rate, which has been achieved for a 20ns write operation using a writing current of only 35uA. We further demonstrate error rates below 10-9 at voltage and current at 0.25V and 50uA using 10ns writing pulses on the same 30nm devices with extended 400C thermal budget while preserving functionality confirm the almost unlimited endurance of these data and retention at 85°C. Finally, TDDB studies confirm the almost unlimited endurance of these devices at the operating voltage.

Scaling STT-MRAM cells beyond 1X technology nodes will require MTJ devices smaller than 30 nm. For such small sizes, process-induced damage becomes a primary factor of device performance. A robust method of assessing magnetic properties of sub-30 nm devices is thus needed. Here we report measurements of the anisotropy field H K down to 20 nm devices using ST-FMR. We show that H K increases for decreasing sizes. The interfacial anisotropy field exceeds 23 kOe, leading to Hk larger than 13 kOe for 20 nm devices under optimal process conditions. Using insight from micromagnetic simulations, we develop a simple model to fit Hk size dependence, allowing us to quantify magnetic edge damage for various process conditions.

Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) is emerging as a leading candidate for a variety of embedded memory applications ranging from embedded NVM to working memory and last level cache. In this paper, we review recent breakthroughs that have brought perpendicular STT-MRAM to the cusp of mass production.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a leading candidate for embedded memory applications, with promises of low power, high performance, and non-volatility.

Spin Transfer Torque Magnetic Random Access Memories (STT-MRAM) are based on Magnetic Tunnel Junctions (MTJs) made out of two ferromagnetic electrodes separated by a MgO tunnel barrier.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is the leading technology for next generation non-volatile embedded memories [1].

We present recent advances in writing speed of pSTT_MRAM which demonstrate its potential as a candidate for replacement of LCC cache for advanced technology nodes as well as applications where non-volatility may be needed. In this paper we explore the feasibility of sub-ns switching of devices and their characterization using comprehensive time resolved electrical measurement of the reversal mechanism. We show that the switching mechanism can be described as a simple nucleation followed by propagation model that can be characterized statistically. We further demonstrate that after optimization of the Magnetic Tunnel Junction (MTJ) stack, single devices can be switched reliably using write pulse length down to 750ps while preserving functionality and data retention @ 125°C. Results of the integration at array level on an 8MB test vehicle are also presented allowing full array writing using 3ns pulses without ECC and demonstrated data retention of 10 years (1ppm) at 125°C.

Current understanding of thermal stability of perpendicular STT-MRAM based on device-level data suggests that the thermal stability factor A is almost independent of device diameter above ∼30nm. Here we report that contrary to this conventional wisdom, chip-level data retention exhibits substantial size dependence for diameters between 55 and 100 nm. We show that the method widely used to measure A is inaccurate for devices larger than ∼30 nm, leading to significant underestimation of the size dependence. We derive an improved model, allowing us to reconcile the size dependence of A measured at device and chip level.

STT-MRAM technology has been attracting renewed attention since the embedability of a working STT-MRAM design has been demonstrated [1]. In this paper we expand on the versatility of STT-MRAM by demonstrating the conversion of a standard STT-MRAM cell to a One Time Programmable (OTP) anti-fuse cell. Both designs are integrated at the Mbit level on a single chip using the same magnetic stack, processing and CMOS cell design. A single BEOL mask change can convert an STT-MRAM device to an OTP design by simply reducing its size. The increased resistance yields larger voltage drop across the device, due to the voltage divider effect in the 1T-1MTJ cell and is sufficient to trigger reliable dielectric breakdown of the oxide tunnel barrier, effectively shorting the device. In this paper we demonstrate the seamless integration of an OTP based on STT-MRAM and 100% programming and reading yield at the Mbit level.

The recent rise of mobile applications such as Internet of Things (IoT), wearable electronics, and context aware computing has renewed the search for a universal embedded memory technology [1]. Such a technology should combine fast read/write, low voltage operation, low power consumption, non-volatility, infinite endurance, with CMOS process compatibility. Magnetic Random Access Memory based on Spin Transfer Torque phenomena (STT-MRAM) has been recognized as a promising candidate. The technology is innately non-volatile, and it has been shown that STT-MRAM based on perpendicularly magnetized Magnetic Tunnel Junctions (MTJs) can be written at high speed with low power. However, two major challenges remain. The first is to design multilayered MTJs that can withstand temperatures used in CMOS backend processing without any degradation of their magnetic properties. The second challenge is that fast read/write must be achieved not only at the single device level, but on entire memory arrays which requires controlling defects and distributions of magnetic properties.

We present major breakthroughs in MTJ design for STT-MRAM applications allowing reliable write for pulse lengths down to 1.5ns, data retention up to 125°C for 10 years and full compatibility with BEOL process up to 400°C for 1 hour. We have successfully integrated the novel structure onto an 8Mbit test chip. We demonstrate writing of every single cell in the array using sub-5ns pulses over a wide temperature range without using any error correction. We also show that sensing times of 4ns are sufficient to read every data cell. The inherent scalability of the design makes it a prime candidate for universal embedded non-volatile memories down to the 28nm node and beyond.

Magnetic random access memories based on the spin transfer torque phenomenon (STT-MRAMs) have become one of the leading candidates for next generation memory applications. Among the many attractive features of this technology are its potential for high speed and endurance, read signal margin, low power consumption, scalability, and non-volatility. In this paper, we discuss our recent results on perpendicular STT-MRAM stack designs that show STT efficiency higher than 5 kBT/μA, energy barriers higher than 100 kBT at room temperature for sub-40 nm diameter devices, and tunnel magnetoresistance higher than 150%. We use both single device data and results from 8 Mb array to demonstrate data retention sufficient for automotive applications. Moreover, we also demonstrate for the first time thermal stability up to 400 °C exceeding the requirement of Si CMOS back-end processing, thus opening the realm of non-volatile embedded memory to STT-MRAM technology.