138 results on '"Shamiryan, D."'
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2. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
3. Integrated diffusion–recombination model for describing the logarithmic time dependence of plasma damage in porous low- k materials
4. In-line control of Si loss after post ion implantation strip
5. Effect of top power on a low- k film during oxygen strip in a TCP etch chamber
6. Dry etching process for bulk finFET manufacturing
7. Oxygen chemiluminescence in He plasma as a method for plasma damage evaluation
8. Charging of submicron structures during silicon dioxide etching in one- and two-frequency gas discharges
9. Plasma etching: From micro- to nanoelectronics
10. Diffusion of solvents in thin porous films
11. Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density
12. SiCP Selective Epitaxial Growth in Recessed Source/Drain Regions yielding to Drive Current Enhancement in n-channel MOSFET
13. Wafer Backside Cleaning Strategies for High-k/Metal Gate Processing
14. Implementation of high- k and metal gate materials for the 45 nm node and beyond: gate patterning development
15. Low-k dielectric materials
16. Simulations of diffusion barrier deposition on porous low- k films
17. Pinhole density measurements of barriers deposited on low- k films
18. Optimization of low-k UV Curing: Effect of Wavelength on Critical Properties of the Dielectrics
19. Comparative study of PECVD SiOCH low-k films obtained at different deposition conditions
20. Investigation of barrier and slurry effects on the galvanic corrosion of copper
21. Russian MEMS production of European quality
22. Interprocess control of critical dimensions in production of MEMS
23. Automated defect detection system in MEMS manufacturing
24. Automated approach to the analysis of geometric parameters of MEMS elements.
25. Improving mechanical robustness of ultralow-k SiOCH plasma enhanced chemical vapor deposition glasses by controlled porogen decomposition prior to UV-hardening.
26. Growth and characterization of atomic layer deposited WC[sub 0.7]N[sub 0.3] on polymer films.
27. Low dielectric constant materials for microelectronics.
28. Factors affecting an efficient sealing of porous low-k dielectrics by physical vapor deposition Ta(N) thin films.
29. Automated approach to the analysis of geometric parameters of MEMS elements
30. Smoothening of 193 Immersion Resist by 172 nm VUV Exposure
31. Revealing the Porous Structure of Low-k Materials Through Solvent Diffusion
32. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
33. 8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS
34. Effect of energetic ions on plasma damage of porous SiCOH low-k materials
35. Charging and the secondary electron–electron emission on a trench surface: broadening and shift of ion energy spectrum at plasma trench etching
36. Metrology for Implanted Si Substrate Loss Studies
37. Effects of He Plasma Pretreatment on Low-k Damage during Cu Surface Cleaning with NH[sub 3] Plasma
38. The metal hard-mask approach for contact patterning
39. Experimental and Theoretical Studies of Radical Production in RF CCP Discharge at 81-MHz Frequency in $\hbox{Ar/CF}_{4}$ and $\hbox{Ar/CHF}_{3}$ Mixtures
40. SELECTIVE REMOVAL OF HIGH-KGATE DIELECTRICS
41. High Performance 70-nm Germanium pMOSFETs With Boron LDD Implants
42. Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability
43. Effect of quartz window temperature on plasma composition during STI etch
44. Using Ellipsometry for Assessment of TiN Surface Roughness after Plasma Etch
45. Spacer defined FinFET: Active area patterning of sub-20nm fins with high density
46. Metal Inserted Poly-Si (MIPS) and FUSI dual metal (TaN and NiSi) CMOS integration
47. Influence of crystallographic orientation on dry etch properties of TiN
48. Influence of TaN Gate Electrode Microstructure on Its Dry Etch Properties
49. Implementation of high-k and metal gate materials for the 45nm node and beyond: gate patterning development
50. Integration challenges for multi-gate devices
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