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12. SiCP Selective Epitaxial Growth in Recessed Source/Drain Regions yielding to Drive Current Enhancement in n-channel MOSFET

13. Wafer Backside Cleaning Strategies for High-k/Metal Gate Processing

25. Improving mechanical robustness of ultralow-k SiOCH plasma enhanced chemical vapor deposition glasses by controlled porogen decomposition prior to UV-hardening.

26. Growth and characterization of atomic layer deposited WC[sub 0.7]N[sub 0.3] on polymer films.

27. Low dielectric constant materials for microelectronics.

28. Factors affecting an efficient sealing of porous low-k dielectrics by physical vapor deposition Ta(N) thin films.

30. Smoothening of 193 Immersion Resist by 172 nm VUV Exposure

33. 8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

36. Metrology for Implanted Si Substrate Loss Studies

42. Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability

46. Metal Inserted Poly-Si (MIPS) and FUSI dual metal (TaN and NiSi) CMOS integration

49. Implementation of high-k and metal gate materials for the 45nm node and beyond: gate patterning development

50. Integration challenges for multi-gate devices

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