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This article describes a 4 $\times $ 112 Gb/s digital receiver targeting long-reach (LR) channels. An SNR optimized approach is presented, which relaxes the ADC resolution requirement and the number of FFE taps without sacrificing BER. The discrete-time front end overcomes gain–BW limitations to provide 10+ dB gain at 28 GHz. A 56-GS/s ADC then converts the signal to 6-b digital consuming only 195 mW. The following DFE-FFE-based digital equalizer is capable of compensating 36-dB loss achieving a BER of 2e−5. Furthermore, TDC and ISI filter-based low-latency timing recovery meet jitter tolerance specs over a wide range of data rates from 10 to 112 Gb/s, including 28-Gb/s NRZ. The overall receiver consumes 338 mW with 3.18-pJ/bit energy efficiency.

This article presents a multiprotocol DSP-DAC-based SerDes architecture. The lookup table (LUT)-based DSP provides flexible number of taps for equalization, and soft switching driver allows 1.2-Vpp transmit swing to achieve higher SNR. The architecture employs cascaded phase-locked loop (PLL)-based flexible clocking to support a wide range of data rates from 10 to 112 Gb/s. The $LC$ PLL generates 10.25–14.5 GHz but distributes a divided version of the clock between 2.25 and 3.625 GHz with less than 140-fs integrated jitter. The local ring PLL multiplies the clock to 28 GHz but keeps the jitter less than 180 fs thanks to wide loop bandwidth. The transmitter is implemented in 7-nm FinFET consuming 175 mW with 1.56-pJ/bit efficiency.

This paper describes a 4 × 112 Gb/s digital receiver targeting Long Reach (LR) channels. The discrete time front-end overcomes gain-BW limitations to provide 10+dB gain at 28GHz. A 56GS/s ADC then converts the signal to 6-b digital consuming only 195mW. The following DFE-FFE based digital equalizer is capable of compensating 36 dB loss achieving BER of 2e-5. Furthermore, TDC and ISI filter based low latency timing recovery meets jitter tolerance specs over a wide range of data rates (25Gb/s NRZ to 106.25Gb/s PAM-4). The overall receiver consumes 338mW with 3.18pJ/bit energy efficiency

Internet of things (IoT) devices such as self-driven cars and home appliances are creating massive amounts of data traffic. Obviously, such demand trickles down to every electrical interface in a network. Therefore, next-generation data centers need to evolve accordingly to accommodate the bandwidth demand of a rapidly changing world of technology. Since the channel loss is not improving at the same rate, most of the standards are adopting multilevel signaling to make more efficient use of the frequency spectrum. A 4×112Gb/s PAM-4 transmitter presented in this work is leading this trend to keep electrical signaling viable and relevant for future data centers. It introduces three techniques to enable flexibility over different protocols and achieves 1.56pJ/b (175mW at 112Gb/s data rate including clocking) energy efficiency. First, improving signal-to-noise ratio is key to achieve lower BER in multilevel signaling. This work introduces a ‘soft-switching’ H-bridge output driver to enable a 1.2V peak-to-peak differential output swing without exposing devices beyond breakdown voltage. Second, ‘flex clocking’ is achieved by combining a central LC-PLL with a per-lane sub-sampling ring PLL. This combination enables flexible clock generation to seamlessly support data rates between 10Gb/s NRZ and 112Gb/s PAM-4. This clocking architecture enables low-frequency clock distribution for power saving and is easily scalable to more lanes. Third, a DSP-DAC-based transmitter is used to support an arbitrary number of equalization taps and different modulation schemes [1]. A segmented lookup-table-based (LUP-based) implementation further reduces the DSP power.

When implementing 112Gbps LR SerDesPHY, what are the top for next generation designs?

This paper presents the design and Silicon verification of a 2.488---11.2 Gbps multi-standard SerDes transceiver in a 40 nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. A system modeling approach is described, which is used for optimizing the architectural trade-offs. The transceiver makes use of a low-jitter LC phase locked loop to enable high-reliability system design. The design has 420 fs RJrms and consumes 30.1 mW/Gbps at 11.2 Gbps.

The paper presents the design of a 2.488 – 11.2 Gbps SerDes transceiver in a 40nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. The transceiver makes use of a low-jitter LC PLL to enable high-reliability system design. A system modeling approach is also described, which is used for optimizing the architectural trade-offs. The design has 520fs RJ rms and consumes 30.1 mW/Gbps at 11.2 Gbps.

A 2.3 to 5GHz LC PLL is implemented in 65nm standard CMOS for 0.6 to 10Gb/s SerDes applications. The LC VCO is measured to have 67% coarse tuning range and worst-case hold range of 9.6%. The rms random jitter (RJ rms ) on the TX output with a clock pattern is measured to be 460fs at 5GHz and 548fs at 3.125GHz. The total power dissipated from the 1.8V, 1.0V supplies is 29mW at 5GHz.