10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture

This article presents a multiprotocol DSP-DAC-based SerDes architecture. The lookup table (LUT)-based DSP provides flexible number of taps for equalization, and soft switching driver allows 1.2-Vpp transmit swing to achieve higher SNR. The architecture employs cascaded phase-locked loop (PLL)-based flexible clocking to support a wide range of data rates from 10 to 112 Gb/s. The $LC$ PLL generates 10.25–14.5 GHz but distributes a divided version of the clock between 2.25 and 3.625 GHz with less than 140-fs integrated jitter. The local ring PLL multiplies the clock to 28 GHz but keeps the jitter less than 180 fs thanks to wide loop bandwidth. The transmitter is implemented in 7-nm FinFET consuming 175 mW with 1.56-pJ/bit efficiency.