Search

NoC-based designs provide a scalable and flexible communication solution for the rising number of processing cores on a single chip. To master the complexity of the software design in such a NoC-based multi-core architecture, advanced incremental integration testing solutions are required. This work presents a virtual platform based software testing and debugging approach for a synchronous application model on a NoC-based designs provide a scalable and flexible communication solution for the rising number of processing cores on a single chip. To master the complexity of the software design in such a NoC-based multi-core architecture, advanced incremental integration testing solutions are required. This work presents a virtual platform based software testing and debugging approach for a synchronous application model on a 2x2 NoC-based MPSoC. We propose a development approach and a test environment that exploits the time approximation within Imperas OVP instruction accurate simulator and a functional model of the Nostrum NoC, for both software instructions and hardware clock cycles at larger time stamps called Quantum that does not sacrifice functional correctness. The functional testing environment runs the target software without running it on the real hardware platform. With the help of Nostrum NoC we can support a synchronous system execution that is reasonably fast and precise with respect to a global synchronization signal, called HeartBeat. As work in progress, this work also discusses several possible timing refinement and their possible implication on the simulation semantics and performance and how it is tackled in the future work. NoC-based MPSoC. We propose a development approach and a test environment that exploits the time approximation within Imperas OVP instruction accurate simulator and a functional model of the Nostrum NoC, for both software instructions and hardware clock cycles at larger time stamps called Quantum that does not sacrifice functional, QC 20170912

With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER1., QC 20170626