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A Ka-band CMOS cascode power amplifier (PA) linearized with a cold-FET-based interstage matching network is presented, which is designed in a 65-nm CMOS process. Since it is difficult to make a cascode PA matched to the optimum output and input impedances at high frequencies, a matching network has to be introduced at the node between the common-source (CS) and common-gate (CG) stages. The cold-FET-based matching network improves the linearity and the input and output impedance matchings, which is analyzed and optimized with its simple model. It makes the PA have gain expansion and phase lag with the power, which allows the PA to have less amplitude-to-amplitude (AM–AM) and amplitude-to-phase (AM–PM) distortions. In addition, it improves the return losses of the PA by making the impedances for power matching and conjugate matching located closely. The implemented PA achieves the peak power-added efficiency (PAE) of 38.2% and the saturated output power ( $P_{\mathrm {sat}}$ ) of 17.1 dBm at 31 GHz while occupying the chip area of 0.16 mm2. It is also shown that the OP1 dB is improved by 1.7 dB, and the AM–PM distortion is reduced to only 1.1° due to the linearization technique. It is tested with 64-quadrature amplitude modulation (QAM) signals, which has a 400-MHz channel bandwidth (BW) and a 9.7-dB peak-to-average power ratio (PAPR). It achieves average output powers of 9.6/7.7 dBm with error vector magnitudes (EVMs) of −25/−30 dB for 64-QAM OFDM signals, efficiencies of 17.7%/12%, and the adjacent channel leakage ratio (ACLR) of −28.2/−32.8 dBc, respectively.

This paper presents a highly efficient 5G NR RF transmitter (TX) system consisting of a SAW-less RF transmitter IC, an RF power amplifier module (PAM) and a supply modulator IC (SM-IC). The RF TX with a 12-bit current-steering digital-to-analog converter (DAC) generates +7 dBm of output power to drive the PAM for high power user equipment (HPUE) in the 5G NR n77 band. The SM-IC generates a maximum output power of 10W at a 5-V peak envelope output voltage and provides an envelope tracking supply voltage of a 100-MHz NR signal to the n77 PAM. The PAM employing a differential topology generates a saturation output power of 32.5 dBm including the loss of the SOI switch and output filter. The designed PAM in ET mode achieves an ACLR of -37 dBc at a 27-dBm output power and saves 950 mW in comparison to APT mode.

This paper presents 2G/3G/4G/5G transmitter that has a compact die area and supports multi bands in 5G new radio (NR). The transmitter with inter-digitated switchable transformer is designed to support n77/n78/n79 of 5G FR1 bands (3.2GHz to 5GHz) and B46/B47 of V2X bands (5.125GHz to 5.925GHz). The transformer provides optimum transformed load impedance at the drive amplifier output with 3-stacked switches. The on-chip transformer with inter-digitated structure results in a high coupling factor to minimize the insertion loss. An interstage matching network between a mixer and a drive amplifier induces a channel flatness characteristic. The designed transmitter is fabricated using a 14nm FinFET CMOS process. It achieves a peak average output power of 7dBm and 2% under measured root mean square (rms) EVM in the case of DFT-s-OFDM 256QAM Full-RB signal, while satisfying the 3GPP specification. It also satisfies 1dB under channel flatness and the adjacent channel leakage ratio (ACLR) −43.2dBc in case of n77/n78, and −42.7dBc in case of n79, while consuming 295mW and 300mW dc power at 7.5dBm and 6.7dBm output power, respectively. The transmitter with inter-digitated switchable transformer has a size of 0.18mm2.

To be competitive in a mobile market, current consumption and bill-of-material (BOM) cost have to be minimized. Current reduction techniques have been actively investigated as they become a key factor to increase battery lifetime. To reduce BOM cost, external low-noise amplifier (eLNA) usage and discrete passive components have to be minimized with simple interfaces, which influences the number of PCB Iayers and stacks. This work is oriented to provide a low-power and low-cost cellular RF transceiver that supports 2G, 3G, and 4G as well as new-radio (NR) frequency range1 (FR1) with a dual-mode Global Navigation Satellite System (GNSS) implemented in a 14nm FinFET CMOS technology. A fully digital interface is implemented to transfer data between an RFIC and a modem for enhanced routability as demonstrated in Fig. 6.1.1.

This letter presents a 28-GHz CMOS linear power amplifier (PA) for 5G beamforming front-end that has dual power modes. The proposed PA consists of parallelly connected cascode cells, which are used to linearize the PA in the high-power mode (HPM). Power modes are implemented by splitting the cascode cells again. To have a low-power mode (LPM), half of the cells are turned off while halving the supply voltage simultaneously. This concurrent change makes it possible to keep the phase of the PA unchanged over two power modes while the dc power consumption is reduced by about half in the LPM. In addition, the good linearity is maintained in the LPM. The PA has gains of 18/14 dB, saturated output powers of 18.5/12.2 dBm, P1dBs of 16.5/10.2 dBm, and peak PAEs of 27.3%/17.8% with a 28-GHz continuous wave (CW) signal. The maximum linear output powers that satisfy EVM $\times100$ -MHz 64-QAM OFDM signal.

This paper presents a highly linear cascode power amplifier (PA) for 5-GHz 802.11ac (wireless local area network) WLAN applications, which is fabricated with a 0.13- $\mu \text{m}$ standard RF CMOS process. A parallel-cascoded configuration is proposed to cancel out third and fifth intermodulation distortions and third harmonic distortion (HD) due to drain–source current nonlinearity. This also reduces distortions due to drain–source and gate-source nonlinear capacitances at both common source (CS) and common gate (CG) stages. The configuration allows the amplifier linear characteristics to be robust against gate node voltage variations of CG transistors compared to previous multigated transistor linearization methods, because the CG transistors always remain in the saturation region and the nonlinearities of capacitances associated with CG transistors cancel each other under a wide range of output powers. In addition, an active feedback linearizer is applied to improve AM–AM and the power-added efficiency (PAE) at high output powers. At 5.15 GHz, the proposed PA is tested with a 256-quadrature amplitude modulation WLAN 802.11ac signal source without digital predistortions. The output powers satisfying the stringent linearity, a −35-dB error vector magnitude, are 17.8, 17.3, and 15.6 dBm with 11.5%, 10.4%, and 7.5% PAEs at 20, 40, and 80 MHz, respectively.

A dual-mode radio frequency CMOS power amplifier (PA) for Internet of Things application is presented, which is integrated with the other circuits in a 55-nm bulk CMOS process. The low-power mode is achieved by reducing the number of turn-on power transistors, which are also used for linearization. The PA has a gain control scheme that functions by controlling the transconductance ( ${g_{m}}$ ) of the driver stage. A simple body network is introduced to common gate power transistors to improve the linearity of the PA. It is measured with 802.11n 64-quadrature-amplitude-modulation (MCS7) signal and shows a maximum average power of 16 dBm with a supply current of 222 mA under an error-vector-magnitude of −27 dB, which is packaged in a QFN 5 ${\times } \,\, 5$ mm.

A dynamic feedback linearizer for an RF CMOS power amplifier (PA) is presented, which consists of a negative feedback network and a dynamic feedback control circuit to inject a reshaped envelope signal to the network. The linearizer compensates for the gain compression of the RF CMOS PA in high-power region by reducing the feedback dynamically, and it also reduces the amplitude-to-phase modulation (AM-PM) distortions. The PA including the linearizer was fabricated using a 0.18- $\mu \text{m}$ RF CMOS process, which has an output transmission-line transformer on a printed circuit board. It delivers an output power of 28.1 dBm at 1.7 GHz with power added efficiency of 40.9%, and adjacent channel leakage ratio (ACLR $_{\mathrm {E-UTRA}}$ ) of under −30 dBc for a 10-MHz 16-QAM long-term evolution signal without digital predistortions.

A common-gate (CG) transistor in a cascode power amplifier has a large input capacitance variation in the saturation region with respect to the source voltage. This causes large nonlinearity in a CMOS PA that utilizes a cascode configuration. Here, we propose a method to reduce the capacitance variation by introducing a parallel auxiliary transistor that works in both the saturation and depletion regions by applying a bias voltage that is slightly different from the main one. This provides the proposed CMOS PA a gain of 27.8 dB and an output power of 16.7 dBm with a PAE of 14.7% for an 802.11n modulated signal with an EVM of −25 dB. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:125–128, 2017

In the past decades, many reliability analyses have been developed and applied to engineering fields considering uncertainties of input and output random variables as normal distributions. However, when input uncertainty is taken into the system as extreme events such as weather, temperature, environmental conditions etc., output distribution cannot be described by normal distribution. On the other hand, one of distributions to analyze reliability of a system under extreme events is generalized Pareto distribution. Generalized Pareto distribution has been developed and applied for modelling extreme events. However, conventional methods estimate only the shape and scale parameters by assuming that the location parameter is chosen by experiences focused only on the tail distribution. However, since the tail distribution affected by the body distribution and vice versa, both the body and tail distributions should be considered when the parameters of distribution are estimated. In this study, therefore, a new parameter estimation method is proposed to determine shape, scale and location parameters simultaneously by combining likelihood functions of body and tail distributions using Akaike information criterion and generalized Pareto distribution, respectively. Finally, the parameters of body and tail distributions are estimated by maximum likelihood estimation. The proposed method is verified by using mathematical examples with and without inclusion of extreme events. Results show that the proposed method can estimate parameters and distributions for body and tail distributions as well as the more accurate reliability of system under extreme events.

공학분야의 신뢰성 해석은 점점 더 높은 신뢰도 영역에 대한 확률밀도함수의 예측을 요구한다. 따라서 높은 신뢰도를 정확하게 해석하기 위해 분포의 꼬리부분을 정확하게 표현해야 한다. 최근 들어 꼬리부분에 대한 표본만을 이용해 꼬리 모형을 생성하여 신뢰도를 추정할 수 있는 방법인 일반화파레토 분포에 대한 연구가 활발히 진행되고 있다. 하지만 기존의 연구에서는 부정확한 임계점 추정으로 꼬리 부분에서 신뢰도의 정확도가 떨어진다. 따라서 본 논문에서는 아카이케 정보척도를 이용하여 임계점을 정확하고 강건하게 추정하고 이를 통해 꼬리 모형의 정확도를 향상시키는 아카이케 정보척도 기반 일반화파레토 분포 기법을 제안한다. 또한 제안하는 기법을 이용한 신뢰성 해석을 수행하여 정확도가 향상된 신뢰성 해석 결과를 도출하였다.

A 2-stage 1.7-GHz Doherty power amplifier (PA) with an adaptive bias (ADB) circuit was designed for small-cell base station applications. An uneven power cell size ratio was used to provide a large back-off efficiency for high peak-to-average power ratio (PAPR) signals. To simplify the power divider and inter-stage matching network, a lumped Lange-type quadrature coupler was used. The leakage signal from the isolated port of the coupler was used as an input signal for the ADB circuit of the peaking amplifier. The PA was implemented in a 0.25-μm GaN on a SiC MMIC process. For a 1.7-GHz continuous wave, the PA has a 45.8% power added efficiency (PAE) at the output power of 38.6-dBm and a 31.2% PAE at 7-dB back-off power. For an LTE downlink signal, adjacent channel leakage ratio (ACLR) of −25.9-dBc was obtained at the average output power of 31.4-dBm without a digital pre-distortion (DPD).

In this paper, the guidance law for formation flight and collision avoidance of multiple Unmanned Aerial Vehicle (UAV)s is proposed. To construct the physically comprehensible guidance law for formation flight, the virtual structure approach is used. To develop a guidance law for collision avoidance considering both other UAVs and unknown static obstacles, a geometric approach using information such as a relative position vector is utilized. Through the Lyapunov theorem, the stability of the proposed guidance law is proved. To combine guidance commands, the concept of the elastic weighting factor inspired by the elastic behavior of shape memory polymer, which tends to regain its original shape after deformation, is introduced. By using the concept of elastic weighting factor, multiple UAVs are able to cope actively with the situation of a collision between both UAVs and static obstacles during the formation flight. To verify the performance of the proposed method, numerical simulations are performed.

A fully integrated dual-mode CMOS power amplifier (PA) with nonlinear MOS capacitance compensation is presented using 0.18-μm RF CMOS process. The proposed technique is used to implement dual mode structure as well as reduces AM-PM distortion. Dual-mode output matching network using transmission line transformer (TLT) is implemented for efficient dual mode operation. With a supply voltage 3.5V, the PA has the power gain of 26.2 and 14.2dB in low power mode (LPM) and high power mode (HPM), respectively. The quiescent current is only 28mA at LPM. The maximum linear output power satisfying 3GPP WCDMA modulated signal is 28/16.3dBm with a PAE 33.8/10.2% in the HPM/LPM.

TM plane wave scattering from a slit in a thick conducting screen is examined. A Fourier transform technique is employed to express the scattered field in the spectral domain and the boundary conditions are enforced to obtain simultaneous equations for the transmitted field inside the thick conducting screen. The simultaneous equations are solved to represent the transmitted and scattered fields in series forms. Approximate series solutions for scattering and transmission are obtained in closed-forms which are valid for high-frequency scattering regime. >

TE plane-wave scattering from a slit in a thick conducting screen is reexamined. The boundary conditions are enforced to obtain simultaneous equations for the transmitted field inside the thick conducting screen. The simultaneous equations are solved to represent the transmitted and scattered fields in series forms. An approximate series solution for transmission is obtained in closed form which is valid for the high-frequency scattering regime. >