Search

Some wafers in a lot may become spoiled after they are processed at a workstation; such a lot is called a small lot. In a low yield and high price scenario, scrapping small lots may increase revenue and profit; yet, this notion has seldom been examined. This study presents a model for formulating the decision-making problem of scrapping small lots. A genetic algorithm is used to solve the problem when the solution space is large. An exhaustive search method is used when the solution space is small. Some numerical examples are used to evaluate the outcome of scrapping small lots. The profit obtained by the proposed scrapping method may be up to 23% higher than that obtained without scrapping. Index Terms--Bottleneck, high price, low yield, product introduction, small lots.

This paper presents the development of an efficient approach to the deadlock-free scheduling of photolithography equipment in semiconductor fabrication. Trends toward high automation and flexibility in the photolithography equipment accelerate the necessity of an intelligent scheduler that can guarantee reliability and improve the productivity of the photolithography equipment. Therefore, the scheduler of the photolithography equipment should be able to handle failures of process modules and deadlock while optimizing its performance measures such as throughput and utilization. The contingency of failure of process modules makes the tasks of optimizing the performance measures and managing deadlock more difficult because failure of process modules can change states unexpectedly and deadlock situations can vary dynamically according to failure of process modules. This paper proposes a deadlock-free scheduling approach that can perform scheduling and deadlock management in an efficient way for photolithography equipment, in spite of failures of process modules. First, this paper presents a novel framework in which the authors decompose the deadlock management problem into subproblems and then integrate them with scheduling algorithms. In other words, they identify deadlock-prone and deadlock-safe process modules in the context of the deadlock management and then focus on the deadlock-prone process modules to guarantee deadlock-freeness when applying scheduling algorithms to all of the process modules. To realize the proposed framework, a resource request matrix is introduced to represent operational states. The resource request matrix provides an explicit representation of the deadlock situations, which is useful in identifying deadlock-prone process modules and applying deadlock management algorithms. The authors also present algorithms of polynomial complexity to identify deadlock-prone process modules and algorithms to manage deadlock, which take failures of process modules into consideration. Index Terms--Deadlock avoidance, deadlock-free scheduling, photolithography, semiconductor fabrication.

Cluster tools provide a flexible, reconfigurable, and efficient environment for several manufacturing processes (e.g., semiconductor manufacturing). A new timing constraint (distinct from a simple deadline), referred to as residency constraint, puts a timing limit on the time that a wafer can stay in a processing module in a clustertool. The authors demonstrate that a solution that does not address residency constraints can be found easily. However, when residency constraints are added to the model, the problem becomes complex and a scheduling technique may spend a long time searching for a good solution. Also, in some cases, one may need to decrease throughput to satisfy residency constraints. The authors introduce a new technique to address cluster tool scheduling in the presence of residency constraints. The proposed technique uses a buffer resource for temporarily holding wafers to release other resources such as the robot arm. This resource is usually available in the tool for maintenance reasons. A tradeoff is discussed in using the buffer resource and a scheduling algorithm is presented that will use this resource when it can help to increase throughput under residency constraints. The experiments show that in many cases that are common in semiconductor manufacturing, use of their proposed technique can improve throughput. Index Terms--Buffer, cluster tools, deadline, residency constraints, scheduling.

Cluster tools, each of which consists of several single-wafer processing chambers and a wafer handling robot, have been increasingly used for diverse wafer fabrication processes. Processes such as some low pressure chemical vapor deposition processes require strict timing control. Unless a wafer processed at a chamber for such a process leaves the chamber within a specified time limit, the wafer is subject to quality problems due to residual gases and heat. We address the scheduling problem for such time-constrained dual-armed cluster tools that have diverse wafer flow patterns. We propose a systematic method of determining the schedulable process time range for which there exists a feasible schedule that satisfies the time constraints. We explain how to select the desirable process times within the schedulable process time range. We present a method of determining the tool operation schedule. For more flexible scheduling under the time constraints, we propose a modification of the conventional swap operation in order to allow wafer delay on a robot arm during a swap operation. We compare the performance of the new swap strategy with that of the conventional swap strategy. Index Terms--Cluster tool, scheduling, swap, time constraint.

This paper describes a model-free method for estimating some yield metrics that are used to track integrated circuit fabrication processes. Our method uses binary probe test data at the wafer level to estimate the size, shape and location of large-area defects or clusters of defective chips. Unlike previous methods in the yield modeling literature, our approach makes extensive use of the location of failing chips to directly identify clusters. An important byproduct of this analysis is a decomposition of wafer yield that attributes defective chips to either large- or small-area defects. Simulation studies show that our procedure is superior to the time-honored windowing technique for achieving a similar breakdown. In addition, by directly estimating defect clusters, we can provide engineers with a greater understanding of the manufacturing process. It has been our experience that routine identification of the spatial signatures of clustered defects and associated root-cause analysis is a cost-effective approach to yield and process improvement.

The results of a full model accounting for the thermal behavior of a commercially available rapid thermal processing furnace are given. In particular, emphasis has been placed on achieving a fiat temperature profile over the wafer. System parameters allowing RTP equipment to be improved are reviewed.

This paper describes the development of real-time control technology for the improvement of manufacturing characteristics of reactive ion etchers. A general control strategy is presented. The principal ideas are to sense key plasma parameters, develop a dynamic input - output model for the subsystem connecting the equipment inputs to the key plasma variables, and design and implement a multivariable control system to control these variables. Experimental results show that this approach to closed-loop control leads to a much more stable etch rate in the presence of a variety of disturbances as compared to current industrial practice.

A new RTP system concept is proposed and demonstrated. The system uses a vertical cylindrical quartz tube, while the wafer is placed horizontally. Linear halogen lamps are arranged in a hexagonal shape, and the hexagonal-shaped lamp groups are stacked vertically. Each lamp group is controlled independently, allowing a temperature difference within [+ or -] 1.5 [degrees] C to be achieved over a 6-in wafer in steady state. Oxidation under optimal power condition results in a 1.37% standard deviation for an average oxide thickness of 110.4 [Angstrom]. The temperature nonuniformity during the transient has been greatly improved by using dynamic control. The convection loss in the system has been evaluated and its radial dependence is found to be smoother in this chamber than in a conventional rectangular chamber. The ray-tracing simulation in three-dimensional space did result in a better comprehension of the optically complex system. The system efficiency has turned out to be lower than in the case of a conventional rectangular chamber. A large portion of the radiation energy is absorbed by the reflectors. There is a strong side heating to the vertical edge of the wafer. Both are due to multiple horizontal reflections of the rays on the reflectors without hitting the wafer. The temperature profiles calculated from the ray-tracing results show an excellent agreement with experiments and confirm the accuracy of the ray-tracing simulation. The main advantages of this new system concept are its excellent temperature uniformity and the good accessibility of the wafer for technological treatments and in situ measurements.

This paper develops an approach for using a wavelength-dependent emissivity model of a semiconductor wafer in calculating heat transfer in a rapid thermal processing (RTP) station. The wafer emissivity is modeled by a generalized polynomial in wavelength where the coefficients may be functions of temperature. A comparison of experimental data with simulated results for a silicon wafer is provided.