Search

A large single-grain Pb(Zr,Ti)O3 (PZT) film was integrated into low-temperature polycrystalline silicon (poly-Si) thin-film transistors fabricated on a glass substrate. The poly-Si was crystallized by NiSi2 seed-induced lateral crystallization (SILC). The SILC poly-Si had a superior electrical performance to other crystallization methods as a result of its high crystalline volume fraction (91.2%). PZT with a perovskite phase is generally obtained at 800 °C, which is not suitable for glass substrates. Therefore we developed a low-temperature perovskite PZT using an artificially controlled seeding process. An artificially controlled nucleation seed was first formed by rapid thermal annealing at 650 °C in 1 s pulses and a single seed was then grown in a tube furnace at 550 °C for 2 h. The resulting device had a large memory window (3.5 V) and a highly reliable memory operation. This approach could potentially be applied to the next generation of non-volatile memory devices as well as in integrated system-on-glass displays.

The source and drain regions were formed successfully by dopant induced crystallization method for top gate poly silicon thin film transistors. It was found that the resistance of source and drain varies with respect to dopant concentration and the grain boundary influence on resistance at different doses was intensively studied in this work. In the present study, boron was doped by ion mass doping (IMD) and PECVD and the resistance of 230 Ω was the doping condition of 2 keV 1 min and 17 keV 10 min in ion mass doping method. Thin film transistor by DIC exhibited a field effect mobility of 56 cm 2 /V s, leakage current of 4.1 × 10 −11 A, slope of 0.84 V/dec, I on of 2.7 × 10 −4 A, V th of −6.5 V at V d = 10 V In crystallization of in situ boron doped a-Si, 80 Ω in resistance was obtained at 1000 A. N type poly Si of 1000 A has 270 Ω in in-situ doping method. In-situ doped a-Si deposited by PECVD was further doped by using IMD. And the resistance was lowered by 10–20 Ω. Bottom gate thin film transistors fabricated by metal induced lateral crystallization (MILC) exhibits a field effect mobility of 26 cm 2 /V s, leakage current of 1.34 × 10 −10 A, slope of 0.7 V/dec, I on of 1.02 × 10 −4 A, V th of 4.5 V at V d = 10 V.

The electrical performance of low-temperature polycrystalline silicon thin-film transistors (TFTs) is greatly affected by structures such as channel geometry, lightly doped drain, film thickness, etc. In this paper, the split channel polycrystalline silicon TFTs are fabricated through the silicide seed induced lateral crystallization method by dividing channel width with fixed numerical channel size. The number of channels splitting from 1 to 10 significantly improves driving characteristics such as driving current, field-effect mobility, subthreshold slope, and threshold voltage. It is found that the two main causes of improvements are the enlargement of effective channel width and a decrease in series resistance due to the crystal filtering effect on narrowly split channels, which lead to trap-state density reduction during lateral crystal growth. The causes of enlarged effective channel width and the decreased series resistance by the crystal filtering effect are demonstrated through capacitance-voltage and trap-state density extraction.

The electrical performance of low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) fabricated by silicide-induced crystallization (SIC) is greatly affected by metal contamination such as Ni silicide. In this paper, the effect of Ni silicide density on the SIC poly-Si TFTs is investigated by in-situ Ni silicidation at room temperature, 100°C, 200°C, and 300°C, respectively. It was observed that grain size of fully crystallized polycrystalline silicon (poly-Si) decreased with the increase of in-situ silicidation temperature. This is due to an increase in the density of nucleation sites for crystallization. As a result, grain boundaries and interface trap-state densities were significantly increased and electrical properties such as subthreshold slope, on-state current and field effect mobility were drastically degraded.

It is known that MILC polysilicon thin-film transistors (TFTs) show excellent electrical properties except for a relatively high leakage current. In this work, a lightly doped drain structure (LDD) was prepared in an n-type MILC poly silicon TFT and the effect of the LDD length on the leakage current has been systematically investigated. It turned out that the LDD is mainly responsible for the low leakage current, and no more than 0.5 µm of the lightly doped region is necessary to lower the leakage current to less than 3 × 10−11A at V D = 10 V. No appreciable effect on the leakage current can be found by an LDS (lightly doped source) but an LDS length of more than 1.5 µm caused a reduction of the on-current to below 10−5 A, whereas the on-current is typically more than 10−4 A in a conventional MILC TFT.

A novel and simple crystallization method for high performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) using Ni silicide seed-induced lateral crystallization (SILC) was proposed in this study, and it includes no additional deposition and/or etching processes that are not found in the fabrication of conventional metal-induced lateral crystallization (MILC) TFTs. The poly-Si thin films crystallized by SILC were characterized by x-ray photoelectron spectroscopy (XPS), x-ray diffraction (XRD), field emission scanning electron microscopy (FESEM), and Micro-Raman spectroscopy. The electrical properties were obtained from ID-VG transfer curves and the interface trap density was determined by Levinson plot analysis. The results show that SILC poly-Si films have lower Ni contamination, better crystallinity, and higher crystalline fraction than MILC poly-Si films. The p-channel SILC poly-Si TFTs exhibited a mobility of 66 cm2/V·s, a minimum leakage current of 3.4 × 10−11 A at VD = −5 V, a subthreshold slope of 0.85 V/dec, and a maximum on/off ratio of 5.0 × 106, all of which resulted in a high-performance device which surpassed conventional MILC poly-Si TFTs.

The effects of phosphorus doping and boron doping on the metal-induced lateral crystallization (MILC) rate have been studied. In the case of phosphorus doping, the MILC rate is very sensitive to the sequence of nickel deposition and doping. Phosphorous doping before the nickel deposition reduced the MILC rate much more than the vice versa. When the nickel removal was between the nickel deposition and phosphorus doping, the doping effect on the MILC rate turned out to be in the between of the two cases which are phosphorus doping before nickel deposition and nickel deposition before phosphorus doping. Boron doping results in the crystallization of a-Si at a lower temperature (550°C) compared with that of the solid phase crystallization (SPC). The sheet resistance of boron doped Si remained high because the boron dopants were segregated at the grain boundaries during crystallization of a-Si.

A Lightly Doped Drain (LDD) structure is known to be very effective in preventing hot electrons in modern NMOS transistors. In this work, the lightly doped region was formed in poly TFT by using a separate LDD mask aligned to a gate mask. The misalignment can be calculated to be about 1.5 microm, and depending on the location of the V(d) application between the source and drain, an LDD or Lightly Doped Source (LDS) structure can be realized on the same TFT. In this way, we can make a perfect comparison between these two structures. It turned out that the LDD is mainly responsible for the low leakage current, and no more than 0.5 microm of the lightly doped region is necessary to lower the leakage current down to less than 5 x 10(-11) amps at V(d) = 10 volts. Typically, the on-current of MILC TFT is more than 10(-4) amps, but 2.5 microm LDS decreases it to below 10(-7) amps.

Metal-induced lateral crystallization (MILC) technology has been regarded as the only alternative for low temperature polycrystalline silicon (poly-Si) since it became apparent that laser technology still had intrinsic problems for industrial use. The only problem with MILC poly-Si thin-film transistors (TFTs) is a relatively large leakage current, which has been reported to be due to Ni silicides trapped at the grain boundaries of the poly-Si thin film on the way to lateral crystallization. In this work, the trapped Ni silicides have been removed by catalytic phase transformation. This process has ameliorated not only the problem of leakage current but it has also improved other electrical properties, such as field effect mobility and subthreshold slope by gettering of the Ni silicide.

In this study, a low temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) was fabricated by self-aligned silicide seed induced lateral crystallization (SA-SILC). In comparison with a self-aligned metal induced lateral crystallization (SA-MILC) TFT, the SA-SILC TFT showed better electrical properties. In particular, the leakage current was decreased by SA-SILC at high drain voltages. It was found that the Ni rich phase between the channel and drain junction region acted as trapping sites to generate leakage current by thermionic field emission. After applying the SA-SILC process, the p-channel polycrystalline silicon (poly-Si) TFT exhibited a mobility of 67 cm 2/V·s, a minimum leakage current of 2.6 × 10−11 A at V D = −5 V, a subthreshold slope of 0.8 V/dec, and a maximum on/off ratio of 7.0 × 10 6, together resulting in a high-performance device that surpasses the conventional SA-MILC poly-Si TFT.

Iridium oxide (IrO2), one of the versatile oxide materials among the transition metal oxides, has been used for many applications due to its attractive electrical, optical properties and biocompatibility [1-3]. To the best of our knowledge, however, there is no report on investigation of IrO2 as electrode material for an aqueous supercapacitor. In this work, we prepared the IrO2 thin film by rf magnetron sputtering method on stainless steel (SS) substrate at different temperatures. The deposited films were firstly used as electrode materials for supercapacitor in 1M LiNO3 aqueous electrolyte with activated carbon and saturated calomel electrode (SCE) for counter and reference electrodes. Structural and electrochemical performances were studied by X-ray diffraction (XRD), cyclic voltammetry (CV) and electrochemical impedance spectroscopy (EIS). Figure1 shows the XRD patterns of IrO2 films sputtered at different substrate temperatures. As can be seen from Fig.1 (a), no well-defined IrO2 diffraction peaks but SS substrate (2θ = 44, 51 and 75) are detected in room-temperature-sputtered IrO2 film. While increases the substrate temperature to 300°C [Fig.1 (d)], typical diffraction peaks of crystalline IrO2 are observed (JCPDS No. 88-0288). CV curves of the IrO2 film sputtered at different temperatures in 1M LiNO3 electrolyte are compared in Figure 2. The CV measurements were carried out at a scan rate of 5 mV·s. Generally, all the CV curves are roughly rectangular in shape and exhibit near mirrorimage current response on voltage reversal, indicating a capacitive behavior of the present samples in potential range of 0-1.0V. Moreover, the specific capacitance (F·g ) was calculated using the voltammetric charge integrated from the cyclic voltammogram, and the highest capacitance of 293, 274, 264 and 226 F·g was obtained for the IrO2 film sputtered at room temperature, 100°C, 200°C and 300C, respectively. Figure 3 presents the Nyquist plots of the IrO2 film electrode sputtered at room temperature before and after 1000 cycles under the scan rate of 100 mV·s. The plot consists of a high-frequency impedance attributed to the processes occurring at the electrode/electrolyte interface, a semicircle corresponding to a parallel combination of charge-transfer resistance (Rct) and double-layer capacitance (Cdl), and finally a linear region at low-frequency range. As shown, the diameter of the semicircle increases after 1000 cycles, indicating the resistance of the capacitor increases in certain degree. However, the nearly straight line in low-frequency range inclines at angle of approximately 90o to the real axis, indicating that the IrO2 film electrode trends to become a purely capacitive behavior in LiNO3 solution (vertical lines characteristic of a limiting diffusion process).

On the basis of new triode-type field emission arrays (FEAs) and the so-called swap-gate driving method for a 3-in.-diagonal flat lamp using carbon nanofiber (CNF) emitters in our previous research, the characteristics of our flat lamp were investigated according to the swap-gate driving conditions. It was found that the longer the gate-pulse width (duration time), the higher the anode current. Additionally, in the case of a fixed gate-pulse width, the anode current increased as the gate frequency increased. One particularly interesting experimental result was that the emission current (Ia) increased with the shortening of the pulse width of the gate when the sum of the gate-pulse widths per second was equal.

In this study, three different crystalline states of silicon were prepared to be doped with phosphorous by IMD, amorphous, poly crystalline and single crystalline silicon. The dose was controlled by IMD duration time and heat treatment for electrical activation was done in RTA and Furnace. In case of RTA, annealing temperature was controlled by the duration time of power application. In case of a single crystal substrate, the resistance was measured to be 20-50 omega/square depending on the dose and annealing temperature. In case of poly crystal, we could observe segregation of the dopant at grain boundaries, which caused increase of the resistance with increase of annealing temperature. In case of amorphous silicon thin film, this phenomenon could not be observed due to lack of the grain boundaries and the minimum resistance of this work was about 300 omega/square, which was about the same to that in a poly silicon thin film.

Bottom-gated polycrystalline-silicon (poly-Si) thin-film transistors (TFT's) with a planarized copper (Cu) gate for large-area displays have been fabricated and characterized. The 500 nm depth of trenchs are filled up with 400 nm, 500 nm, 600 nm thickness of Cu using the damascene process of VLSI technology, poly-Si TFT's with 100 nm thick gate insulator are fabricated on the Cu gate. As the Cu gate's thickness becomes thinner, the anomalous leakage current of poly-Si TFT's is reduced significantly both before and after electrical stressing. The results simulated by 3D electric field simulator demonstrate that the structure of planarized gate in bottom-gate TFT can effectively reduce the electric field causing the field emission between the gate and the drain.

Polycrystalline silicon thin-film transistors (TFTs) fabricated by seed-induced crystallization (SIC) have large leakage currents due to defects that consist of Ni impurities. Here, we describe a novel method of gettering to remove Ni impurities using a Si gettering layer that is separated from the active layer by a chemical SiO2 etch stop interlayer formed by dipping into H2SO4. The leakage current, the on/off ratio, and a channel breakdown voltage were greatly improved. These results were explained by lowered trap-state density in the channel.

A planarized thick copper (Cu) gate low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) is fabricated for ultra-large active-matrix organic light-emitting diode (AMOLED) displays. We introduce a damascene and chemical mechanical polishing process to embed a planarized Cu gate of 500 nm thickness into a trench and Si3N4/SiO2 multilayer gate insulator, to prevent the Cu gate from diffusing into the silicon (Si) layer at 550°C, and metal-induced lateral crystallization (MILC) technology to crystallize the amorphous Si layer. A poly-Si TFT with planarized thick Cu gate exhibits a field effect mobility of 5 cm2/Vs and a threshold voltage of −9 V, and a subthreshold swing (S) of 1.4 V/dec.

Ni was deposited on amorphous silicon (a-Si) thin film by Metal Organic Chemical Vapor Deposition (MOCVD), using MABON as a precursor. The amount of Ni deposited on a-Si was controlled by the deposition time. It has been found that nickel does not form a continuous film on top of a-Si thin film. Crystallization was carried out at 570 °C in hydrogen ambient. Partial crystallization occurs first and then the phase transformation spreads throughout the surface. 4 h is required for full crystallization, where the rate for Metal-Induced Lateral Crystallization (MILC) at this temperature is typically 20 um/hr. The electrical properties of such prepared poly Thin Film Transistors (TFTs) are quite acceptable for an active matrix. Raman spectrum analysis indicates that MABON Low Temperature Poly Silicon (LTPS) is suitable for a high efficiency solar cell because of its high crystalline quality.

In this work, non-volatile memory thin-film transistor (NVM-TFT) was fabricated by nickel silicide-induced laterally crystallized (SILC) polycrystalline silicon (poly-Si) as the active layer. The nickel seed silicide-induced crystallized (SIC) poly-Si was used as storage layer which is embedded in the gate insulator. The novel unit pixel of active matrix organic light-emitting diode (AMOLED) using NVM-TFT is proposed and investigated the electrical and optical performance. The threshold voltage shift showed 17.2 V and the high reliability of retention characteristic was demonstrated until 10 years. The retention time can modulate the recharge refresh time of the unit pixel of AMOLED up to 5000 sec.

It has been known that LDD is essential to reduce the leakage current in poly TFTs, which has been regarded as one of the most important issues in poly TFT characteristics. However, according to the conventional process, an extra mask is needed solely for the LDD formation, which is not only complicated but also difficult to maintain the reproducibility. In this work, a simple method has been introduced for formation of LDD structure in poly Si TFTs, Tilted Back Exposure (TBE) technique. It has been found that asymmetry patterns can be realized with TBE process and submicron accuracy can be easily achieved by adjusting the angle between the substrate and light source. The LDD TFTs using TBE process shows almost the same electrical properties as the LDD TFTs using an additional separate LDD Mask.

In this study, we studied the effect of the electrical stress on the on-current of metal-induced laterally crystallized poly-Si TFTs. It was found that the electrical performance of polycrystalline silicon thin-film transistors (TFTs) is greatly affected by the electrical stress. Under the electrical stress condition, the drain current increases due to hot-electron trap at the drain junction. The computer simulation revealed the fact that the improvement mechanism can be reproduced by effective channel length shortening. It turns out that analysis of the capacitance and output characteristics supports this model.

In this work, the authors fabricated 1-transistor ferroelectric random access memory based on polycrystalline-silicon (poly-Si) on a glass substrate. A novel technique was used to form a large single-grained Pb(Zr,Ti)O3 (PZT) layer as the gate insulator. Generally, the crystallization temperature of PZT is 800 °C, which is beyond the limits for a glass substrate; however, here the authors developed a selectively nucleated lateral crystallization technique to minimize the crystallization temperature and grow 40 μm grains of PZT. Pt layer using rapid thermal annealing at 650 °C for a short time, and grew a single seed by tube-furnace at 550 °C for 2 h. Our device demonstrated excellent electrical properties with long retention time, which only decreased by 9% after 104 s, and good fatigue characteristics, which only decreased by 4% after 104 cycles.

A ferroelectric-flash (F-flash) memory cells having a metal-ferroelectric-nitride-oxynitride-silicon structure are demonstrated, and the ferroelectric materials were perovskite-dominated Pb(Zr,Ti)O3 (PZT) crystallized by Pt gate electrode. The PZT thin-film as a blocking layer improves electrical and memorial performance where programming and erasing mechanism are different from the metal-ferroelectric-insulator-semiconductor device or the conventional silicon-oxide-nitride-oxide-silicon device. F-flash cells exhibit not only the excellent electrical transistor performance, having 442.7 cm2 V−1 s−1 of field-effect mobility, 190 mV dec−1 of substhreshold slope, and 8 × 105 on/off drain current ratio, but also a high reliable memory characteristics, having a large memory window (6.5 V), low-operating voltage (0 to −5 V), faster P/E switching speed (50/500 μs), long retention time (>10 years), and excellent fatigue P/E cycle (>105) due to the boosting effect, amplification effect, and energy band distortion of nitride from the large polarization. All these characteristics correspond to the best performances among conventional flash cells reported so far.

The electrical performance of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) fabricated by metal-induced lateral crystallization (MILC) is greatly affected by metal catalyst contaminations, such as Ni and Ni silicide trapped in the channel, since they concentrate in front of laterally grown crystallites. In the present work, the effect of the MILC/MILC boundary (MMB) on MILC polycrystalline silicon (poly-Si) TFTs is investigated by the comparison of MILC poly-Si TFTs with MMB at the center of the channel, and equivalent TFTs with MMB at a position ejected from the channel. The MMB location was controlled by the Ni catalyst position. Both a low off-state leakage current and a free from short channel effect (kink effect) were observed in high electric-field conditions. Furthermore, the field-effect mobility and drain current noise were drastically improved by ejecting the MILC boundary in the source direction.

In this study, the effect of dopant concentration in lightly doped drain (LDD) region on the electrical properties of N-type gate insulator doping mask (GIDM) LDD metal-induced lateral crystallization (MILC) polycrystalline silicon thin film transistors (TFTs) was investigated. In order to find the optimum value for the dopant concentration in LDD region, we analyzed the electrical properties of LDD MILC TFTs with different dopant concentration in LDD region. The dopant concentrations in LDD regions of the TFTs were measured using secondary ion mass spectroscopy (SIMS). From the electrical properties and the SIMS data of the TFTs, it has been found that for the N-type GIDM LDD MILC TFTs with the LDD length of about 1.5 µm, the dopant concentration in LDD region should be in the range between 1019 and 3×1020/cm3 to ensure the suppression of off-state leakage current without device performance degradation.

not Available.

Transparent nanofloating gate memory devices based on top-gate zinc oxide thin-film transistors were developed. The proposed devices contained a facile and dry-synthesized palladium nanocluster array as a charge-trapping layer. The good programmable memory characteristics were exhibited due to the thin tunneling oxide, caused by the top-gate structure. The good endurance, data retention capability, and environmental stability demonstrated by the proposed device made it suitable for nonvolatile memory applications. As the whole processes were carried at room temperature, this letter has a potential use in fabricating high-performance and high-reliability nonvolatile memory devices on flexible substrates.

not Available.

not Available.

Low leakage current structures, such as the lightly doped drain and the field-induced drain, employing a subgate were investigated. In order to achieve the self-alignment of a submicrometer level lightly doped drain, the transmittance change in the phase transformation of silicon by a metal-induced lateral crystallization method was employed. Due to an extended thermionic emission domain, more than one order of magnitude improvements in the leakage current at the practical off-state were obtained. Controlling the subgate dielectric resulted in a better on/off current ratio. Simulated results demonstrated that the proposed field-induced drain structure effectively suppressed the electric fields near the drain.