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DC microgrids are increasingly becoming the backbone of renewable energy integration. Their ability to efficiently manage intermittent sources like solar and wind power is transforming the energy landscape. However, a critical challenge remains in the form of DC arc faults, which can significantly compromise the reliability and safety of these systems. Parallel arc faults represent a particularly challenging scenario due to their unique electrical behavior. Unlike series arc faults, which cause a decrease in system current, parallel arcs can lead to a significant increase in current due to the low resistance path they create. This research delves into the electrical behavior of DC systems during parallel arc faults. By analyzing the source current signals in different domains, the authors aim to identify specific characteristic features of the source current that can serve as reliable indicators combined with artificial learning models for arc fault diagnosis. The findings of this research can have significant implications for the improvement of advanced arc failure recognition systems. This research represents a valuable step towards safe and reliable DC systems by addressing the challenge of parallel arc fault detection.

Active front-end (AFE) rectifiers are a well-known solution in industries due to bidirectional power flow, sinusoidal line currents, and dc-link voltage adjustment. Typically, in three-phase AFE rectifiers, the power is distributed evenly among the phase legs, aiming for a natural balancing of aging over time. However, uneven thermal stress caused by different switching frequencies or design of cooling system and prior replacement of failure power switches might create an unavoidable aging mismatch between phase legs of AFE rectifier. In this article, a per-phase model predictive direct power control with offset voltage injection is proposed. The proposed method notably reduces power loss of the weakest phase to improve the lifespan of circuit and reduce maintenance costs. The power components of the AFE rectifier are regulated utilizing predicted rectifier voltages, which are changed by adding proper zero-sequence signal to decrease losses in the most aging leg. The minimum power loss of the weakest leg involves avoiding changing the corresponding switching state for two-thirds of the source period. Simulations and experiments are conducted to validate the developed technique.

Nowadays, active rectifiers are increasingly used, particularly in grid-connected applications. The high efficiency and reliability of active rectifiers become crucial for increasing the system performance. Due to the lack of model predictive control methods considering the different aging levels among phase legs of rectifiers, this paper thus introduces a direct power control-based model predictive control for independent loss reduction in each phase of the active rectifier. Different from conventional techniques, the target of proposed model predictive direct power control scheme is lowering switching loss in the leg having highest aging level of active rectifier, resulting in increasing its corresponding lifetime and lifetime of entire rectifier. As opposed to the model predictive control method based on incorporating additional terms regarding switching loss in the cost function, a switching state preselection strategy is proposed in this study to determine clamping region and corresponding preselected switching state for the leg having highest aging level of active rectifier. The use of the proposed method lowers thermal stress in the leg having highest aging level and increases lifetime of active rectifier. Simulation and experimental results for the proposed technique are presented and compared with conventional model predictive direct power control method to validate the accuracy and feasibility of the proposed method.

In recent years, the pulse-width-modulation (PWM) converter has been found to have extensive applications in renewable energy, industrial fields, and others. The high efficiency requirement is crucial to operating a PWM rectifier in various applications, in addition to the fundamental control objectives of sinusoidal grid currents and the correct DC bus voltage. Additionally, in practical application, another issue arises when the grid voltage frequently experiences distortion, leading to a distorted grid current and a significant rise in total harmonic distortion (THD). To resolve these problems, a model predictive virtual flux-based direct power control (MPVFDPC) with improved power loss performance is proposed based on an integrated switching state predetermination strategy. The proposed MPVFDPC for PWM rectifier inherits the merits of both virtual flux control and direct power control, which have fast dynamic performance and the grid current THD is considerably decreased under distorted grid voltage states. The proposed technique aims to minimize switching loss under ideal and distorted grid voltage states by exploiting the discontinuous modulation concept by using a switching state predetermination strategy. The MPVFDPC with switching state predetermination strategy is proven by employing it in experiments as well as simulations in comparison with previous models: predictive direct power control (Conv. MPDPC) and conventional MPVFDPC (Conv. MPVFDPC). The acquired waveforms and quantitative data are employed to prove the effectiveness of the developed algorithm.

The expansion of DC electrical distribution systems necessitates advancements in detecting and mitigating DC arc events, a significant contributor to fire accidents in low-voltage DC distribution systems. Detecting DC arc faults poses considerable challenges, making them a major safety concern in DC power lines. Conventional approaches mainly rely on arc current, which can vary during normal operation, potentially leading to false alarms. Moreover, these methods often require manual adjustment of detection thresholds for different systems, introducing the risk of malfunction. This study proposes an advanced arc fault recognition procedure that extracts and utilizes various key features for the DC arc detection. This work investigated new various features, which are the square average, the average, the median, the rms, the peak-to-peak, and the variance values, to find out which one can be the most effective features to detect the DC arc failure. The results of this detection process show good evidence for the effectiveness and reliability of the proposed malfunction detecting plan.

The intricate spectrum of arc faults elicited by diverse load types introduces a complex and formidable challenge in residential series arc fault detection. Series DC arc faults pose a significant concern as they can potentially instigate fire incidents and exert adverse ramifications on power systems if left undetected. Nonetheless, their detection within practical power systems remains challenging, predominantly attributed to the meager arc current magnitude, the absence of a discernible zero-crossing interval, and the manifestation of multifarious aberrant behaviors contingent upon the diverse array of power loads and controllers. Importantly, the conventional safeguards, notably encompassing protection fuses, may exhibit inefficacy in promptly activating during the occurrence of series DC arc faults. The ramifications of undiscerned arc faults are profound, with the potential for engendering erroneous operational modes within power systems, thereby amplifying the risk of material and human casualties. In light of these exigencies, the development of an efficacious detection mechanism targeting series arc faults within DC systems becomes a paramount imperative. This research proposed a preprocessing signal to eliminate the switching noises, which could degrade the performance of artificial machine learning algorithms. The diagnosis results valid the effectiveness of the proposed diagnosis scheme for all ranges of switching frequencies.

This paper presents an efficient independent phase switching loss reduction technique for 2-level 3-phase voltage source inverters. A modified carrier-based pulse-width modulation algorithm, named per-phase discontinuous pulse-width modulation, is used to generate various non-switching intervals for the phase leg having the worst aging state by injecting a proper zero-sequence voltage to reference voltages. The non-switching intervals result in keeping a specific phase leg from switching to decrease the switching frequency and corresponding loss. The careful determination of variable clamping intervals aims to achieve a desirable decrease in the per-phase switching frequency of 2-level 3-phase voltage source inverters while ensuring that the output performance is not much degraded. The decrease in switching frequency and corresponding switching loss exerts a positive impact on the thermal stress of power semiconductor devices, resulting in improving the reliability of voltage source inverters. To evaluate the performance of the proposed method, the conventional carrier-based space vector modulation, 3-phase generalized discontinuous pulse-width modulation, and a discontinuous pulse-width modulation using hybrid offset voltage are implemented along with the proposed method. The accuracy and efficiency of the proposed method are validated using both simulation and experimental data.

In a power electronic system, a control objective is to improve efficiency and reduce thermal stress in converters in order to increase the lifetime of devices. To achieve this, minimizing losses is crucial. The objective of this research paper is to present a method aimed at decreasing individually switching losses in voltage source inverters (VSI). The proposed technique uses per-phase model predictive control (MPC) with preselected switching states to target specific phase legs and achieves corresponding loss reduction. With the information of predicted reference voltages, the developed preselection algorithm determines the non-switching area of the most aged leg and corresponding switching states among available voltage vectors of VSI. The switching loss reduction in the most aged leg is achieved by selecting the optimal switching state among preselected voltage vectors based on a pre-established optimal criterion. The thermal stress of the most aged leg will be reduced, and therefore its lifetime will be increased, resulting in improving the reliability and lifetime of the entire VSI. Finally, the effectiveness of the proposed per-phase MPC method with preselection of switching state is verified by both simulation and experimental results.

One of the key goals of power electronics is to reduce losses in three-phase converters in order to increase efficiency and reduce thermal stress, which can lengthen the lifetime of devices. However, the aforementioned studies do not account for the fact that the phase legs of the converter can experience various aging conditions, which reduces the expected lifetime of converter. This paper proposes a minimum loss per-phase method based on predictive control for voltage source inverter, which aims at particularly reducing loss of specific phase leg to increase the lifetime of the entire converter. The output currents will be controlled using predicted reference voltages and predictive zero-sequence voltage injection in the proposed technique. The particular phase leg, which is the most aged leg, will be clamped to the positive and negative dc-link to generate a non-switching region. This will result in the reduction of switching frequency and switching loss of the most aged phase leg in the voltage source inverter, which prolongs the lifetime of the particular phase leg and entire converter. The results of simulation and experimentation are used to confirm the validity of the proposed method and effectiveness in increasing lifetime of converter, where the switching loss of the most aged leg is reduced by up to 85%, and corresponding lifetime increases by about four times compared to the conventional model predictive control method.

DC microgrids are vital for integrating renewable energy sources into the grid, but they face the threat of DC arc faults, which can lead to malfunctions and fire hazards. Therefore, ensuring the secure and efficient operation of DC systems necessitates a comprehensive understanding of the characteristics of DC arc faults and the implementation of a reliable arc fault detection technique. Existing arc-fault detection methods often rely on time–frequency domain features and machine learning algorithms. In this study, we propose an advanced detection technique that utilizes a novel approach based on feature differences between moving intervals and advanced learning techniques (ALTs). The proposed method employs a unique approach by utilizing a time signal derived from power supply-side signals as a reference input. To operationalize the proposed method, a meticulous feature extraction process is employed on each dataset. Notably, the difference between features within distinct moving intervals is calculated, forming a set of differentials that encapsulate critical information about the evolving arc-fault conditions. These differentials are then channeled as inputs for advanced learning techniques, enhancing the model’s ability to discern intricate patterns indicative of DC arc faults. The results demonstrate the effectiveness and consistency of our approach across various scenarios, validating its potential to improve fault detection in DC systems.

DC series arc faults pose a significant threat to the reliability of DC systems, particularly in DC generation units where aging components and high voltage levels contribute to their occurrence. Recognizing the severity of this issue, this study aimed to enhance DC arc fault detection by proposing an advanced recognition procedure. The methodology involves a sophisticated combination of current filtering using the Three-Sigma Rule in the time domain and the removal of switching noise in the frequency domain. To further enhance the diagnostic capabilities, the proposed method utilizes time and frequency signals generated from power supply-side signals as a reference input. The time–frequency features extracted from the filtered signals are then combined with artificial learning models. This fusion of advanced signal processing and machine learning techniques aims to capitalize on the strengths of both domains, providing a more comprehensive and effective means of detecting arc faults. The results of this detection process validate the effectiveness and consistency of the proposed DC arc failure identification schematic. This research contributes to the advancement of fault detection methodologies in DC systems, particularly by addressing the challenges associated with distinguishing arc-related distortions, ultimately enhancing the safety and dependability of DC electrical systems.

Three-phase AC/DC pulse-width-modulated (PWM) converters have been widely employed in various renewable energy systems and industrial applications, which require a high-efficiency power converter operation. This article proposes a technique to reduce switching loss in AC/DC converters by integrating a voltage vector preselection strategy to model predictive virtual flux control. The voltage vector preselection strategy preselects available voltage vectors corresponding to switching states that lead to minimum switching loss in the phase leg, which conducts the highest current. By using preselected voltage vectors, clamping intervals are generated at every fundamental period to maintain the present switching states of the power switches, resulting in the reduction in switching loss. Additionally, by using virtual flux control, the proposed approach can effectively be used under both ideal and distorted source voltage conditions. The proposed method is compared with the conventional model predictive current control and the conventional model predictive virtual flux control. Both a simulation and experiment are performed to validate the correctness and effectiveness of the proposed method, which has been found to decrease the switching loss of an AC/DC converter by up to 15% compared to conventional control schemes at a negligible increase in the input current total harmonic distortion and DC output voltage ripple.

Unequal thermal stress among the phase legs of a multiphase converter leads to a reduction in the useful lifespan and reliability of that converter in general. Increasing the converter’s lifespan by relieving the stressed phase leg, which suffers excessive thermal stress due to aging, is crucial. This paper evaluates two control concepts, including two per-phase model predictive control methods for extending the lifespan of a voltage source inverter. These two per-phase techniques alter the switching pattern to reduce the losses of the most aged phase leg. Hence, the loss and the corresponding thermal stress of the leg that has aged the most are reduced. In such a way, the lifespan and reliability of the converter are prolonged. Two per-phase model predictive control techniques are executed in both simulation and experiment environments, where the corresponding results are provided to evaluate the behavior of these control strategies, considering several operational aspects both in steady state and transient operation. In addition to static load conditions, two per-phase techniques are verified for the correct operation under dynamic load (induction motor) conditions.

Discontinuous pulse-width-modulation (DPWM) methods have been extensively used in the industrial area to reduce overall losses, which decreases the corresponding thermal stress on the power switches of converters. However, local thermal overload can arise due to different aging conditions of semiconductor devices or failure in the cooling system. This leads to reduced reliability of the converter system due to the low expected lifespan of the most aged switches or phase legs. In this paper, the modified DPWM strategies for independent control of per-phase switching loss are introduced to deal with this matter. The proposed per-phase DPWM techniques are generated by modifying the conventional three-phase DPWM methods for reducing the switching loss in a specific leg, whereas the output performance is not degraded. This paper reports on output performance, including output current total harmonic distortion (THD) and power loss of switching devices, analysis for the various modified DPWM strategies for independent control of per-phase switching loss, which is applicable in 2-level 3-phase voltage source inverters (2L3P VSIs). The results are compared to the corresponding continuous PWM technique to verify and analyze the effectiveness and accuracy of the modified DPWM strategies for independent control of per-phase switching loss.

During the last few decades, insulated-gate bipolar transistor (IGBT) power modules have evolved as reliable and useful electronic parts due to the increasing relevance of power inverters in power infrastructure, reliability enhancement, and long-life operation. Excessive temperature stresses caused by excessive power losses frequently cause high-power-density IGBT modules to fail. As a result, module temperature monitoring techniques are critical in designing and selecting IGBT modules for high-power-density applications to guarantee that temperature stresses in the various module components remain within the rated values. In this paper, a module’s different losses were estimated, a heating pipe system for the thermal power cycling technique was proposed, and finite element method (FEM) thermal modeling and module temperature measurement were performed using ANSYS Icepak software version 2022 R1 to determine whether the IGBT module’s temperature rise was within acceptable bounds. To test the proposed technique, a proposed design structure of the practical railway application with a 3.3 MW traction inverter is introduced using commercialized IGBT modules from Semikron company with maximum temperature of about 150 °C. the FEM analysis results showed that the maximum junction temperature is about 109 °C which is in acceptable ranges, confirming the appropriate selection of the employed IGBT module for the target application.

Direct current (DC) networks play a pivotal role in the growing integration of renewable energy sources. However, the occurrence of DC arc faults can introduce disruptions and pose fire hazards within these networks. In order to ensure both safety and optimal functionality, it becomes imperative to comprehend the characteristics of DC arc faults and implement a dependable detection system. This paper introduces an innovative arc fault detection algorithm that leverages current filtering based on the empirical rule in conjunction with intelligent machine learning techniques. The core of this approach involves the sampling and subsequent filtration of current using the empirical rule. This filtering process effectively amplifies the distinctions between normal and arcing states, thereby enhancing the overall performance of the intelligent learning techniques integrated into the system. Furthermore, this proposed diagnosis scheme requires only the signal from the current sensor, which reduces the complexity of the diagnosis scheme. The results obtained from the detection process serve to affirm the effectiveness and reliability of the proposed DC arc fault diagnosis scheme.

Arc phenomena are usually related to the undesired disengagement of two electrical connections. The emission power discharge from the failure arc may damage wiring and can present a fire hazard. Numerous studies have been proposed to detect arc events and quickly isolate them from an electrical system. DC arc faults are often sorted into two types: series and parallel arcs. A series arc may be the outcome of discharging links in electrical wiring. By contrast, the parallel arc occurs between two electric wires, or between a link and a ground, owing to contamination or poor isolation. The currents in a system with an arc fault are considerably greater when the arc parallel in nature than when the arc is series in nature. In this paper, the electric activities of a network are investigated for the duration of series and parallel arc failures in both the time and frequency domains. The arcing behavior investigated is selected to allow for the identification of series and parallel arcs. The sorting of electrical arcs in an accurate and reliable manner is useful for electrical protection schemes. The identification process used here is based on data related to different domains, such as load current and voltage. In this study, eight learning techniques are investigated with the aim of detecting series and parallel arc faults. The arc behaviors were studied in the various domains. We used the load current and voltage characteristics as an statistic for categorizing a given arc failure. This study could be beneficial to enhance the stability and reliability of arc-fault detectors.

This paper proposes a per-phase switching frequency control method to extend the lifespan of a three-phase voltage source inverter. The model predictive control that can intuitively deal with various control objectives is used in the proposed method. The cost function of the proposed technique consists of two terms. One is for current control, and another is for switching frequency control of each phase. Also, if necessary, a term for capacitor current RMS reduction can be added to the proposed cost function. The proposed technique reduces the switching loss of the most aged phase by reducing the number of switching operations. As a result, the reduced switching losses lower the junction temperature of the switching device. This extends the lifetime of the switching device. In addition, in the proposed technique, the capacitor current RMS, which can increase due to the per-phase switching frequency control, is effectively reduced by using the optional term for the capacitor current RMS reduction. The performances of the proposed method were verified through simulations and experiments.

The conventional ultra-high-speed motor (UHSM) has been mostly developed for light load (or low power) applications (e.g., ~100W, 500 kr/min). However, the new mechanical antenna system requires a high-power UHSM. Accordingly, the conventional design approach of low-power UHSM cannot address the new challenges, especially with high-power design. The new challenges include lowered critical bending resonance (CBR) due to higher rotor aspect ratio ( $L/D$ ), ineffective electrical loading in the slotless stator due to commonly used three-phase winding, and significant temperature variation unusually in the axial direction and its mutual impact on the electromagnetic and mechanical performances. To address these new challenges, this paper proposes a quasi-3D thermal model to estimate critical temperature variations, a Rotordynamic model to limit CBR frequencies above the rated speed, and an electromagnetic model with multiphase winding to increase electrical loading in the slotless stator effectively. These models are systematically integrated to develop a unique Multiphysics multi-objective optimization (MMO) method, which enables (i) the mutual influence analysis among Multiphysics performances, such as thermo-electrical and thermo-physical that are critical in HP-UHSM, and (ii) a precise trade-off analysis between the efficiency and design safety margin (DSM). To validate the effectiveness of the proposed new MMO method, a 2-kW 500 kr/min UHSM, the highest power rated motor at this speed to the best of author’s knowledge, is designed for a mechanical antenna system and experimentally validated. It provides 94.5% efficiency with 30% DSM at 500 kr/min and no CBR below 11 kHz.

The unwanted electric discharge usually relates to arc phenomena between two connectors. The energy from an arc might fuse the electric wiring and be responsible for a fire. Various researches have been investigated for safety operations to improve detected techniques for arc diagnosis. There are two types of arc faults: parallel and series arcs. A parallel arc happens among two electrical lines, or line and ground, due to degrading insulation or contamination. On the other hand, a series arc might result from releasing connections in the wiring. The system’s current can be significantly increased by parallel arc fault compared with the series arc. In this work, the electrical behavior of the system is investigated during parallel arc faults to understand the arcing characteristics from different cases, identify electrical characteristics that are useful and reliable for the diagnosis process, and determine the location of the fault based on current or voltage of the faulted system. Eight learning techniques are adopted to detect arc fault in this study. Parallel arc signals were analyzed in the time and frequency domains, and unique characteristics of the current are extracted using Fourier analysis as an indicator for diagnosing an arc fault. This research can be used to improve arc-fault detector reliability and robustness.

This paper proposes a series and parallel DC arc detecting and identifying (SPADI) technique using the frequency features of the load current ( $I_{L}$ ) and the load voltage ( $V_{L}$ ). The frequency changes in $V_{L}$ and $I_{L}$ under the series and parallel arc are different. The parallel arc can only raise the high-frequency components of $V_{L}$ . In contrast, the high-frequency components of $I_{L}$ can be increased in both series and parallel arcs. However, the increasing frequency range is different. The high-frequency components of $I_{L}$ generated by the series arc are concentrated in the 5 kHz to 40 kHz band. Meanwhile, the high-frequency components of $I_{L}$ caused by the parallel arc are observed evenly in all frequency ranges. Inspired by these features, $V_{L}$ ’s 5 kHz to 100 kHz components are used to sense the parallel arc in the proposed technique. In addition, the series arc is detected using the 5 kHz to 40 kHz and 50 kHz to 100 kHz bands of $I_{L}$ . Experimental tests verified the proposed algorithm implemented at the digital signal processor (DSP). As a result of 160 repeated tests, the probabilities of detecting the series and parallel arc were 100 % and 96.25 %, respectively. Moreover, the probability of correctly identifying the arc type when detecting the arc was 100 %. Also, the average detection times of the series and parallel arc were 0.11 s and 0.16 s, respectively.

Due to the lack of comparative studies between discontinuous pulse-width modulation and model predictive control methods for reducing switching losses in two-level three-phase voltage source inverter, a comparative analysis of a generalized discontinuous pulse-width modulation and two model predictive control approaches for reducing switching losses is studied in this paper. Both generalized discontinuous pulse-width modulation and two model predictive control approaches are described and conducted in the simulation and experiment. The output performance is obtained by these methods after conducting in various conditions, including switching frequency, output power, and load conditions. It is validated that the generalized discontinuous pulse-width modulation control scheme achieves a better control performance at steady-state, while two model predictive control schemes have better transient-state performance with a superior dynamic. Additionally, the generalized discontinuous pulse-width modulation approach achieves better reducing switching losses performance and has slightly higher efficiency than that of two model predictive control approaches.

This paper proposes a lifespan extension technique for three-phase voltage inverters using hybrid offset voltage. The proposed method lengthens the inverter lifetime by independently adjusting the switching frequency of the three phases in accordance with the aging degree. To reduce the switching operation of the phase with the shortest lifetime, the proposed technique injects the offset voltage for generalized discontinuous pulse-width modulation PWM (GDPWM) into the reference voltage in the region where the switching operation of the shortest lifespan phase can be stopped. When the switching operation does not need to be stopped, the offset voltage for space vector PWM (SVPWM) is injected into the reference voltage for high inverter load current quality. An offset voltage that varies according to the need to stop the switching operation is the proposed hybrid offset voltage. Using the proposed hybrid offset voltage, the switching frequencies of the three phases are independently controllable. In addition, since only the switching operation of the phase having the shortest lifespan is reduced, the load current quality in accordance with the switching operation reduction is good compared to the conventional method to simultaneously diminish all phase switching frequencies. The proposed method significantly increases the reliability of the three-phase voltage inverter, where the thermal stress of the phase having the shortest lifespan is decreased up to 55%, whereas the inverter lifetime can be increased by 10 times. The proposed technique was verified by simulations and experiments.

As the use of interleaved DC–DC converters in electric vehicles (EVs) increases, research on reliability improvement is required. In the case of interleaved DC–DC converters, degradation occurs between transistors and capacitors. In particular, transistor degradation imbalances cause an increase in output capacitor RMS current, which increases power loss and accelerates capacitor degradation. This degradation affects system reliability by increasing thermal stress. In this paper, based on a degraded 2-leg interleaved DC–DC boost converter, research to reduce the converter’s output capacitor RMS current was conducted. The output capacitor RMS current according to the transistor degradation imbalance was analyzed. As a result, it was confirmed that the transistor degradation imbalance causes an increase in the capacitor RMS current. To address this issue, a phase optimization algorithm for reducing increased capacitor RMS current is presented in this paper. Next, the phase optimization algorithm is mathematically analyzed. Finally, its efficacy is proved through simulations and experiments.

This paper proposes a novel, degradation-sensitive, adaptive SST controller for cascode GaN-FETs. Unlike in traditional transformers, a semiconductor switch’s degradation and failure can compromise its robustness and integrity. It is vital to continuously monitor a switch’s health condition to adapt it to mission-critical applications. The current state-of-the-art degradation monitoring methods for power electronics systems are computationally intensive, have limited capacity to accurately identify the severity of degradation, and can be challenging to implement in real time. These methods primarily focus on conducting accelerated life testing (ALT) of individual switches and are not typically implemented for online monitoring. The proposed controller uses accelerated life testing (ALT)-based switch degradation mapping for degradation severity assessment. This controller intelligently derates the SST to (1) ensure robust operation over the SST’s lifetime and (2) achieve the optimal degradation-sensitive function. Additionally, a fast behavioral switch loss model for cascode GaN-FETs is used. This proposed fast model estimates the loss accurately without proprietary switch parasitic information. Finally, the proposed method is experimentally validated using a 5 kW cascode GaN-FET-based SST platform.

Owing to the low number of submodules (SMs) in modular multilevel converters (MMCs), especially in medium-voltage applications, the output current and voltage generated by conventional nearest-level control (NLC) methods contain evident distortions. Previously, various hybrid and level-increased NLC methods have been proposed to improve the output voltage quality, but such measures wither increased the complexity or did not regulate all the control objectives simultaneously. To further enhance the output performances of MMCs containing low numbers of SMs, an improved predictive NLC (I-PNLC) method combining NLC and model predictive control (MPC) is proposed, where the output and circulating currents are regulated with the corresponding predicted references, and the output voltage is controlled by the added voltage correction. The proposed I-PNLC not only reduces the output current and voltage total harmonic distortion (THD) considerably but also avoids additional complexity in the control system design. The results of simulations and an experiment are presented to verify the proposed approach, in addition to a comparison of the evaluations of conventional NLC methods.

This paper proposes a DC series arc detection algorithm in a photovoltaic (PV) system using an adaptive moving average (AMA). The proposed algorithm uses two moving averages of $F_{av}$ which is the average of 5 kHz to 40 kHz frequency band. One is ${MA}_{small}$ which is the moving average highly affected by recent $F_{av}$ . The other is ${MA}_{large}$ which is the moving average heavily affected by past $F_{av}$ . There is a little difference between ${MA}_{small}$ and ${MA}_{large}$ before arcing because $F_{av}$ is approximately constant. However, this difference increases when the arc occurs because ${MA}_{large}$ slowly follows ${MA}_{small}$ . This difference is used as an arc detection indicator (ADI) in this study. Additionally, AMA is proposed to avoid nuisance tripping in the normal transient state. The proposed method determines the arc occurrence using the relative magnitudes of the two moving averages. Therefore, it is less affected by the shape of the frequency fluctuations caused by the load inverter. Hence, the proposed algorithm is effective in the centralized and spread-type of frequency fluctuations. These results were verified through an arc detection test and nuisance tripping test using arc experimental data and MATLAB.

The wide variety of arc faults induced by different load types renders residential series arc fault detection complicated and challenging. Series dc arc faults could cause fire accidents and adversely affect power systems if not promptly detected. However, in practical power systems, they are difficult to detect because of a low arc current, absence of a zero-crossing period, and various abnormal behavior based on different types of power loads and controllers. In particular, conventional protection fuses may not be activated when they occur. Undetected arc faults could cause false operation of power systems and potentially lead to damage to property and human casualties. Therefore, it is imperative to develop a detection system for series arc faults in DC systems for the reliable and efficient operation of such systems. In this study, several typical loads, especially nonlinear and complex loads such as power electronic loads, were chosen and analyzed, and five time-domain parameters of the current—average value, median value, variance value, RMS value, and distance of the maximum and minimum values—were chosen for arc fault detection. Various machine learning algorithms were used for arc fault detection and their detection accuracies were compared.

Series arc faults are becoming more dangerous in DC systems. Without detecting in time and separation correctly, these fault events can cause electrical fires or explosions, creating a massive threat to people’s safety and properties. This paper presents an analysis and comparison of DC series arc fault detection using various artificial intelligence (AI) algorithms in DC systems. The combinations of six feature parameters in both time and frequency domains with various AI techniques are recommended to detect DC series arc fault effectively. The performance and effectiveness of different combinations between feature parameters and learning techniques are summarized and discussed. Finally, practical challenges are identified, and suitable combinations of feature parameters and learning techniques are recommended for different operation conditions.

Nearest-level control (NLC) is a popular technique used in modular multilevel converters (MMCs) with a large number of submodules (SMs) owing to the NLC's flexibility and ease of implementation. However, in medium-voltage applications, MMCs contain a relatively low number of SMs, and the drawbacks of the NLC methods emerge, wherein the poor quality of output voltages and currents result in high total harmonic distortion, large ripples in SM capacitor voltages, and unsuppressed circulating currents. Several NLC methods have been proposed to handle these problems, but they do not satisfy all the control objectives simultaneously. This paper proposed a modified NLC capable of enhancing the output quality of MMCs with low number of SMs without deteriorating the control objectives. Unlike previously reported NLC methods, instead of directly calculating the numbers of SMs from the upper and lower arm voltage references, the difference and total number of SMs are obtained from the output voltage reference and circulating current control, respectively. Hence, the numbers of SMs in the upper and lower arms are acquired by simply solving a system of first-order two-variable equations. The simulated and experimental results for a single-phase MMC system were used to verify the appropriateness and effectiveness of the proposed modified NLC method.

The reliability of the electronic converter is a vital concern in an industrialized area. Capacitors are critical in electronic converters and are more likely to fail than other electronic gears. Due to aging, the capacitor progressively loses its original quality and capacitance, and the equivalent series resistance escalates. Hence, condition monitoring is a fundamental procedure for evaluating capacitor health that affords prognostic repairs to guarantee stability in power networks. The ESR and capacitance of the capacitor are commonly employed to estimate the condition grade. This study proposes an estimation scheme that utilizes the source current to assess the health condition of an aluminum capacitor. Several advanced intelligence techniques are adopted to estimate the parameters of an AEC in a three-phase inverter system. First, different signals used as inputs, such as input power, capacitor current, voltage, and power, output current, voltage, and power, are analyzed using fast Fourier transform and discrete wavelet transform analysis. Then, various indexes of the analyzed signals, such as RMS, average, median, and variance, are used as the inputs in learning models to monitor the AEC’s parameters. In addition, various input signals are combined to obtain the best combinations for capacitor monitoring. The estimated results prove that utilizing the source current combined with selected indexes improves the monitoring accuracy of the AEC’s health status.

In this paper, the performance variations of SiC MOSFET-based voltage and current source inverters under gate oxide degradation are studied. It is confirmed that the turn-on and turn-off delays of SiC MOSFETs change significantly by high electric field stress, which accelerates the gate oxide degradation. Variations in the turn-on and turn-off delays of switching devices extend or reduce the duty error of voltage source inverters and current source inverters. The performance variations of the voltage and current source inverter due to the duty error changes caused by the gate oxide degradation are analyzed through simulations. As a result, the gate oxide degradation worsens the performance of the voltage source inverter. Furthermore, the negative gate oxide degradation, which lowers the threshold voltage, decreases the performance of the current source inverter.

This paper proposes a novel input power factor control method based on a concept of virtual capacitors to provide unity input power factor for three-phase matrix rectifiers. The proposed algorithm introduces, at the input terminal of the matrix rectifier, an imaginary input capacitor generated by modifying a reference vector of the space vector modulation method. The virtual input capacitor, which is fictitiously built in parallel with an input LC filter, successfully compensates for the leading power factor of the LC filter of the matrix rectifier. Thus, the proposed method yields a unity power factor operation despite the presence of the LC filter of the three-phase matrix rectifier. In addition, under a condition when the unity power factor operation cannot be realized, the proposed algorithm adjusts a virtual capacitance to obtain a maximum achievable power factor operation. Because the proposed technique yields the input power factor control by introducing the virtual capacitor and adjusting a reference space vector, the proposed algorithm can be easily incorporated with conventional space vector modulation algorithms for the three-phase matrix rectifiers. Thus, the proposed method can control input power factor without employing proportional-integral controllers used in conventional power factor control methods for the matrix rectifiers, leading to simple control structure and straightforward tuning process for power factor control.

This paper proposes a direct power control (DPC) method with a minimum reactive power reference for ac-to-dc matrix rectifiers using space vector modulation. Based on the calculated active and reactive power reference values, the developed DPC algorithm directly controls both the active and reactive power components of the source by operating the three-phase matrix rectifiers, thereby obtaining the sinusoidal input currents and output dc voltage/current of the rectifier. The proposed DPC method instantaneously determines a source reactive power reference command to achieve a unity input power factor or maximum achievable power factor on given input and output conditions, because ac-to-dc matrix rectifiers cannot always attain a unity power factor due to the existence of the input capacitors. In addition, the developed algorithm calculates the minimum reactive power reference without using any circuit parameters. Thus, the proposed algorithm is free from any inevitable parameter uncertainty, resulting in a more robust and accurate power factor control for the rectifier. Based on the minimum reactive power reference, the proposed algorithm enables matrix rectifiers to operate at an input power factor that can be maximally obtained at all times. The effectiveness of the proposed method was verified by the simulations and experiments.

This paper presents switch fault detection and compensation control schemes for a modified dc-dc converter that relocates a diode location. The proposed fault detection and compensation control schemes are applicable to various energy generation systems that include energy storage. A fault detection index has been introduced to detect an open switch fault in the modified converter structure, and a compensation control method based on a mixed switching strategy has been developed. The fault-tolerant control method along with the detection scheme can make a system return to work even under a switch fault. The proposed schemes have been tested and verified both by the simulations and by experiments using a TMS320F28335 DSP. The results will significantly improve the reliability of alternative energy generation systems against open switch faults.

High modularity, easy scalability, and superior harmonic performance, comprising the topology with the most potential for medium- to high-voltage high-power applications, are representative features of a modular multilevel converter (MMC). Each application of a MMC requires a proper scheme such that it conforms to control objectives such as correct submodule capacitor voltage balancing control and the suppression of circulating current. Over the past few years, various studies have been presented that meet the MMC requirements through both classical control-based pulse-width modulation and model predictive control, although some drawbacks exist for both control concepts. The dynamic performance of the classical control methods with proportional-integral or proportional-resonant controllers is unsatisfactory, and the requirement of proportional-integral parameters tuning procedure makes converter operation performance depends on proportional-integral parameters adjustment. Meanwhile, model predictive control performance depends significantly on the mathematical model of a system, and weighting factor selection is tedious. In this paper, we propose an improved phase-shifted carrier pulse-width modulation method and capacitor voltage balancing control that inherits the merits from both classical control and model predictive control. Meanwhile, the proposed control method eliminates the requirement of the tedious proportional-integral parameters tuning procedure and improves the dynamic performance compared with the conventional phase-shifted carrier pulse-width modulation-based proportional-integral controller method. Simulations and experiments were conducted to demonstrate the proposed method's properness.

This paper proposes a model predictive virtual flux control (MPVFC) method that can mitigate the degradation of the total harmonic distortion of rectifier input currents experienced by active frontend (AFE) rectifiers when input voltages are distorted by harmonics. The proposed method utilizes a cost function based on virtual fluxes, which are robust to input voltage distortions, to control the rectifiers. For the calculation of the proposed cost function which consists of a predictive value of the rectifier virtual flux and a reference of the rectifier virtual flux, the dynamics of AFE rectifiers and the definition of the integration in the discrete time domain are used. Also, the phase of the reference current which is needed when calculating the reference of the rectifier virtual flux is obtained by the input virtual flux. The proposed MPVFC method shows better input current waveforms with lower total harmonic distortion than those obtained with the conventional model predictive control method under input voltage distortion conditions, which was proved via simulations and experiments.

A predictive direct power control (PDPC) technique to decrease switching loss by injecting offset voltage is proposed for three-phase voltage source converters. The active and reactive power elements of the converter are directly controlled by using three-phase future converter input voltages, which are modified for lowering switching losses by injecting a future offset voltage. Switching operations, generated by the developed PDPC algorithm with modified converter voltage, stop switching operation in one of the converter phases exposed to the highest input current. The non-switching period and the non-switching phase in the proposed technique is automatically adjusted by the reactive power reference, which leads to high efficiency, irrespective of varying input power factor angle condition. The proposed algorithm chooses one optimal voltage vector enabling future active and reactive power to approach closest to the future power references and prohibiting switching of one converter phase conducting the highest current at each step. Therefore, the developed technique can directly control power components and increase converter efficiency, which is proven by simulation and experimental verification.

Demand for modular multilevel converters (MMCs) has been steadily increasing for utilization in medium- to high-power applications because of qualities such as high modularity, easy scalability, and superior harmonic performance. Furthermore, there has been a growing trend toward utilizing model predictive control for MMCs due to its simplicity, good dynamic response, and ease of multi-objective control. However, the rise in computational load leads to a great drawback when increasing the number of submodules (SMs). This paper presents an approach to reducing the computational load and using on-state SMs and circulating currents, by preselecting the number of SMs inserted in the upper and lower arms. This approach is based on using the number of on-state SMs and the circulating current, to compute the number of SMs inserted in the upper and lower arms, which is evaluated in the next sampling instant. This facilitates a significant reduction in the number of control options and the computational load. A sorting algorithm is used to retain the balancing capacitor voltages in each SM, while the cost function guarantees the regulation of the ac-side currents, arm voltages, and MMC circulating currents. Simulation and experiment results validate the performance of the proposed approach.

Active front-end rectifiers are tasked with generating high-quality, low-distortion sinusoidal line currents in the presence of adverse circuit conditions. When suitable control methods are applied to such rectifiers, significant performance improvements can be realized, especially under abnormal utility conditions. Although several control methods based on model predictive control platforms have been recently developed, there is a lack of comparative studies of these methods in the literature. In this paper, the details and theoretical background of four model predictive control methods, namely, current control, virtual flux control, direct power control, and virtual flux direct power control, are presented. Then, the performance of these methods was compared by the way of experiments to determine the respective quality of the line current under various conditions, such as unbalanced input voltages, input voltage distortion, uncertainty in the parameters, and dc voltage fluctuation. In summary, based on the results of the experiments, the virtual flux control scheme was found to be distinctly superior to the other three schemes for distorted and unbalanced line voltages.

When single-phase three-level neutral-point-clamped (NPC) converters operate, there are two main control objectives that need to be met for correct operation. First, the ac source current must be controlled to be sinusoidal. Second, the dc capacitor voltages must be balanced. In original model predictive control (MPC) methods for NPC converters, an optimization process involving an empirical weighting factor design is required to meet both of these objectives simultaneously. This study proposes an MPC approach developed for single-phase three-level NPC converters to meet these objectives using a single reference voltage consisting of a difference-mode term and a common-mode term in each phase. The difference-mode term and the common-mode term are responsible for sinusoidal ac source current synthesis and dc capacitor voltage balancing, respectively. Then, a single cost function compares the adjusted reference voltage with possible voltage candidates to select an optimal switching state, resulting in the smallest cost function value. Different from the conventional MPC method, the proposed approach avoids the selection of weighting factors and the attendance of various control objectives. Thanks to the deterministic approach, the proposed MPC method is straightforward to implement and maintain fast transient performance while guaranteeing the control objectives. Finally, the effectiveness and feasibility of the proposed approach for single-phase three-level NPC are verified through comprehensive experimental results.

A predictive control method using injected offset voltage to achieve neutral point (NP) voltage balance of three-phase three-level neutral point clamped (NP) rectifiers, without employing a weighting factor, is proposed in this study. One of the biggest problems with the three-level NP rectifiers is the dc link capacitor voltage imbalance. Therefore, it is necessary to maintain the balance of the NP voltage in addition to synthesize the three-phase sinusoidal input current by control methods. Conventional predictive control methods for the NP rectifiers have used a weighting factor in a cost function that determines the control ratio of the input currents and the capacitor voltage balance. As a result, it is burdensome to empirically redesign the weighting factor when the rectifiers’ parameter values and control conditions change. Unlike the conventional methods, the proposed approach without the weighting factor can significantly eliminate differences between two DC capacitor voltages by utilizing an offset voltage, which is generated by using the difference between the upper and lower capacitor voltages. Consequently, the proposed approach using the offset voltage injection can control the input currents and retain the balance of NP voltage. Simulation and experiments are presented to verify the correctness of the NP voltage balancing of the proposed control method.

Capacitors are critical components of power converter systems as they influence the cost, size, performance, and scale of such systems. However, capacitors exhibit the highest degeneration and breakdown rates among all power converter components due to their wear-out failures and short lifespans. Therefore, condition monitoring is a vital process to estimate the health status of capacitors and to provide predictive maintenance for ensuring stability in the operation of power converter systems. The equivalent series resistance (ESR) and the capacitance of the capacitor are two widely used parameters for evaluating the health status of capacitors. Unlike the ESR, the capacitance of a capacitor is suitable for the health monitoring of various types of capacitors; therefore, it is more preferable for large-scale systems. This paper presents an overview of previous research addressing this aspect of capacitors and provides a better understanding of the capacitance monitoring of capacitors utilized in power converter systems.

This paper proposes a highly efficient single-phase three-level neutral point clamped (NPC) converter operated by a model predictive control (MPC) method with reduced commutations of switches. The proposed method only allows switching states with none or a single commutation at the next step as candidates for future switching states for the MPC method. Because the proposed method preselects switching states with reduced commutations when selecting an optimal state at a future step, the proposed method can reduce the number of switchings and the corresponding switching losses. Although the proposed method slightly increases the peak-to-peak variations of the two dc capacitor voltages, the developed method does not deteriorate the input current quality and input power factor despite the reduced number of switching numbers and losses. Thus, the proposed method can reduce the number of switching losses and lead to high efficiency, in comparison with the conventional MPC method.

In multilevel cascaded H-bridge (CHB) inverters, the number of voltage vectors generated by the inverter quickly increases with increasing voltage level. However, because the sampling period is short, it is difficult to consider all the vectors as the voltage level increases. This paper proposes a model predictive control algorithm with reduced computational complexity and fast dynamic response for CHB inverters. The proposed method presents a robust approach to interpret a next step as a steady or transient state by comparing an optimal voltage vector at a present step and a reference voltage vector at the next step. During steady state, only an optimal vector at a present step and its adjacent vectors are considered as a candidate-vector subset. On the other hand, this paper defines a new candidate vector subset for the transient state, which consists of more vectors than those in the subset used for the steady state for fast dynamic speed; however, the vectors are less than all the possible vectors generated by the CHB inverter, for calculation simplicity. In conclusion, the proposed method can reduce the computational complexity without significantly deteriorating the dynamic responses.

Voltage source inverters operated by predictive control methods generally lead to a variable switching frequency, because predictive control methods generate switching operation based on an optimal voltage state selected at every sampling period. Varying switching frequencies make it difficult to design output filters of voltage source inverters. This paper proposes a predictive control algorithm with a constant switching frequency for the load current control of single-phase voltage source inverters. This method selects two future optimal voltage states used in the subsequent sampling period, which are a zero-voltage state and a future optimal voltage state, based on the slope of the reference current at each sampling period. After selecting the two future voltages, the proposed method distributes them to produce a constant switching frequency and symmetric switching pattern. The performance of the proposed method is validated with both simulation and experimental results for single-phase voltage source inverters.