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The authors developed a wideband on-chip Wilkinson power divider (WPD) using lumped-element transmission lines (LE TLs) with 2-port negative capacitance (NCAP) circuits that provide the phase response with a positive slope and broadband port impedance. The bandwidth of the WPD was increased using the broadband quarter-wavelength ( λ /4) LE TLs with port-matched NCAP circuits. The WPD was implemented in the Global Foundry 8SF 130-nm RF CMOS IC technology. The size of the core chip is 1100 µm × 400 µm. The S-parameter measurements showed an absolute bandwidth ranging between 0.76 and 1.6 GHz, and a fractional bandwidth of 71.2%. In the frequency range of the bandwidth, the insertion loss was 0.4–3.4 dB, with the isolation between the two output ports was >18 dB, and the noise figures were 11–12 dB. The input-referred 1-dB gain compression point at the frequency of 1 GHz was ‒6 dBm.

We propose a wideband lumped element directional coupler using lossy negative capacitance (NCAP). NCAP provides a broadband resonance effect combined with passive inductors and capacitors in a circuit, enabling the coupler to exhibit wideband directivity performance. In addition, a 3-dB loss in the NCAP enhanced the bandwidth at the expense of the transmission gain, which decreased by only 0.3 dB. The proposed coupler was implemented in the IBM 7RF 180-nm CMOS technology. The size of the core chip is $1180\,\,\mu \text {m} \times 570\,\,\mu \text{m}$ . The designed NCAP provides a capacitance of −13 pF using a supply voltage of 2.7 V and a current of 9.6 mA. The coupling was designed to be −10 dB at the center frequency of 1 GHz. The bandwidth was defined by the frequency range, which exhibited a directivity of more than 30 dB. The S-parameter measurements showed an absolute bandwidth ranging from 0.86 to 1.12 GHz, and a fractional bandwidth of 26%. In the bandwidth, the coupling had a 0.5-dB variation, the transmission loss was smaller than 2.14 dB, and the noise figures were 1.8–2.5 dB.

Herein, we present a floating 2-port nonreciprocal negative capacitance (NCAP) circuit that employs a unilateral gain boosting technique by including an asymmetric cross-coupled differential cascode transistor pair. The proposed circuit provides an asymmetric gain characteristic. The forward gain ( $S_{21}$ ) is increased at the cost of the backward gain ( $S_{12}$ ). The technique not only provides a boosted forward gain but also stable operation resulting from this reduced backward gain. We further investigate the stability of the NCAP circuit in terms of the output resistances of the current sources in the circuit. The proposed NCAP circuit was implemented in IBM 7RF 180-nm CMOS technology and was designed to have a supply voltage of 3 V and a current of 10 mA. The S-parameter measurements showed a self-resonance frequency of 2.25 GHz. The maximum $S_{21}$ was −0.2 dB at 1 GHz. In the frequency range from 0.5 to 1.5 GHz, the capacitance was approximately −4 pF, and the difference between $S_{21}$ and $S_{12}$ was 8.7–9.6 dB. The size of the core chip was $150 \times 190~\mu \text{m}^{2}$ .

This paper presents a power amplifier module (PAM) that operates efficiently in low-power mode for IEEE 802.11g Wi-Fi applications. The PAM consists of a power amplifier (PA), a buck converter, and a power detector. Two packaging technologies were used to integrate the compact module: a low-temperature co-fired ceramic (LTCC) technology and a ferrite-filled printed circuit board (PCB) technology. The LTCC portion includes radio-frequency inductors, capacitors, transmission lines, and interconnection lines to minimize the overall size, while a power inductor for the buck converter is implemented in ferrite-filled PCB. The PA and the buck converter are designed in 2- $\mu \text{m}$ InGaP/GaAs heterojunction bipolar transistor technology and 0.35- $\mu \text{m}$ CMOS technology, respectively. The output power level is converted into a voltage by the power detector, and the voltage controls the buck converter, thereby optimizing the supply voltage of the PA. This adaptive supply voltage helps to improve the power-added efficiency (PAE) in the low-power regime while maintaining linearity. The PAM showed an error vector magnitude of less than 4% up to an output power of 22 dBm. The PAE is 8% and 11% at output powers of 11 and 16 dBm, respectively, representing respective improvements of 60% and 43%. The overall size of the PAM is $5 \times 7.5 \times 1.2$ mm $^{\mathrm {\mathbf {3}}}$ .

An ultra-compact and wideband low noise amplifier (LNA) in a quad flat non-leaded (QFN) package is presented. The LNA monolithic microwave integrated circuit (MMIC) is implemented in a 0.25 μm GaN IC technology on a Silicon Carbide (SiC) substrate provided by Triquint. A source degeneration inductor and a gate inductor are used to obtain the noise and input matching simultaneously. The resistive feedback and inductor peaking techniques are employed to achieve a wideband characteristic. The LNA chip is mounted in the 3×3-mm 2 QFN package and measured. The supply voltages for the first and second stages are 14 V and 7 V, respectively, and the total current is 70 mA. The highest gain is 13.5 dB around the mid-band, and -3 dB frequencies are observed at 0.7 and 12 GHz. Input and output return losses (S11 and S22) of less than -10 dB measure from 1 to 12 GHz; there is an absolute bandwidth of 11 GHz and a fractional bandwidth of 169%. Across the bandwidth, the noise figures (NFs) are between 3 and 5 dB, while the output-referred third-order intercept points (OIP3s) are between 26 and 28 dBm. The overall chip size with all bonding pads is 1.1×0.9 mm 2 . To the best of our knowledge, this LNA shows the best figure-of-merit (FoM) compared with other published GaN LNAs with the same gate length.

In this article, we present a simplified Doherty power amplifier (DPA) architecture for the easy implementation of dual-band operation. The proposed DPA structure eliminates the 35 Ω quarter wavelength impedance inverters used in the conventional DPAs by matching the output impedances of the carrier and peak amplifiers of the DPA to other values (e.g., 100 Ω). The electrical lengths of the offset line and the phase compensation line are carefully chosen to enhance the Doherty effect (high efficiency at back-off power level) at two assigned frequency bands. Broadband matching networks are also designed to increase the operation bandwidths at the two designed bands. To prove the design concept, a dual-band DPA is designed and measured. In the first frequency band (550–650 MHz), the designed DPA provides 60.6–76.3% drain efficiency (DE) at full output power, 46–54.9% DE at 6 dB of output power back-off (OBO); in the second frequency band (950–1050 MHz), the designed DPA provides 51.4–61.2% DE at full output power, 35–38% DE at 6 dB of OBO. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:953–956, 2015

In a dense environment of loosely-coupled wireless charging pads to which out-of-band signalling is applied, cross-connection errors occur according to the wireless communication distance of out-of-band signalling. A cross-connect abatement technique using received-signal-strength-indicator measurement is proposed to prevent this problem and to provide stable wireless charging. To evaluate the performance of the proposed technique, two compact wireless charger environments are created in an RF shield room. The experimental results indicate that the wireless charging system using the proposed technology provides wireless charging services without cross-connection errors.

This letter presents an active phase shifter providing a quasi-constant transmission (S21) phase over a wide frequency range. The active phase shifter consists of positive and negative inductance/capacitance(L/C). The transmission phase of the positive L/C is compensated by that of the negative L/C along the frequency. The active phase shifter was implemented in IBM 7RF 180 nm CMOS technology. The measured transmission phase ranged between −70° and −110° with a minimum phase variation of 10°, and the insertion loss ranged between 4 and 6 dB from 1.2 to 2.8 GHz. The size of the core chip was $650\times 800\,\,\mu \text {m}^{2}$ .

This letter presents a power amplifier (PA) with an on-chip power detector for 2.4-GHz wireless local area network application. The power detector consists of a clamp circuit, a diode detector, and a coupled line directional coupler. A series inductor for an output matching network in the PA is combined with a through line of the coupler, which reduces the coupling level. Therefore, the coupler employs a metamaterial-based transformer configuration to increase coupling. The amount of coupling is increased by 2.5 dB in the 1:1 symmetric transformer structure and by 4.5 dB from two metamaterial units along the coupled line.

An on-chip power divider with an extremely wide bandwidth is presented. The power divider was implemented in a TSMC 180 nm RF CMOS process. Measurements showed an absolute bandwidth of 68 GHz from 14 to 82 GHz with a matching condition of

This paper presents a folded inductor implemented with a multichip module, which involves a laminate organic packaging technology with an unfilled via process. The folded inductor had an increased inductor layer surface area because of the unfilled vias along the inductor layer. Thus, the quality (Q) factor of the inductor improved as the series resistance, resulting from the skin effect, decreased. The Q-factor for a folded inductor showed a maximum improvement of 32% by including contact resistances, in comparison with the Q -factors of a normal planar inductor.

This paper presents error vector magnitude (EVM) behavior under two different modes of a reference voltage (Vref); one is a static EVM with a constant Vref and the other is a dynamic EVM with a pulsed Vref. A 2.4-GHz two-stage power amplifier (PA) is implemented by GaAs HBT technology to investigate EVM behavior for IEEE 802.11 g wireless local area network application. A square wave pulse with the duty cycle of 50% is applied as Vref for dynamic operation mode. In this paper, it is shown that a dynamic EVM is worse than a static EVM because a transient response of PA output distorts preamble and signal in orthogonal frequency division multiplexing signal bursts. This transient response is explained by a two-pole thermal network in this study, and transient response experiments with a resistor-capacitor (R-C) network at a power supply were performed for verification

Recently, researches to find rational mathematical model for prediction of capsizing have been progressed by ITTC. Lee(1997) developed a mathematical model which describes 6 DOF transient motions, such as capsizing, of a ship in regular waves. In this study a mathematical model for prediction of capsizing in following and quartering seas is developed based on Lee`s model. And factors affecting prediction of capsizing are analyzed through comparing simulation results with experimental results. Present simulation results are compared with ITTC bench mark test results. In rolling tests with beam seas and tree runs with stern quartering seas, capsizing events are predicted well. But calculated roll angle is larger than experimental one. It is found that nonlinear manoeuvring coefficients don`t affect the prediction of capsizing events.

This paper focuses on high-performance LC CMOS voltage-controlled oscillator (VCO) design at 2 GHz with high-Q inductors realized using wiring metal lines in advanced packages. Those inductors are used in the resonator of the VCO to achieve low phase noise, low power consumption, and a wide frequency tuning range. A fine-pitch ball-grid array (FBGA) package and a wafer-level package (WLP) are incorporated to realize the high-Q inductor. The Q-factors of inductors embedded in packages are compared with a Si on-chip inductor. The effects of the high Q-factor on the VCO performance are investigated. In addition, the dominant loss factor in an LC-tank is analyzed from the phase noise perspective. The VCOs using three different inductor technologies are presented. The performance of VCOs using the embedded inductor in a FBGA and a WLP is compared with that of a VCO using the on-chip inductor. The VCO design is optimized from the high-Q perspective to enhance performance. Through this optimization, less phase noise, lower power consumption, and a wider frequency tuning range are obtained simultaneously

This paper presents a power amplifier with an on-chip power detector for 2.4 GHz wireless local area network (WLAN) application. The power detector consists of a clamp circuit, a diode detector and a coupled line directional coupler. A series inductor for an output matching network in the power amplifier is combined with a through line of the coupler, which reduces the coupling level. Therefore, the coupler employs a metamaterial-based transformer configuration to increase coupling. The amount of coupling is increased by 2.5 dB in the 1:1 symmetric transformer structure and by 4.5 dB from 2 metamaterial units along the coupled line.

An ultra-wideband power divider with out-of-band filtering and DC blocking functions is presented. The divider consists of three parallel-coupled lines, a short-circuited shunt stub and a resistor. The divider was implemented in a two-layer printed circuit board with a high dielectric constant. The measurements show a minimum insertion loss of −0.4 dB in the middle band and a rejection of −17 to −18 dBc at 1.5 and 11.5 GHz, respectively.

A CMOS voltage controlled oscillator(VCO) with additional parallel resistors in its LC resonator has been proposed to improve the tuning (frequency-to-voltage) linearity and reduce the tuning sensitivity KVCO. The VCO is linearly tunable from 806 to 1,113 MHz with a 34% tuning range controlled linearly by the tuning voltage. The phase noise of the VCO is −100.4 dBc/Hz at 100-kHz offset frequency from 903MHz carrier. The supply voltage was 1.8V with the current of 2.5 mA flowing through the differential core. The chip size is 0.815 × 0.680 mm2, which has been fabricated in a standard 180-nm CMOS technology.

A frequency-agile load modulation scheme is proposed for reliable near-field magnetic communication with a magnetic resonance wireless power transfer system. A working prototype of the system to realise concurrent power and data transfer in the high-frequency band has been fabricated to verify that demodulation of the load modulation signal state detected on the transmitter side is stable over the distance ranges covering the near-field coupling region. This scheme can be a simple and efficient solution against potential issues such as non-communication and envelope inversion arising from strong magnetic resonance coupling.

Presented is the linearity improvement technique of a power amplifier (PA) using a digitally-controlled tunable output matching network implemented in GaAs BiFET technology. The load impedance of the heterojunction bipolar transistor (HBT) power device in the last stage of the PA is adjustable in terms of output power levels by a metal-insulator-metal (MIM) capacitor array with pHEMT switches in the output matching network. A 2.4 GHz two-stage PA for IEEE 802.11g, Wireless Local Area Network (WLAN) application, is implemented to demonstrate the technique. Not only is the maximum linear output power of the PA increased by 2.5 dB, but the linearity is also improved by 4 dB at the output power of 15 dBm for the error vector magnitude specification of −28 dB.

A technique to improve the linearity of the frequency–voltage (f–V) characteristic and to reduce the differential tuning sensitivity, KVCO, of voltage-controlled oscillators (VCOs) is proposed. The VCO designed using the linearisation technique is tunable from 806 to 1113 MHz with a 34% tuning range and exhibits a nearly constant KVCO of 62 MHz/V over the entire frequency range.

Presented is a systematic approach for the layout optimisation of a Si-based power device by a distributed large model considering all the layout parasitic components resulting from the interconnections. The optimisation in terms of gain, PldB and PAE is shown with the SiGe power devices. Using the optimised power devices, a preliminary two-stage power amplifier was implemented for PCS application.