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Although being the optical lithography, the extreme ultraviolet (EUV) lithography with 13.5-nm wavelength is very different from the deep ultraviolet (DUV) lithography with 193-nm wavelength. Hence, the understanding of the complex detailed EUV mechanisms to cause a chemical reaction in chemically amplified resists (CARs) is required to develop EUV resists and exposure process. In this paper, for organic, metal-organic and metal-oxide resists, the electron-scattering model of exposure mechanisms needs to include the elastic and inelastic mean free paths. On top of that, Dill’s parameters of DUV and EUV resisters from the photo-generated reaction are discussed to indicate the physical and chemical characteristics. For CAR and EUV resists, Dill B parameter is large than Dill A and B parameters.

Plasmonic nanoparticle (NP) arrays with narrow gaps have been suggested as an effective light collection solution for plasmonic structures. For an effective low-cost bottom-up strategy, block copolymer (BCP) self-assembly with evaporative metal-deposition is mentioned as one of the best effective ways to produce Au NP arrays with narrow gaps. In this paper, BCP self-assembly for nanopost-template arrays and metal-deposition over the nanotemplate surface for positional arrangement of Au NPs are described using a self-consistent field theory (SCFT) and a level-set method, respectively. According to the of BCP self-assembly simulation results, both the diameter of the cylinder post and gap size become larger due to the increase of polymerization degree (N). However, these parameters become smaller in terms of the increase of the Flory-Huggins interaction parameter χ. For plasmonic phenomena about a top-down incident wavelength of 600-nm, according to a rigorous coupled-wave analysis (RCWA), although the electric field around a single spherical post becomes larger at smaller diameter, there is no top-down plasmonic phenomenon at a gap size of 10-nm between nanoposts.

The line-edge roughness (LER) is a critical issue that significantly impacts the critical dimension (CD) because the LER does not scale with the feature size. Hence, the LER influences the device performance with 7-nm and 5-nm patterns. In this study, LER impact on the performance of the fin-field-effect-transistors (FinFETs) are investigated using a compact device method. The fin-width roughness (FWR) is based on the stochastic fluctuation such as the LER and the line-width roughness (LWR) in the lithography process. The calculated results of the FWRs and the gate lengths L = 7-nm and 5-nm are addressed with the cases of electric potentials with the y-direction along the gate length, electric potentials with the x-direction along the fin width, and the absolute drain currents with the gate lengths L = 7-nm or 5-nm due to gate voltages. According to the gate length, the impact of the FWR patterns on the performance of fin-field-effect-transistors (FinFETs) can find regular fluctuations.

Extreme ultraviolet (EUV) lithography is a prospective technology for the fabrication of integrated chips with critical dimensions (CDs) under 10-nm. However, since chips with similar CDs have similar defect sizes, one of the most critical problems in extreme ultraviolet lithography (EUVL) is mask defect and repair. Defects cause local areas of undesired absorption, reflectivity, or phase change, which ultimately lead to imperfections in the printed image. For example, phase defects may cause substantial changes in image anomalies with different focuses. In this paper, the results of EUV vote-taking lithography are calculated and compared with other repair methods using the scattering matrix (S-matrix) method. Vote-taking lithography with the assumed perfect defect-free masks (N = 4) can maximize 90% and 91% repair improvements at pit defect and dump defect, respectively.

The extreme ultraviolet (EUV) lithography has the potential to enable 5-nm half-pitch resolution in semiconductor manufacturing, but faces a number of persistent challenges. At the 5-nm technology node, a precise process simulator with nanometer accuracy will be required. For a precise simulation, the better understanding the EUV process mechanism is critical for the improvement of resist performance and the development of new resist materials. In this paper, an EUV stochastic simulator is introduced for the modeling of EUV processes. The line-edge roughness (LER) and resist characters are described for the requirements of 5-nm pattern performance using this stochastic simulation. Through the opportunity to simulate EUVL materials and processes, the performance of EUVL resist and the optimization of EUVL parameters for 5-nm pattern formation can be conducted.

Extreme ultraviolet (EUV) lithography is a prospective technology for the fabrication of integrated chips with critical dimensions (CDs) under 10-nm. However, since chips with similar CDs have similar defect sizes, one of the most critical problems in extreme ultraviolet lithography (EUVL) is mask defect and repair. Defects cause local areas of undesired absorption, reflectivity, or phase change, which ultimately lead to imperfections in the printed image. For example, phase defects may cause substantial changes in image anomalies with different focuses. In this paper, repair methods such as modified absorber, modified absorber with film adding, modified absorber with multilayer peeling, and vote-taking are compared quantitatively using the scattering matrix method.

For the wavelength reduction to overcome the diffraction limit of the optical lithography, the surface plasmon lithography (SPL) has lower cost and simpler system configuration than the extreme ultraviolet (EUV) lithography. In this paper, for the below 10-nm critical dimension (CD) as one of critical challenges in the lithography technology, SPL based on the SP interference and metamaterial in bowtie and hexahedron structures is proposed and demonstrated by using computer simulations such as the rigorous coupled-wave analysis (RCWA) method and the finite difference time domain (FDTD) method. For 193-nm wavelength, the minimum FWHM (the full width at half maximum) of the transverse magnetic (TM) intensity in xz plane (and yz plane) is 10-nm (and 7-nm) in a bowtie plasmonic structure. For hexahedron structures, the minimum 30-nm FWHM of TM intensity with 193-nm wavelength is improved to the minimum 16-nm FWHM by using metamaterial and SP interference.

As the critical dimension (CD) of electronic devices continues to be scaled down to less than 10-nm in size, the lineedge roughness (LER) becomes a critical issue that significantly affects the CD, as well as the device performance because the LER does not scale along with the feature size. Therefore, the LER needs to be reduced to continue to shrink the feature size as well as minimize the device malfunctions. In this study, the LER impacts on the performance of fin-field-effect-transistors (FinFETs) are investigated using a compact device method. For the fluctuation of electric potentials due to the fin-width roughness (FWR) based on the stochastic fluctuation during the lithography process, electric potentials with fat-fin, thin-fin, big-source, and big-drain FWRs are right shift, left shift, down shift, and upper shift to the electric potential without FWR, respectively. For the fluctuation of drain currents due to gate voltages, drain currents with fat-fin, big-source, and big-drain FWRs are righter shift in order. According to the Taguchi method, gate voltage and channel length are more dominant parameters on the sensitivity of electronic potential and current drain of a FinFET device.

For the extreme ultraviolet (EUV) lithography, multilayer (ML) defects such as bump and pit defects can disrupt the phase of reflected field and degrade aerial images on wafer. In this paper, a defect printability and repair simulator (DPRS) is introduced to predict and repair the effect of ML defects in EUV aerial images. DPRS is composed of multilayer growth by using Gaussian function and Stearns's method, mask simulation by using a scattering matrix (S-matrix) analysis method, and projection simulation by using Köhler's illumination. For bump and pit ML defects, the combining the modified absorber and the layer-by-layer ML peeling is better than other methods. This study can be helpful in understanding EUV defect and also give insight into the EUV defect compensation for the device volume production.

When the variety of personal health services are provided in the ICBM(IoT, Cloud, Bigdata, and Mobile) environment, the security requirements of personal health service(PHS) including privacy issues is proposed in this paper. Because it is expected that the services related to personal health are provided in the cloud environment, the security requirements of a cloud environment is firstly investigated and then security threats including direct and indirect threats in a cloud environment are analyzed in terms of the security of PHS. In addition, the security requirements of PHS is developed based on the security requirements of electronic medical record(EMR) for medical service in this paper, then the validity of the proposed security requirements is shown by the relation between security requirements of cloud environment and PHS to indicate that a security requriement is supported by several security requirements of PHS.

The extraordinary optical transmission through a sub-wavelength size metal-aperture and metamaterials has been tremendous interests for the untilization of the surface plasmon polariton (SPP). Its technology, however, is hard to apply for the optical lithography process. In this study, a maskless plasmonic lithography (MPL) is modeled and simulated for 15-nm critical dimension (CD). The near-field intensity with the plasmonic phenomena of aperture shapes is described due to aperture parameters by using a scattering matrix (S-matrix) analysis method and the finite difference time domain (FDTD) method. MPL parameters of bowtie structures are optimized and improved for the imperfection of the resist pattern. The most dominant parameter on CD is gap size of bowtie by Taguchi method.

To make cloud computing environments more secure, this paper focuses on the security of virtualized server systems. A security layer is introduced to the secure architecture of a virtualized server as an abstraction. Because the security layer will play a key role in securing the virtualized server, there is a need for it to be sufficiently robust to tackle the most common security threats associated with cloud computing. First, security threats to cloud computing are analysed based on a publication from an international organization and the security issues surrounding virtualized servers are clarified. Following this, the security elements and their functions for each of the security requirements for virtualized servers are defined. The relationship between the security issues and security elements is then presented to verify the effectiveness of the security layer. It is shown that, using the proposed security elements, the security issues facing virtualized server systems in cloud computing are adequately mitigated. Therefore, our research will be helpful in the development of virtualized servers by making cloud computing more secure.

The inrush current of a large inductive load can be reduced with a soft starter; however, the large inrush current caused by simultaneous bulk starts (SBSs) cannot be effectively reduced. In order to reduce the high inrush current and voltage sag owing to the SBSs of large capacity inductive loads within a power network, a novel hybrid sequential start control system is proposed, implemented on embedded systems, and evaluated with a testbed in this study. From the experimental and simulation results of the proposed control system, the inrush current could be effectively restricted below the maximum current capacity of a power distributing board. Moreover, with the proposed system, power cost typically dictated by the peak power consumption can be fairly reduced, and the quality of the power system connected to the inductive loads can be efficiently increased.

Background P2Y10, along with GPR34 and GPR174, is a G protein-coupled receptor that is activated by an endogenous lipid mediator lysophosphatidylserine (LysoPS). Its expression pattern and its function are completely unknown. We have previously shown that P2Y10 is one of the highly up-regulated genes at the late differentiation stage during in vitro eosinophilopoiesis. Objective We explored the expression and functions of P2Y10 in human cord blood (CB)-derived and peripheral blood (PB) eosinophils. Methods Real-time PCR, FACS, Western blot, ELISA, and chemotaxis assays were performed to determine the expression and function of P2Y10. Results As CB cells differentiated towards eosinophils, P2Y10 mRNA and protein were abundantly expressed. P2Y10 was the most highly expressed in the granulocytes from PB, to a lesser extent in monocytes, and least in lymphocytes. Further fractionation of granulocytes revealed that eosinophils express P2Y10 much more strongly than do neutrophils. PB eosinophils solely expressed P2Y10 among the three LysoPS receptors, while PB neutrophils expressed the three at comparable levels. LysoPS activated both CB and PB eosinophils to induce a robust ERK phosphorylation. Importantly, LysoPS was capable of triggering degranulation of ECP in PB eosinophils. This response was significantly reduced by pharmacological inhibitors of TNF-alpha-converting enzyme (TACE), epidermal growth factor receptor (EGFR), and ERK1/2, which were known to be required in P2Y10-mediated signalling pathways. However, LysoPS had no effect on chemotaxis, differentiation, or eosinophil survival. Conclusions and clinical relevance LysoPS provokes eosinophil degranulation through P2Y10. Therefore, P2Y10 is a potential therapeutic target to control eosinophil-associated diseases.

As the pattern size is cross to virus and molecular sizes, the fabrication cost becomes important. Advantages of the block copolymer lithography (BCPL) through the nanoimprint lithography (NIL) are no diffraction limits, simple and cheap process, and complementary for each of major draw- backs. In this paper, the directed self-assembly lithography of BCP with NIL is successfully modeled and simulated by using the Navier-Stokes equation for the BCP filling process, the multi-thin layer method and the Dill's equation for the UV exposure process, and the self-consistent field theory (SCFT) for the self-assemble process. The impact of the simulation parameters on the pattern formation is discussed and analyzed by using the response surface methodology (RSM).

With the extreme ultraviolet (EUV) lithography, the performance limit of chemically amplified resists has recently been extended to 16-and 11-nm nodes. However, the line edge roughness (LER) and the line width roughness (LWR) are not reduced automatically with this performance extension. In this paper, to investigate the impacts of the EUVL mask and the EUVL exposure process on LER, EUVL is modeled using multilayer-thin-film theory for the mask structure and the Monte Carlo (MC) method for the exposure process. Simulation results demonstrate how LERs of the mask transfer to the resist and the exposure process develops the resist LERs.

The family of ISO/IEEE11073 standards is the basis of the e-health system and provides interoperability for personal health devices. In the early stage of e-health business, it was expected that people would use a health device individually. In this case, a measurement datum was episodically acquired and generally transmitted for one person at a time. Recently, a health device is expected to be used by multiple people, and large amounts of measurement data are gathered in a short time interval. In addition, mobile health devices have become more popular, so that energy efficient measurement data transmission is required, to prolong the use of a device. In IEEE11073 PHD standards, data transmission is classified into three different types: immediate individual transfer, small block transfer, and large block transfer. The large block transfer using PM-store concept provides efficient transmission. However, an existing PM-store has problem when a device is used by multiple people. To address the defined problem, a modified PM-segment that is in compliance with 11073 standards is proposed in this paper. In particular, the proposed PM-segment is designed to minimize the additional complexity of an agent instead of a manager and it is interoperable with the existing manager. The proposed PM-segment shows better performance than the existing PM-segment, in terms of memory requirements and expected queue time. Also, performance comparison among the three transfers is performed in regard to the delay time and communication power consumption points of view.

For future semiconductor device scaling, self-assembly, directed self-assembly (DSA) of block copolymers (BCPs), is a promising method with simplified processing conditions; however, critical challenge is defect control for fine pattern. Electric field is a method for the defect control. In this paper, for electric field effects to jog defects, the electric field induced self-assembled patterns is modeled and simulated by using the Monte Carlo method of dielectric polymers, the self-consistent-field theory (SCFT), and the Navier-Stokes equation. Electric field effects are quantified by using defect degree. Defective patterns are forced to undergo a phase transition to lamellar phase under electric field. For the high electric field, the excess free energy for the defect-free state becomes small. Simulation results can help to optimize electric field and process time in terms of defect area.

Directed self-assembly (DSA) of block copolymers (BCPs) has become an intense field of study as a complementary technique to conventional lithography for 1×-nm semiconductor patterning. DSA contact hole (C/H) shrinking is a possible implemental technique in the DSA process. In this paper, a DSA C/H shrinking is fully modeled and simulated by using a self-consistent field theory (SCFT). Simulation results show good agreement with experiment results. In terms of this simulation, the potential of DSA C/H shrinking with thermal reflow is integrated into the conventional CMOS lithography process in order to achieve high resolution and pattern density multiplication at a low cost. The optical proximity correction (OPC) of DSA C/H shrinking due to prepattern C/H and pitch can increase process window for DSA C/H shrinking.

Since the diffraction limit of Rayleigh criterion hardly creates finer features, the development for the quantum lithography of entangled photons, one of technologies beyond the diffraction limit, is a key merit without the shorter wavelength source tool. In the arbitrary pattern formation for the commercialization of this lithography, however, this quantum lithography is required to implement mask patterns and the conventional optical lithography. In this paper, for the quantum lithography of entangled photons, collective behavior of N-photon entangled states is modeled and simulated to show the effect of photon entangled states for 3-dimensional arbitrary pattern formation by using the rigorous coupled wave analysis (RCWA) and Kirchhoff analysis. For the enhanced resolution from the point of view that the de Broglie wavelength of a quantum state comprised of two entangled photons is half the classical wavelength associated with either photon, simulation results of entangled photons are similar to those of short wavelengths. However, both of simulation results show that the resolution of entangled photons is better than those of the shorter wavelengths. Simulation results can predict realistic better performance of entangled photons.

We propose a control system consisted of TRIAC PWM module and sequential start control system attenuating voltage-dip and inrush current caused by starting of inductive load network. To minimize the high voltage-dip and inrush current induced from a large capacity inductive load, we developed a TRIAC PWM module. And we also developed a sequential start control system preventing simultaneous starting of the inductive loads within a same power network. According to the experimental results with the proposed control system, the voltage-dip and inrush current could be effectively attenuated such that they can meet the related international standards and resolve the issues associated with simultaneous starting of multiple inductive loads. By employing this system, power cost usually implemented by the estimation of peak power consumption can be reduced and the power quality of a power distribution system connected to the inductive load network can be stabilized efficiently.

Semiconductor manufacturing depends on optical lithography. The most basic parameters of the photolithography technique are the resolution and the cost. As the wavelength becomes shorter, the light source and optics become more complex and expensive. The litho-cure-litho-etch (LCLE) process, which is composed of two lithography processes (litho 1 and litho 2) and an intermediate curing step, can reduce the number of process steps and the cost compared to the litho-etch-lithoetch (LELE) process. In this research, the post-exposure bake (PEB) of the LCLE process was investigated. Advanced modeling techniques for the PEB process and the curing process are introduced to explore pattern interactions between the two lithography processes in the LCLE process. Using the simulation results, we discuss the impacts of the depletion of the acid concentration in the vicinity of cured patterns and of acid/quencher diffusion effects on the pattern formation of the LCLE process.

In this paper, we perform a complexity analysis for implementation of the ISO/IEEE 11073 Personal Health Device (PHD) standards in order to check the required system resources when ISO/IEEE 11073 PHD standards are implemented on the embedded system. Base on the implemented programs complying the PHD standards for a weighing scale, a blood pressure monitor, and a glucose meter among the various personal health devices, we make a pseudo-code. And then from the two different points of view such as program memory space and data memory space, we make a complexity analysis model. Because system resources or capability are strongly restricted in the personal health devices, our research work is very useful to estimate the required system resources.

The directed self-assembly (DSA) technology of block copolymers is a candidate for next-generation lithography. The computation model of this lithography can assist in overcoming its challenges. In this paper, a template-assisted self-assembly (DSA graphoepitaxy) is modeled and simulated in a molecular scale to reduce the process complexity. For a full simulation, the template fabrication and DSA process are modeled and simulated to evaluate the impact of the process parameters on the pattern profile. Simulation results similar to the experimental results allow the prediction of the self-assembled patterns of the confined block polymers.

Photoresist lithography has been applied to the fabrication of micro/nano devices, such as microfluidic structures, quantum dots, and photonic devices, in MEMS (micro-electro mechanical systems) and NEMS (nano-electro-mechanical systems). In particular, nano devices can be expected to present different physical phenomena due to their three-dimensional (3D) structure. The flexible 3D micro/nano fabrication technique and its process simulation have become among the major topics needed to understand nano-mechanical phenomena. For this purpose, the moving-mask technology and the lithography processes for the positive- and negative-tone photoresists were modeled. The validity of the simulation of the proposed 3D nano/microstructuring was successfully confirmed by comparing the experiment results and the simulated results. Hence, the developed model and the simulation can present and optimize photoresist characteristics and lithography process conditions due to the various 3D nano/microstructures. They could be help in the understanding of nanomaterial and mechanical phenomena.

Because photoresist has the uncertain triangle relation among the higher resolution, the lower line-edge-roughness (LER) (or line-with-roughness (LWR)), and the improved sensitivity, for below 20-nm pattern formation, this relation makes hard to use the optical lithography. Directed self-assembly (DSA) has been considered as a potential candidate to extend the resolution limit of the optical lithography. The effects of DSA processing and DSA molecular geometry on LER should be well understood in order to meet the ITRS lithographic specifications. In this paper, for the optical lithography and the block copolymer (BCP) lithography such as graphoepitaxy, LER behavior is modeled by the stochastic methods such as the Monte Carlo method and the dissipative particle dynamics (DPD) method. Simulation results explain that the LER of the BCP lithography is smaller than that of the optical lithography because of a self-healing capability of block copolymers.

Because top-down approaches, such as the extreme ultraviolet technique and high-index fluidbased immersion ArF lithography, may cover one or two generations, lithography technology for scaling down feature size to sub-10-nm is becoming more complex. The directed self-assembly technology of block copolymers is one candidate for next-generation lithography. In this paper, a directed self-assembly lithography process for block copolymers is modeled and simulated on a molecular scale to solve the challenges associated with directed self-assembly technology. Sub-10nm patterns can be formed by using precise pattern placement of a conventional ‘top-down’ optical lithography with the well-defined nanostructure and self-healing properties of ‘bottom-up’ block copolymer self-assembly. Simulation results matched the experiment results.

For the feature size scaling down to tens of nanometers, the top-down approaches are getting more severe because the extremely ultra-violet (EUV) technique, the high-index fluid-based immersion ArF lithography, and the double patterning technology (DPT) under development may be cover one or two generations. An alternative technology to extend lithography patterning beyond current resolution limits is to combine the top-down lithography and bottom-up assembly. In this paper, an directed self-assembly lithography process of ''bottom-up'' block copolymer self-assembly, is modeled and simulated in molecular-scale. Impacts of block polymer components on pattern formation are analyzed and discussed.

Photoresist lithography has been applied in MEMS (micro electro mechanical systems). A flexible 3D (three-dimensional) micro/nano fabrication technique and its process simulation tool are required for 3D MEMS. This paper presents an UV (ultraviolet) lithography process simulation for the formation of an embedded micro/nano fluidic channel in a negative-tone photoresist. For this purpose, the moving-mask technology is modeled. The simulation algorithm of the nanolithography is applied for the micro-lithography. The validity of the simulation for the proposed 3D microstructuring is successfully confirmed by a comparison between the experimental and the simulated results. Hence, modeling and simulation for the formation of various patterns of micro/nano fluidic channels in a negative-tone photoresist can be used to provide the photoresist characteristics and to optimize the lithography process conditions.

For the purpose of compromising hosts, attackers including infected hosts initially perform a portscan using IP addresses in order to find vulnerable hosts. Considerable research related to portscan detection has been done and many algorithms have been proposed and implemented in the network intrusion detection system (NIDS). In order to distinguish portscanners from remote hosts, most portscan detection algorithms use a fixed threshold that is manually managed by the network manager. Because the threshold is a constant, even though the network environment or the characteristics of traffic can change, many false positives and false negatives are generated by NIDS. This reduces the efficiency of NIDS and imposes a high processing burden on a network management system (NMS). In this paper, in order to address this problem, we propose an automatic portscan detection system using an fast increase slow decrease (FISD) scheme, that will automatically and adaptively set the threshold based on statistical data for traffic during prior time periods. In particular, we focus on reducing false positives rather than false negatives, while the threshold is adaptively set within a range between minimum and maximum values. We also propose a new portscan detection algorithm, rate of increase in the number of failed connection request (RINF), which is much more suitable for our system and shows better performance than other existing algorithms. In terms of the implementation, we compare our scheme with other two simple threshold estimation methods for an adaptive threshold setting scheme. Also, we compare our detection algorithm with other three existing approaches for portscan detection using a real traffic trace. In summary, we show that FISD results in less false positives than other schemes and RINF can fast and accurately detect portscanners. We also show that the proposed system, including our scheme and algorithm, provides good performance in terms of the rate of false positives.

Authors thank Kiyoshi Minemura in Aichi University of Technology and Tomomi Uchiyama in Nagoya University, Japan for their helpful researches. This research was supported by the MIC(Ministry of Information and Communication), Korea, under the ITRC (Information Technology Research Center) support program supervised by the IITA(Institute of Information Technology Advancement) (IITA-2008-C109008010030).