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Devices based on AlGaN/GaN heterostructures, for example, Schottky barrier diodes (SBDs) and high electron mobility transistors (HEMTs), have been intensively investigated for applications to high-frequency and high-power areas. Presently, the substrates widely distributed are AlGaN/GaN on SiC for its high performance in radio frequency (RF) applications, for examples high cutoff frequency (fT) or high maximum oscillation frequency (fmax), and AlGaN/GaN on Si for its high power performance, for examples high breakdown voltage or high voltage operation. Chemical vapor deposition (CVD) diamond substrates have a thermal conductivity of 12 W/cm·K, and this is a remarkable point because HEMTs or SBDs on AlGaN/GaN on CVD diamonds are one of the promising alternatives for power and RF applications. In comparison, the thermal conductivity of AlGaN/GaN on a sapphire substrate is 0.33 W/cm·K while that of AlGaN/GaN on a Si substrate is 1.3 W/cm·K and that of AlGaN/GaN on a SiC substrate is 4.9 W/cm·K. In this work, we fabricated SBDs with a 137 mm Schottky channel length on AlGaN/GaN on Si and also on a CVD diamond substrate. We also compared the thermal behaviors of these fabricated large scale SBDs on Si and a CVD diamond substrate.

In this study, an E‐band low‐noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) has been designed using silicon‐germanium 130‐nm bipolar complementary metal‐oxide‐semiconductor technology to suppress unwanted signal gain outside operating frequencies and improve the signal gain and noise figures at operating frequencies. The proposed impedance‐controllable filter has series (Rs) and parallel (Rp) resistors instead of a conventional inductor‐capacitor (L‐C) filter without any resistor in an interstage matching circuit. Using the impedance‐controllable filter instead of the conventional L‐C filter, the unwanted high signal gains of the designed E‐band LNA at frequencies of 54 GHz to 57 GHz are suppressed by 8 dB to 12 dB from 24 dB to 26 dB to 12 dB to 18 dB. The small‐signal gain S21 at the operating frequencies of 70 GHz to 95 GHz are only decreased by 1.4 dB to 2.4 dB from 21.6 dB to 25.4 dB to 19.2 dB to 24.0 dB. The fabricated E‐band LNA MMIC with the proposed filter has a measured S21 of 16 dB to 21 dB, input matching (S11) of –14 dB to –5 dB, and output matching (S22) of –19 dB to –4 dB at E‐band operating frequencies of 70 GHz to 95 GHz.

GaN-based metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) are intensively investigated for high power, high frequency [1] and aerospace application [2] due to its wide bandgap, high breakdown field, and high carrier density and mobility at AlGaN/GaN interface [3]. For the demonstration of high power radio-frequency and aerospace applicable devices, the passivation layer introduced on the AlGaN barrier plays significant roles for the enhancement of the frequency characteristics [4] and proton radiation hardness [2]. From this point of view, diverse passivation materials and systems have been researched in GaN-based MIS-HEMTs [2, 5, 6]. However, the detailed impact of passivation layer on the device properties and the immunity to the proton irradiation is not clear in many cases, so far. In this work, we have prepared the SiN/Al2O3 bi-layer passivation system to study the impact of mechanical stress introduced by the passivation layer deposition on the device performance (Sample A: SiN = 20 nm, Sample B: SiN/Al2O3 = 5/15 nm, Sample C: SiN/Al2O3 = 5/35 nm). The correlation between the induced mechanical stress on the GaN channel and carrier transport properties in terms of carrier concentration and mobility at hetero-interface in GaN-based MIS-HEMTs was examined. The Al2O3 layer deposited by the atomic layer deposition (ALD) provided the tensile stress which compensated the compressive stress generated by the SiN layer deposited by the plasma enhanced chemical vapor deposition (PEDVD). When the compressive stress reduces through the deposition of Al2O3 on the SiN layer, the carrier concentration and mobility at hetero-interface were increased. With decreasing compressive stress, the piezoelectric field enlarges that enhances polarization charges [7] and carrier concentration. The carrier mobility was also improved with diminishing compressive stress since the mean free path related to the lattice scattering is decreased, enhancing transconductance as well. As a result, GaN-based MIS-HEMTs with slight tensile stress in Sample C exhibits the best device performance. The proton radiation hardness according to the passivation system was studied for various passivation systems. When we compared the device characteristics before and after the proton irradiation with the fluences of 1013 and 1014 cm-2 at an energy of 5 MeV, the device properties such as threshold voltage, drain current, and transconductance were changed. After the proton radiation, the threshold voltage was negatively shifted that is identical characteristics to the metal-oxide-semiconductor device [8], rather than GaN-based HEMTs [9] as relatively large amount of holes was trapped inside of the passivation system due to the lower hole mobility than electron. The alternation of the device characteristics depended on the passivation system. The ALD-deposited Al2O3 showed superior quality compared to the PECVD-deposited SiN that was revealed by the pulse-mode stress measurements. Therefore, the hole trap sites generated by the proton irradiation and located interior of the passivation system are less when the Al2O3 layer was employed as a passivation layer, showing smaller threshold voltage shift. Moreover, the carrier mobility deterioration caused by the Coulomb scattering between the trapped holes inside the passivation system and carriers at hetero-interface was improved with the Al2O3 passivation layer. The drain current and transconductance degradation were improved by applying Al2O3 passivation layer. Our systematic measurement results highlight that the optimized SiN/Al2O3 bi-layer passivation system is promising technique for the enhancement of the device performance and improvement of proton radiation hardness in GaN-based MIS-HEMTs. Acknowledgement This work was supported by the National Research Council of Science & Technology (NST) grant by the Korean government (MSIP) (No. CRC-19-02-ETRI). References [1] V. Kummer, W. Lu, R. Schwindt, et al., IEEE Electron Device Lett., vol. 23(8), pp. 455-457, 2002. [2] S. Ahn, B.-J. Kim, Y,-H. Lin, et al., J. Vac. Sci. Technol. B. vol. 34(5), 051202, 2016. [3] T. Palacios, A. Chakraborty, S. Rajan, et al., IEEE Electron. Device Lett., vol 26(11), pp. 781-783, 2005. [4] P. D. Ye, B. Yang, K. K. Ng, et al., Appl. Phys. Lett., vol. 86, 063501, 2005. [5] M. A. Khan, X. Hu, G. Simin, et al., IEEE Electron Device Lett., vol. 21(2), 99. 63-65, 2000. [6] K. Balachander, S. Arulkumaran, H. Ishikawa, et al., Phys. Status Solidi A., vol. 202(2), R16-R18, 2005. [7] S. Joglekar, M. Azize, E. J. Jones, et al., IEEE Trans. on Electron Devices, vol. 63(1), pp. 318-325, 2015. [8] K. Hayama, K. Takakura, H. Ohyama, et al., IEEE Trans. Nucl. Sci., vol 51(6), pp. 3795-3800, 2004. [9] X. Hu, A. P. Karmarkar, B. Jun, IEEE Trans. Nucl. Sci., vol 50(6), pp. 1791-1796, 2003. Figure 1

We investigate DC characteristics of AlGaN/GaN high-electron mobility transistors by using a source-bridged field plate and additional bottom plate (BP) structure. The analysis of experimental data was performed with a two-dimensional simulator. Source connected BP structure stabilized threshold voltage and transconductance regardless of various drain voltages. The effect of BP location was also analyzed, which had optimal DC values because of the dependence of breakdown voltage and drain current of the device on BP position between gate and drain. Finally, the optimum distance of 0.8 μm from drain side gate head edge to BP was achieved for optimum DC characteristics and the highest breakdown voltage of 341 V.

AlGaN/GaN heterostructures were successfully grown with the AlIn(Ga)N back barrier at 900 °C. However, the atomic composition of the AlIn(Ga)N layer was strongly dependent on the growth pressure, which resulted in a different lattice constant of the layer. The AlIn(Ga)N back barrier grown at 400 torr was almost lattice-matched to GaN layer. The AlGaN/GaN heterostructures with 10 and 15 nm-thick AlIn(Ga)N back barrier exhibited improved 2-DEG properties, compared to those of the conventional AlGaN/GaN heterostructure without the back barrier. The high electron mobility transistors (HEMTs) fabricated on the AlGaN/GaN heterostructure with a 15 nm-thick AlIn(Ga)N back barrier exhibited a very low off-state leakage current of ∼2 × 10−7 A/mm which is about 1 order lower in magnitude than the value of the device without the back barrier. The AlIn(Ga)N back barrier is a promising candidate as an alternative to conventional AlGaN and InGaN back barrier.

An enhancement-mode AlGaN/GaN metal-insulator-semiconductor high-electron- mobility-transistor was fabricated using a recess gate and CF4 plasma treatment to investigate its reliable applicability to high-power devices and circuits. The fluorinated-gate device showed hysteresis during the DC current-voltage measurement, and the polarity and magnitude of hysteresis depend on the drain voltage. The hysteresis phenomenon is due to the electron trapping at the Al2O3/AlGaN interface and charging times longer than milliseconds were obtained by pulse I-V measurement. In addition, the subthreshold slope of the fluorinated-gate device was increased after the positive gate bias stress because of the two-dimensional electron gas reduction by ionized fluorine. Our systematic observation revealed that the effect of fluorine ions should be considered for the design of AlGaN/GaN power circuits.

The device performance deterioration mechanism caused by the total ionizing dose effect after the &gamma, ray irradiation was investigated in GaN-based metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) for a 5 nm-thick SiN and HfO2 gate dielectric layer. The &gamma, ray radiation hardness according to the gate dielectric layer was also compared between the two different GaN-based MIS-HEMTs. Although HfO2 has exhibited strong tolerance to the total ionizing dose effect in Si-based devices, there is no detail report of the &gamma, ray radiation effects in GaN-based MIS-HEMTs employing a HfO2 gate dielectric layer. The pulsed-mode stress measurement results and carrier mobility behavior revealed that the device properties not only have direct current (DC) characteristics, but radio frequency (RF) performance has also been mostly degraded by the deterioration of the gate dielectric quality and the trapped charges inside the gate insulator. We also figured out that the immunity to the &gamma, ray radiation was improved when HfO2 was employed instead of SiN as a gate dielectric layer due to its stronger endurance to the &gamma, ray irradiation. Our results highlight that the application of a gate insulator that shows superior immunity to the &gamma, ray irradiation is a crucial factor for the improvement of the total ionizing dose effect in GaN-based MIS-HEMTs.

In this study, we investigated the operational characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) by applying the copper-filled trench and via structures for improved heat dissipation. Therefore, we used a basic T-gate HEMT device to construct the thermal structures. To identify the heat flow across the device structure, a thermal conductivity model and the heat transfer properties corresponding to the GaN, SiC, and Cu materials were applied. Initially, we simulated the direct current (DC) characteristics of a basic GaN on SiC HEMT to confirm the self-heating effect on AlGaN/GaN HEMT. Then, to verify the heat sink effect of the copper-filled thermal structures, we compared the DC characteristics such as the threshold voltage, transconductance, saturation current, and breakdown voltage. Finally, we estimated and compared the lattice temperature of a two-dimensional electron gas channel, the vertical lattice temperature near the drain-side gate head edge, and the transient thermal analysis for the copper-filled thermal trench and via structures. Through this study, we could optimize the operational characteristics of the device by applying an effective heat dissipation structure to the AlGaN/GaN HEMT.

In this paper, we investigated characteristics of AlGaN/GaN high-electron mobility transistors (HEMTs) with high resistive buffer structure consisted of periodically carbon-doped (PCD) GaN buffer layer and AlGaN back barrier layer. The PCD structure was proposed for reducing undesirable trapping effects, which resulted in effective suppression of the current collapse compared to that in conventional carbon buffer structure. To further improve the dynamic performances of the device and to increase the electron confinement of the 2-D electron gas (2-DEG) channel, AlGaN back barrier was inserted between the GaN channel and the PCD buffer layer, which results in greatly improved current collapse with slightly improved 2-DEG mobility compared to those of the device without back barrier. The OFF-state leakage current of the device with back-barrier is about 2 orders lower in magnitude than that of device without back barrier, which leads to the breakdown voltage of 2 kV and figure of merit of 2.27 GV2Ω-1cm-2 for the device with LGD of 10 μm, one of the highest values ever reported for the GaN-based HEMTs.

This study investigates metal-insulator-semiconductor high electron mobility transistor DC characteristics with different gate dielectric layer compositions and thicknesses, and lattice temperature effects on gate leakage current by using a two-dimensional simulation. We first compared electrical properties, including threshold voltage, transconductance, and gate leakage current with the self-heating effect, by applying a single Si3N4 dielectric layer. We then employed different Al2O3 dielectric layer thicknesses on top of the Si3N4, and also investigated lattice temperature across a two-dimensional electron gas channel layer with various dielectric layer compositions to verify the thermal effect on gate leakage current. Gate leakage current was significantly reduced as the dielectric layer was added, and further decreased for a 15-nm thick Al2O3 on a 5-nm Si3N4 structure. Although the gate leakage current increased as Al2O3 thickness increased to 35 nm, the breakdown voltage was improved.

A short-circuited capacitor in a matching circuit between the third and fourth stages of an LNA has been used to reduce an unwanted small-signal gain at 50∼70 GHz and to flatten signal gain at an operating frequency of 77∼97 GHz. The designed LNA shows a small-signal gain of 21.2 to 22.2 dB, a gain flatness of 1 dB, a noise figure of 5.7 to 6.9 dB, an input-reflection coefficient of −14 to −7 dB, an output-reflection coefficient of −26 to −3 dB, an isolation of −51 to −44 dB, and an 1 dB bandwidth of 20 GHz over a frequency range of 76.6∼96.6 GHz. And the simulated power characteristic of the designed LNA present an 1 dB compression power, P IdB , of −3 to −1 dBm over a frequency range of 76.6∼96.6 GHz.

In this study, a high-performance AlGaN/GaN high electron mobility transistor (HEMT) is presented to improve its electrical operation by employing an inner field-plate (IFP) structure. Prior to the IFP structure analysis, we compared the measured and simulated direct current characteristics of the fabricated two-finger conventional T-shaped gate HEMTs. Then, the AlGaN/GaN HEMT with a drain-side field plate (FP) structure was suggested to enhance the breakdown voltage characteristics. The maximum breakdown voltage recorded with a 0.8 &mu, m stretched FP structure was 669 V. Finally, the IFP structure was interfaced with the gate head of the device to compensate the radio frequency characteristics, choosing the optimum length of the drain-side FP structure. Compared to the 0.8 &mu, m stretched FP structure, the IFP structure showed improved frequency characteristics with minimal difference to the breakdown voltage. The frequency variation caused by changing the passivation thickness was also analyzed, and the optimum thickness was identified. Thus, IFP AlGaN/GaN HEMT is a promising candidate for high-power and high-frequency applications.

International audience; Normally-off AlGaN/GaN-based MOS-HEMT has been fabricated by utilizing damage-free self-terminating tetramethyl ammonium hydroxide (TMAH) recess etching. The device exhibited a threshold voltage of +2.0 V with good uniformity, extremely small hysteresis of ∼20 mV, and maximum drain current of 210 mA/mm. The device also exhibited excellent off-state performances, such as breakdown voltage of ∼800 V with off-state leakage current as low as ∼10−12 A and high on/off current ratio (Ion/Ioff) of 1010. These excellent device performances are believed to be due to the high quality recessed surface, provided by the simple self-terminating TMAH etching. Previous article in issue

SiC substrates and GaN/AlGaN epitaxial layers were etched by using an inductively-coupled plasma (ICP) in order to electrically connect the backside metal to the source electrode pads on the front-side of an AlGaN/GaN high-electron-mobility transistor (HEMT) device. The shape of an etched via hole was a tapered cylinder with a larger diameter at the entrance. The surfaces on the bottom and a wall of the via hole were very smooth in comparison with the results on the most recently published papers. Through optimization of the etching conditions, the etch-stops on the GaN epi-layer and on the source pad were successfully completed. The electrical properties of the device with the backside via holes were not critically different from those of the device without the backside via holes. In this paper, the fabrication process and the electrical properties of AlGaN/GaN HEMTs on SiC substrates with taper-shaped backside via holes are reported for the first time.

We report the fabrication and DC and microwave characteristics of 0.5 μm AlGaN/GaN high electron mobility transistors using double plasma treatment process. Silicon nitride layers 700 and 150 A thick were deposited by plasma-enhanced chemical vapor deposition at 260 °C to protect the device and to define the gate footprint. The double plasma process was carried out by two different etching techniques to obtain enhancement-mode AlGaN/GaN high electron mobility transistors with 0.5 μm gate lengths. The enhancement-mode AlGaN/GaN high electron mobility transistor was prepared in parallel to the depletion-mode AlGaN/GaN high electron mobility transistor device on one wafer. Completed double plasma treated 0.5 μm AlGaN/GaN high electron mobility transistor devices fabricated by dry etching exhibited a peak transconductance, gm, of 330 mS/mm, a breakdown voltage of 115 V, a current-gain cutoff frequency ( f T ) of 18 GHz, and a maximum oscillation frequency ( f max ) of 66 GHz.

In this article, 60 GHz MMIC down-conversion mixers for a 60 GHz communication system are designed and fabricated on-chip using a 0.12 μm GaAs PHEMT process technology with an fT of 78 GHz and fmax of 190 GHz.The characteristics of a 60 GHz monolithic cascode mixer with an open stub microstrip line are compared with those of a 60 GHz monolithic cascode mixer without an open stub microstrip line, which are integrated on-chip including matching and bias circuits. The 60 GHz monolithic cascode mixer with an open stub microstrip line measured at RF 60 GHz show a conversion gain of −16 dB, LO to RF isolation of 21.5 dB, and LO to IF isolation of 40.5 dB. Especially in the case of the mixer, the LO to IF isolation characteristic is much better than that of the 60 GHz monolithic cascode mixer without an open stub microstrip line. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1341–1345, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25191

The variation of mixed-mode reliability degradation with emitter scaling in silicon–germanium heterojunction bipolar transistors was investigated. While base current density (JB) after reverse emitter–base stress increased with increasing perimeter-to-area (P/A) ratio, JB exhibited a reverse behavior in the case of mixed-mode stress. In addition, the up and down variation of JB was observed with increasing stress time in some devices of very small P/A ratios. It is considered that these phenomena resulted from self-heating effect depending on device size.

This paper presents a new method of forming a Si/SiGe dual channel on a Si 0.8 Ge 0.2 virtual substrate. Generally, in a CMOS process using a Si/SiGe dual channel, due to several processes involving ion-implantation, annealing and dry-etching after the deposition of the Si/SiGe dual channel, the surface can be damaged, leading to reduced electrical properties. However, if the dual channel is formed during a specific stage of the CMOS process, the defects of the dual channel can be reduced and the thermal stability will be excellent. Therefore, in this paper, a method for minimizing the defects of the dual channel is presented. This method uses the segregation of the Ge in the oxidation process of a SiGe. A Si/SiGe dual channel formed using this method achieved results that were identical to a dual channel deposited using the chemical vapor deposition (CVD) method.

A 28.5-32-GHz fast settling multichannel frequency synthesizer is implemented in 0.25-mum SiGe : C BiCMOS process technology for 60-GHz wireless personal area network (WPAN) applications. The phase-locked loop (PLL) synthesizes carrier frequencies between 28.5-32 GHz in step of 500 MHz, and settles in approximately 327 ns. The proposed PLL can be employed as a frequency source providing eight channels of frequency hopping carriers for 60-GHz WPAN radio. To generate eight channels of carriers, an integer-N PLL with 125-MHz reference frequency is implemented, and a programmable divider with all differential current-steering circuits is designed. The programmable divider reliably provides divide ratios of 114-128 at 15 GHz. To achieve eight channels of carriers at a challenging frequency of 30 GHz, a push-push voltage-controlled oscillator is employed using a Wilkinson power combiner. The PLL consumes 115 mA at 2.5 V and achieves phase noise of -81 dBc/Hz at 1-MHz offset measured from 32-GHz push-push carrier.

The resistance variation of the silicon–germanium (SiGe) thin film resistor caused by the fabrication process of SiGe integrated circuits (ICs) was investigated. The SiGe resistor and the Si resistor were made of the thin films identical with the p-type SiGe base layer and the n-type Si emitter layer of the SiGe hetero-junction bipolar transistor, respectively. The range of the resistance value of the SiGe resistor was much larger than that of the Si resistor, and an abnormally high resistance of the SiGe resistor was often observed. Ti–B precipitates and Ti(Si1−x Ge x )2 protrusions were created as the result of the Ti silicidation of the p-type SiGe layer, whereas no precipitates and protrusions were generated in the case of the n-type Si layer. It was confirmed by scanning electron microscopy that the nonuniform resistance of the SiGe resistor was induced by the removal of the protrusions and underlying field oxides in the contact window. Resistance uniformity of the SiGe resistor was much improved by increasing the contact size. The simulation result of the detrimental influence of the resistance change on ICs indicated that the fabrication process and the structure of the thin film resistor should be optimized for enhancing IC reliability.

SiGe integrated circuits are being used in the field of high-speed wire/wireless communications and microwave systems due to the RF/high-speed analog characteristics and the easiness in the fabrication. Reducing the resistance variation in SiGe thin film resistors results in enhancing the reliability of integrated circuits. In this paper, we investigate the causes that generate the resistance nonuniformity after the silicon-based thin film resistor was fabricated, and consider the counter plan against that. Because the Ti-B precipitate, which formed during the silicide process of the SiGe thin film resistor, gives rise to the nonuniformity of SiGe resistors, the boron ions should be implanted as many as possible. In addition, the resistance deviation increases as the size of the contact hole that interconnects the SiGe resistor and the metal line decreases. Therefore, the size of the contact hole must be enlarged in order to reduce the resistance deviation.

The effect of the electrical resistivity of a silicon–germanium (SiGe) thin film on the phase transition in a GeSbTe (GST) chalcogenide alloy and the manufacturing aspect of the fabrication process of a chalcogenide memory device employing the SiGe film as bottom electrodes were investigated. While p-type SiGe bottom electrodes were formed using in situ doping techniques, n-type ones could be made in a different manner where phosphorus atoms diffused from highly doped silicon underlayers to undoped SiGe films. The p–n heterojunction did not form between the p-type GST and n-type SiGe layers, and the semiconduction type of the SiGe alloys did not influence the memory device switching. It was confirmed that an optimum resistivity value existed for memory operation in spite of proportionality of Joule heating to electrical resistivity. The very high resistivity of the SiGe film had no effect on the reduction of reset current, which might result from the resistance decrease of the SiGe alloy at high temperatures.

The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on-chip 1 to 6 GHz up-conversion and 1 to 8 GHz down-conversion mixers using a 0.8 mm SiGe hetero-junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up-conversion mixer was implemented on-chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up-conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down-conversion mixer was implemented on-chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down-conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.

In this paper, we propose two LC voltage-controlled oscillators (VCOs) that improve both phase noise and tuning range. With both 1/ƒ induced low-frequency noise and low-frequency thermal noise around DC or around harmonics suppressed significantly by the employment of a current-current negative feedback (CCNF) loop, the phase noise in the CCNF LC VCO has been improved by about 10 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise of the CCNF VCO was measured as -112 dBc/Hz at 6 MHz offset from 5.5 GHz carrier frequency. Also, we present a bandwidth-enhanced LC VCO whose tuning range has been increased about 250 % by connecting the varactor to the bases of the crosscoupled pair. The phase noise of the bandwidth-enhanced LC-tank VCO has been improved by about 6 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise reduction has been achieved because the DCdecoupling capacitor Cc prevents the output commonmode level from modulating the varactor bias point, and the signal power increases in the LC-tank resonator. The bandwidth-enhanced LC VCO represents a 12 % bandwidth and phase noise of -108 dBc/Hz at 6 MHz offset.

Modulation-doped Si0.8Ge0.2 pMOSFETs have been successfully fabricated through a well-controlled boron δ-doping (doses of 1 × 1012–5 × 1012 cm−2) by reduced pressure chemical vapor deposition, and their DC and RF characteristics have been investigated. It is seen that the modulation doping, which shifts the hole gas from the Si-cap/Si0.8Ge0.2 interface to the centrum of the Si0.8Ge0.2 quantum well, effectively improves the device’s transconductance (gm), driving-current, cut-off frequency (fT), and gate-voltage swing, without a degradation in devices’ turn-off characteristics. In addition, a reduction in NFmin is observed in the modulation-doped Si0.8Ge0.2 pMOSFETs, responsible for the increased gm and the reduced gate capacitance. The 1/f noise in Si0.8Ge0.2 pMOSFETs is also proven to be lower than that of the Si control, regardless of modulation doping. This device design is well suitable for high-speed and low-noise applications.

This article introduces an 1–12-GHz differential two-stage variable-gain low-noise amplifier (VGLNA) using 0.25-μm SiGe:C BiCMOS commercial process technology for ultra-wideband system.The results of the fabricated monolithic microwave integrated circuit amplifier show 18-dB gain with a 3-dB frequency band of 1.3–11.9 GHz and noise figure of less than 5 dB under the bias condition of 2.5-V supply voltage and 55-mW total dc power consumption. The gain-control range is from −17 dB to +18 dB. The chip size of the manufactured VGLNA is 1.1 × 0.9 mm2 including all testing pads for RF and dc probes. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:1935–1937, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26936

The crystalline quality and ferroelectricity of the Pb(Zr,Ti)O3 (PZT) films deposited on the metallic LaNiO3 (LNO) and Pt electrodes were comparatively analyzed to investigate the possibility for their application to non-volatile memory devices. LNO thin films were successfully deposited on various substrates by using r.f. magnetron sputtering even at a low temperature ranging from 250 to 500 °C, and the ferroelectric PZT thin films were spin-coated onto the LNO and Pt bottom electrodes. Metallic LNO thin films exhibited [100] orientation irrespective of the substrate species and PZT films coated onto LNO films had highly a- and c-axis orientations, while those with Pt bottom electrode were polycrystalline. PZT films with LNO bottom electrode had smaller grain size and larger dielectric constant compared to those grown on the Pt electrode. The ferroelectric thin films fabricated on LNO bottom electrode displayed an asymmetric D–E hysteresis loop, which was explained by the defect effects formed at the interface. Especially, the LNO/PZT/LNO capacitor was found to significantly improve the polarization fatigue and the effects of the LNO electrodes to the fatigue were discussed.

We have grown an AlIn(Ga)N/GaN heterostructure which is a promising alternative to the AlGaN/GaN heterostructure. The mobility and the carrier concentration of the two-dimensional electron gas (2DEG) formed at the AlIn(Ga)N/GaN heterointerface were strongly dependent on both the growth temperature and pressure. Two optimized growth conditions for the heterostructure with a low sheet resistance less than 300 Ω/sq were obtained by varying the growth temperature and pressure from 750 to 1070 °C and 100 to 300 torr, respectively: (i) AlIn(Ga)N/GaN heterostructure with high 2DEG carrier concentration of 2.4 × 1013 cm−2 with mobility of 1010 cm2 V−1s−1 (grown at 900 °C and 100 torr); (ii) AlIn(Ga)N/GaN heterostructure with high 2DEG mobility of 1910 cm2 V−1s−1 with carrier concentration of 1.13 × 1013 cm−2 (grown at 900 °C and 300 torr). Both structures would be useful for different purpose of device application.

In this letter, a new burst-mode optical receiver with burst detection function is proposed and a single-chip 2.5-Gb/s burst-mode optical receiver has been fabricated using 0.25-μm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The single-chip optical receiver has high sensitivity and wide dynamic range for various classes of power budges required in 10-Gigabit-capable passive optical network (XG-PON1) (2.5-Gb/s upstream and 10-Gb/s downstream data rates). For the 2.5-Gb/s burst-mode data streams, sensitivity and overload were -32 and -4 dBm at a bit-error rate of 10-10 , respectively, resulting in a dynamic range of 28 dB.

The relation between Ti silicidation and base resistance in SiGe hetero-junction bipolar transistors (HBT) was investigated. The Ti layer deposited on the Si/SiGe/Si base converted to Ti silicide during two-step annealing. The thickness of the Ti silicide, which was identified as the Ti(Si1-xGex) phase of uniform composition, abruptly increased over the annealing temperature of 650/850 °C, and as a result it accomplished a very low extrinsic base resistance. The Ti silicidation affected the base resistance of real devices (RB), which was extracted from simulating the electrical data of SiGe HBTs such as I –V curves, forward Gummel plots, forward current gain curves, and s-parameter plots. It was shown that the RB was compatible with the theoretical relation which included the small-signal unity-gain frequency (fT), the maximum oscillation frequency (fmax) and RB. fmax varied more sensitively with RB than fT, which was due to the inherent property of fmax being inversely proportional to √RB. The fmax of the SiGe HBT reached 47.4 GHz when Ti silicidation was performed at the annealing temperature of 650/850 °C. This silicidation condition is thought to be an appropriate temperature for Ti silicidation applicable to SiGe HBT fabrication. © 2001 Kluwer Academic Publishers

In this article, a 60 GHz band down-conversion mixer for 60 GHz wireless personal-area network is designed and fabricated on a chip using 0.25 μm SiGe:C BiCMOS process technology. To design this 60 GHz band mixer, architecture of double-balanced mixer is used, including input and output balun circuits, which are composed of active elements. The results of the fabricated mixer measured between RF 57 and 63 GHz show conversion gain of 12.0–10.7 dB, LO to RF isolation and LO to IF isolation of more than 28 dB, and input P1dB of −17 to −18 dBm. The chip size of the manufactured mixer is 1.3 mm × 0.8 mm. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 3007–3009, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23887

This letter presents a 48-GHz capacitively emitter-degenerated LC voltage controlled oscillator (VCO) with double cross-coupled pair showing higher and lower input capacitance than typical cross-coupled pairs. The phase noise of the proposed LC VCO is measured as 114.5 dBc/Hz at 1 MHz offset from 48 GHz carrier, and a current of 6 mA is drawn in the VCO circuit. The proposed VCO shows an excellent figure of merit of 196 dB.

CdZnTe has been characterized by means of polarization-field hysteresis and current–voltage measurements. The CdZnTe is shown to be ferroelectric with polarization endurance up to 107 poling cycles. The polarization is significantly influenced by free carriers and can be switched by light illumination. The capacitance of CdZnTe consists of ferroelectric and depletion components. On the other hand, electrical conduction in the CdZnTe is modulated by the polarization, leading to hysteresis in the current–voltage characteristics. Writing and reading measurement has shown a reading-current difference of 0.015 mA at a nondestructive voltage for the binary digits.

We present the design and evaluation of a 10-gigabit small form factor pluggable transceiver with a prototype single-chip burst-mode receiver, a signal detection circuit, and a clock-data-recovery device for 2.5 Gbit/s upstream in the ITU-T G.987.2 recommendation.

Sr0.25Ba0.75Nb2O6 (SBN) thin films postannealed at 750 °C for 30 min were epitaxially grown in the [00l] direction on p-type (100) Si substrates by the rf magnetron sputtering method. The capacitance–voltage (C–V) characteristics of Au/SBN/Si capacitors, which depend on postannealing conditions, were measured. The C–V curve of the crystalline SBN film had a hysteresis curve with a clockwise rotation. The memory window and surface charge density calculated from the hysteresis loop are 2.1 V and 85 nC/cm2, respectively. From the data of a deep level transient spectroscopy, the activation energies of major traps in the crystalline SBN film obtained were about Ev+0.26 eV and Ev+0.28 eV, by using the Arrhenius plot.

In this paper, a 60 GHz MMIC down-conversion mixer for 60 GHz WPAN is designed and fabricated on chip using 0.25 mum SiGe:C BiCMOS process technology. This 60 GHz mixer is fully integrated on chip, including active input balun and output balun circuits. The results of the fabricated mixer measured at RF 60 GHz show conversion gain of 10.7 dB, LO to IF isolation and RF to IF isolation of above 30 dB, and input P1dB of -17 dBm. Also, the results of the fabricated mixer measured between RF 57 and 63 GHz show conversion gain of 12.0 ~ 10.7 dB, LO to IF isolation and RF to IF isolation of above 28 dB, and input P1dB of -17 ~ -18 dBm. The chip size of the manufactured mixer is 1.3 mm times 0.8 mm.

In this paper, we present the design of 15-GHz frequency synthesizer for 60-GHz WPAN. The PLL generates 7 channels of output signals with 250 MHz step by using the highspeed programmable divider operating up to 10 GHz. A double cross-coupled LC VCO is used for achieving higher oscillation frequency and shows about 20 % tuning range. The PLL represents phase noise of -88 dBc/Hz at 1 MHz offset from 15.75 GHz and consumes 115 mA at 2.5 V supply voltage. The PLL occupies 0.7 times 0.8 mm2 area and is fabricated using 0.25 mum SiGe:C BiCMOS process technology.

In this paper, a 9.1 to 11.5 GHz four-band PLL is presented. In the proposed PLL, both an improved multi-modulus (MM) divider and an adaptive four-band LC VCO are depicted. The MM divider provides division ratios of 6 to 455 depending on the division mode of the six-mode prescaler. The LC VCO generates four bands of oscillation frequencies covering 9.1-11.6 GHz, including an adaptive cross-coupled MOS array. The cross-coupled MOS array was devised to reduce the area of the capacitor array and compensate for the oscillation power. The PLL achieves phase noises of -98 dBc/Hz from 11.4 GHz and -102 dBc/Hz from 9.61 GHz, at an offset of 980 kHz. The PLL consumes 32 mA at 1.2 V. It was fabricated using 130 nm CMOS process technology.