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The push to reduce size, weight, power, and cost (SWaP-C) has led to the integration of multiple subsystems with different criticality levels onto a single hardware platform. Virtualization has played a crucial role in merging real-time capabilities with complex environments, facilitating the creation of Mixed-Criticality Systems (MCS). However, consolidating various workloads on a single platform often requires shared peripheral access, such as Network Interface Controllers (NICs), among guest Virtual Machines (VMs). VirtIO provides a standardized interface for device para-virtualization, enabling us to deploy device drivers and sharing logic within dedicated VMs. Despite its advantages, VirtIO can introduce latency and reduced throughput due to its reliance on the hypervisor or other VMs for network access, which may exacerbate resource contention and affect time isolation between VMs. Time-Sensitive Networking (TSN) techniques can mitigate these issues by ensuring reliable, low-latency, and deterministic network communication, although its implementation often depends on proprietary Linux-based solutions. In this paper, we present BiRtIO, an infrastructure designed to support a virtual real-time network for VMs on the Bao hypervisor without compromising safety and security. It leverages the VirtIO standard and incorporates TSN mechanisms available in mainline Linux, such as bandwidth limitation, to enhance performance and predictability in a saturated virtualized network. Experiments conducted on the Xilinx ZCU102 high-performance multicore platform demonstrate that our solution achieves performance and predictability levels suitable for real-time workloads on MCS with limited Ethernet ports.

Interrupt controllers are a crucial component in computing platforms. From cloud computing to embedded systems, interrupts and respective controllers enable more efficient management and operation of a platform’s resources. Modern computer architectures incorporate hardware interrupt controllers (e.g., Arm Generic Interrupt Controller (GIC)) that are well-established in modern processors and system-on-chips (SoCs). This article describes our work and research on developing the first open-source RISC-V Advanced Interrupt Architecture (AIA) IP compliant with the recently ratified specification (v1.0). Our contribution is multifold and encompasses architecture, microarchitecture, and evaluation. In particular, we explored alternative designs and microarchitectural enhancements for the implemented IP to cope with mixed-criticality systems (MCS) requirements (e.g., real-time and predictability). From this exploration, we highlight the proposed Integrated Embedded AIA (IE-AIA) design. For each configuration, we assess the impact on hardware utilization and interrupt latency. Due to the increased proliferation of virtualization in MCS, we measured the interrupt latency for a system configuration built atop the Bao hypervisor. At the macro level (i.e., considering both hardware and software), and in particular for a full-blown virtualization stack, we observed a reduction of ~99.5% in the average interrupt latency when comparing the Platform-Level Interrupt Controller (PLIC) IP (full trap and emulation) with the standard AIA IP (no hypervisor mediation due to IMSIC direct interrupt injection). For the IE-AIA, our evaluation focused on the micro view (i.e., hardware only), where we observed that under interference, the IE-AIA IP shows a reduction of $\sim 7\times $ in the average interrupt latency and deterministic behavior compared to the standard AIA implementation. We also provide the first empirical-based comparison between the RISC-V PLIC and the RISC-V AIA. Finally, all artifacts described in this article are open source to foster collaboration and further explore additional design configurations.

Virtualization technology has played a pivotal role in consolidating Mixed-Criticality Systems (MCS) onto a single computing platform. However, not all RISC-V processors present in Commercial Off-The-Shelf (COTS) platforms feature the so called Hypervisor extension, which poses a significant challenge in offering hardware virtualization capabilities in existing RISC-V silicon. This paper introduces HSP-V, a ready-to-run low-level software stack to provide static partitioning on RISC-V COTS platforms lacking hardware virtualization support. HSP-V leverages the Domain feature of the RISC-V Open Source Supervisor Binary Interface (OpenSBI) reference implementation to define partitions protected by the Physical Memory Protection (PMP) unit. Additionally, it provides other capabilities such as interrupt partitioning, direct interrupt injection, cache partitioning, and platform-level isolation for DMA-capable devices. The conducted evaluation assesses the impact of HSP-V on different empirical metrics, including domain boot time, interrupt latency, code size, and execution performance using micro and application benchmarks (LMBench and MiBench, respectively). HSP-V achieves highly deterministic interrupt latency with an average execution time of 457 ns (with a standard deviation of only 22 ns), with essentially zero traps in the Domain execution. In scenarios with cache interference, the HSP-V keeps the performance overhead as low as 0.39% for the best case scenario. Finally, all work described in this article is publicly available and open-sourced for the community to further evolve, port, and evaluate HSP-V in other hardware platforms.

Due to the similar characteristics of chaotic systems and cryptography, public key encryption algorithms based on chaotic systems are worth in-depth research and have high value for the future. Chebyshev polynomials have good properties and are often used in the design of public key algorithms. This paper improves the Bose Multi-Chaotic Public Key Cryptographic Algorithm (BMPKC) by applying Chebyshev polynomials. The proposed algorithm (CMPKC-ki) introduces the selective coefficient ki based on the properties of Chebyshev polynomials, allowing the special functions that need to be negotiated in the original system to be freely and randomly chosen as Chebyshev polynomials, and can also be expanded to m levels. The improved cryptographic algorithm also utilizes chaotic hash functions and logistic mapping to generate pseudo-random sequences and overcomes shortcomings of the Bose algorithm by iteratively iterating the selected Chebyshev polynomials based on the number of 0s or 1s in the pseudo-random sequence, thus providing better security. Analysis and software testing results indicate that this algorithm has strong robustness against brute force attacks, achieving a higher attack time for breaking the private key compared to the CEPKC, BMPKC, and CMPKC algorithms. Compared to the CMPKC algorithm, our proposal algorithm achieves better performance in the encryption and decryption phases. Furthermore, we combine this Multi-Chaotic System Key Exchange Protocol with the Advanced Encryption Standard (AES) algorithm, while providing a demonstration, offering more possibilities for practical applications of this system.

Security is one of the main challenges of the Internet of Things (IoT). IoT devices are mainly powered by low-cost microcontrollers (MCUs) that typically lack basic hardware security mechanisms to separate security-critical applications from less critical components. Recently, Arm has started to release Cortex-M MCUs enhanced with TrustZone technology (i.e., TrustZone-M), a system-wide security solution aiming at providing robust protection for IoT devices. Trusted Execution Environments (TEEs) relying on TrustZone hardware have been perceived as safe havens for securing mobile devices. However, for the past few years, considerable effort has gone into unveiling hundreds of vulnerabilities and proposing a collection of relevant defense techniques to address several issues. While new TEE solutions built on TrustZone-M start flourishing, the lessons gathered from the research community appear to be falling short, as these new systems are trapping into the same pitfalls of the past. In this paper, we present uTango, the first multi-world TEE for modern IoT devices. uTango proposes a novel architecture aiming at tackling the major architectural deficiencies currently affecting TrustZone(-M)-assisted TEEs. In particular, we leverage the very same TrustZone hardware primitives used by dual-world implementations to create multiple and equally secure execution environments within the normal world. We demonstrate the benefits of uTango by conducting an extensive evaluation on a real TrustZone-M hardware platform, i.e., Arm Musca-B1. uTango will be open-sourced and freely available on GitHub in hopes of engaging academia and industry on securing the foreseeable trillion IoT devices.

In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads. Combined with the open RISC-V Instruction Set Architecture (ISA), the FPGA technology provides endless opportunities to create reconfigurable IoT devices with different accelerators and coprocessors tightly and loosely coupled with the processor. When connecting IoT devices to the Internet, secure communications and data exchange are major concerns. However, adding security features requires extra capabilities from the already resource-constrained IoT devices. This article presents the FAC-V coprocessor, which is an FPGA-based solution for an RISC-V processor that can be deployed following two different coupling styles. FAC-V implements in hardware the Advanced Encryption Standard (AES), one of the most widely used cryptographic algorithms in IoT low-end devices, at the cost of few FPGA resources. The conducted experiments demonstrate that FAC-V can achieve performance improvements of several orders of magnitude when compared to the software-only AES implementation; e.g., encrypting a message of 16 bytes with AES-256 can reach a performance gain of around 8000× with an energy consumption of 0.1 μJ.

The end of Moore’s Law aligned with data privacy concerns is forcing machine learning (ML) to shift from the cloud to the deep edge. In the next-generation ML systems, the inference and part of the training process will perform at the edge, while the cloud stays responsible for major updates. This new computing paradigm, called federated learning (FL), alleviates the cloud and network infrastructure while increasing data privacy. Recent advances empowered the inference pass of quantized artificial neural networks (ANNs) on Arm Cortex-M and RISC-V microcontroller units (MCUs). Nevertheless, the training remains confined to the cloud, imposing the transaction of high volumes of private data over a network and leading to unpredictable delays when ML applications attempt to adapt to adversarial environments. To fill this gap, we make the first attempt to evaluate the feasibility of ANN training in Arm Cortex-M MCUs. From the available optimization algorithms, stochastic gradient descent (SGD) has the best trade-off between accuracy, memory footprint, and latency. However, its original form and the variants available in the literature still do not fit the stringent requirements of Arm Cortex-M MCUs. We propose L-SGD, a lightweight implementation of SGD optimized for maximum speed and minimal memory footprint in this class of MCUs. We developed a floating-point version and another that operates over quantized weights. For a fully-connected ANN trained on the MNIST dataset, L-SGD (float-32) is 4.20× faster than the SGD while requiring only 2.80% of the memory with negligible accuracy loss. Results also show that quantized training is still unfeasible to train an ANN from the scratch but is a lightweight solution to perform minor model fixes and counteract the fairness problem in typical FL systems.