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In this paper, we present the implementation of the Density Functional Theory (DFT) method using the Geant4-DNA framework in the Single Instruction Single Data (SISD) mode. Furthermore, this implementation is improved in terms of execution time within the GeantV project with vectorization techniques such as Single Instruction Multiple Data (SIMD). Within this framework, a set of SIMD strategies in molecular calculation algorithms such as one-electron operators, two-electron operator, quadrature grids, and functionals, was implemented using the VecCore library. The applications developed in this work implement two DFT functionals, the Local Density Approximation (LDA) and the General Gradient Approximation (GGA), to approximate the molecular ground-state energies of small molecules and amino acids. To assess the performance of the implementations, a standard test simulation was performed in multiple CPU platforms. The SIMD vectorization strategy significantly accelerates DFT calculations, leading to time ratios ranging from 1.6 to 5.4 in either individual steps or entire implementations when compared with the scalar process within Geant4. [ABSTRACT FROM AUTHOR]

In the field of image object detection and semantic segmentation, improving the accuracy of object identification and segmentation is a primary goal. To achieve this, leveraging the potential of multi-scale information through feature map refinement and fusion has been widely recognized. However, existing feature fusion methods either design more complex feature pyramid networks, replace existing detectors, or incrementally introduce feature fusion modules, overlooking the effective approach of enhancing spatial information in deep feature maps. We propose a novel pluggable feature fusion paradigm termed ‘Effective Learning Bridge’. Our research introduces an efficient and adaptive learning mechanism that builds learning bridges between feature maps at different scales within the feature pyramid, thereby enhancing the spatial information of objects in deep feature maps. This mechanism is specifically designed for multi-scale feature maps and can be seamlessly integrated into any network incorporating feature maps. By altering the model’s backpropagation path, we successfully improve learning efficiency, which in turn enhances the accuracy of object detection and segmentation. Our proposed paradigm and method were extensively evaluated through experiments on SIMD, HRSID, and WHDLD datasets and benchmark models. The results unequivocally demonstrate the effectiveness of our approach in significantly improving the accuracy of object detection and semantic segmentation, as well as the overall learning efficiency of the model. [ABSTRACT FROM AUTHOR]

Sepsis-induced myocardial dysfunction (SIMD), also known as sepsis-induced cardiomyopathy (SICM), is linked to significantly increased mortality. Despite its clinical importance, effective therapies for SIMD remain elusive, largely due to an incomplete understanding of its pathogenesis. Over the past five decades, research involving both animal models and human studies has highlighted several pathogenic mechanisms of SICM, yet many aspects remain unexplored. Initially thought to be primarily driven by inflammatory cytokines, current research indicates that these alone are insufficient for the development of cardiac dysfunction. Recent studies have brought attention to additional mechanisms, including excessive nitric oxide production, mitochondrial dysfunction, and disturbances in calcium homeostasis, as contributing factors in SICM. Emerging clinical evidence has highlighted the significant role of myocardial edema in the pathogenesis of SICM, particularly its association with cardiac remodeling in septic shock patients. This review synthesizes our current understanding of SIMD/SICM, focusing on myocardial edema's contribution to cardiac dysfunction and the critical role of the bradykinin receptor B1 (B1R) in altering myocardial microvascular permeability, a potential key player in myocardial edema development during sepsis. Additionally, this review briefly summarizes existing therapeutic strategies and their challenges and explores future research directions. It emphasizes the need for a deeper understanding of SICM to develop more effective treatments. [ABSTRACT FROM AUTHOR]

In this work, we present the highly optimized implementation of the HAETAE algorithm, submitted to the second round of the Korean Post-Quantum Cryptography (KpqC) competition and to the first round of NIST's additional post-quantum standardization for digital signatures on 64-bit ARMv8 embedded processors. To the best of our knowledge, this is the first optimized implementation of the HAETAE algorithm on 64-bit ARMv8 embedded processors. We apply various optimization techniques to enhance the multiplication operations in the HAETAE algorithm. We utilize parallel operation techniques involving vector registers and NEON (Advanced SIMD technology used in ARM processors) instructions of ARMv8 embedded processors. In particular, we achieved the best performance of the HAETAE algorithm on ARMv8 embedded processors by applying all the state-of-the-art NTT (Number Theoretic Transform) implementation techniques. Performance improvements of up to 3.07 × , 3.63 × , and 9.15 × were confirmed for NTT, Inverse-NTT, and pointwise Montgomery operations (Montgomery multiplication used in modular arithmetic), respectively, by applying the state-of-the-art implementation techniques, including the proposed techniques. As a result, we achieved a maximum performance improvement of up to 1.16 × for the key generation algorithm, up to 1.14 × for the signature algorithm, and up to 1.25 × for the verification algorithm. [ABSTRACT FROM AUTHOR]

The present study focused on exploring the clinical value and molecular mechanism of LncRNA MCM3AP antisense RNA 1 (MCM3AP-AS1) in sepsis and sepsis-induced myocardial dysfunction (SIMD). 122 sepsis patients and 90 healthy were included. Sepsis patients were categorized into SIMD and non-MD. The expression levels of MCM3AP-AS1 and miRNA were examined using RT-qPCR. Diagnostic value of MCM3AP-AS1 in sepsis assessed by ROC curves. Logistic regression to explore risk factors influencing the occurrence of SIMD. Cardiomyocytes were induced by LPS to construct cell models in vitro. CCK-8, flow cytometry, and ELISA to analyze cell viability, apoptosis, and inflammation levels. Serum MCM3AP-AS1 was upregulated in patients with sepsis. The sensitivity and specificity of MCM3AP-AS1 were 75.41% and 93.33%, for recognizing sepsis from healthy controls. Additionally, elevated MCM3AP-AS1 is a risk factor for SIMD and can predict SIMD development. Compared with the LPS-induced cardiomyocytes, inhibition of MCM3AP-AS1 significantly attenuated LPS-induced apoptosis and inflammation; however, this attenuation was partially reversed by lowered miR-28-5p, but this reversal was partially eliminated by CASP2. MCM3AP-AS1 may be a novel diagnostic biomarker for sepsis and can predict the development of SIMD. MCM3AP-AS1 probably participated in SIMD progression by regulating cardiomyocyte inflammation and apoptosis through the target miR-28-5p/CASP2 axis. [ABSTRACT FROM AUTHOR]

The immune response gene 1 (IRG1) and its metabolite itaconate are implicated in modulating inflammation and oxidative stress, with potential relevance to sepsis-induced myocardial dysfunction (SIMD). This study investigates their roles in SIMD using both in vivo and in vitro models. Mice were subjected to lipopolysaccharide (LPS)-induced sepsis, and cardiac function was assessed in IRG1 knockout (IRG1-/-) and wild-type mice. Exogenous 4-octyl itaconate (4-OI) supplementation was also examined for its protective effects. In vitro, bone marrow-derived macrophages and RAW264.7 cells were treated with 4-OI following Nuclear factor, erythroid 2 like 2 (NRF2)–small interfering RNA administration to elucidate the underlying mechanisms. Our results indicate that IRG1 deficiency exacerbates myocardial injury during sepsis, while 4-OI administration preserves cardiac function and reduces inflammation. Mechanistic insights reveal that 4-OI activates the NRF2/HO-1 pathway, promoting macrophage polarization and attenuating inflammation. These findings underscore the protective role of the IRG1/itaconate axis in SIMD and suggest a therapeutic potential for 4-OI in modulating macrophage responses. [ABSTRACT FROM AUTHOR]

ABSTRACT Introduction Methods Results Conclusion Socioeconomic deprivation is a known risk factor for head and neck cancer (HNC). Despite this, there is no current way to acknowledge this in two‐week wait (2WW) referrals. 2WW HNC referrals have continually risen, and a self‐reporting questionnaire was trialled with referrals to the ear, nose and throat (ENT) department with suspected HNC, allowing additional triage information not included in referrals to be obtained.Patients referred through the 2WW pathway for HNC between February 2021 and March 2022 were asked to complete an electronic self‐reporting symptom questionnaire. The vetting process resulted in the referral being accepted or regraded to less urgent referral streams. Scottish Index of Multiple Deprivation (SIMD) quintiles were derived using the online postcode checker tool.A total of 984 2WW referrals were retrospectively reviewed. The questionnaire was completed by 717 (72.9%) patients. Regrading of urgency resulted in 292 (29.7%) 2WW appointments not required. Of those regraded, 264 (90.4%) patients completed the questionnaire. A significantly greater number of patients (p = 0.03) from SIMD 4 and SIMD 5 were regraded (33.3%) compared to SIMD 1 and SIMD 2 (26.4%). Patients who did not complete the questionnaire had a higher median age (61.0 years, range: 17–96, IQR: 25.0) compared to those who completed the questionnaire (56.0 years, range: 17–88, IQR: 23.5, p < 0.001).A self‐reported symptom questionnaire can help rebalance urgent appointments to those with genuine red flag symptoms. This in turn reduces social inequality in 2WW referrals and reduces the number of inappropriate 2WW appointments. [ABSTRACT FROM AUTHOR]

This study focuses on the performance of the elastic–viscous–plastic (EVP) dynamical solver within the sea ice model, CICE v6.5.1. The study has been conducted in two steps. First, the standard EVP solver was extracted from CICE for experiments with refactored versions, which are used for performance testing. Second, one refactored version was integrated and tested in the full CICE model to demonstrate that the new algorithms do not significantly impact the physical results. The study reveals two dominant bottlenecks, namely (1) the number of Message Parsing Interface (MPI) and Open Multi-Processing (OpenMP) synchronization points required for halo exchanges during each time step combined with the irregular domain of active sea ice points and (2) the lack of single-instruction, multiple-data (SIMD) code generation. The standard EVP solver has been refactored based on two generic patterns. The first pattern exposes how general finite differences on masked multi-dimensional arrays can be expressed in order to produce significantly better code generation by changing the memory access pattern from random access to direct access. The second pattern takes an alternative approach to handle static grid properties. The measured single-core performance improvement is more than a factor of 5 compared to the standard implementation. The refactored implementation of strong scales on the Intel® Xeon® Scalable Processors series node until the available bandwidth of the node is used. For the Intel® Xeon® CPU Max series, there is sufficient bandwidth to allow the strong scaling to continue for all the cores on the node, resulting in a single-node improvement factor of 35 over the standard implementation. This study also demonstrates improved performance on GPU processors. [ABSTRACT FROM AUTHOR]

SUMMARY: Large-scale and high-resolution seismic modelling are very significant to simulating seismic waves, evaluating earthquake hazards and advancing exploration seismology. However, achieving high-resolution seismic modelling requires substantial computing and storage resources, resulting in a considerable computational cost. To enhance computational efficiency and performance, recent heterogeneous computing platforms, such as Nvidia Graphics Processing Units (GPUs), natively support half-precision floating-point numbers (FP16). FP16 operations can provide faster calculation speed, lower storage requirements and greater performance enhancement over single-precision floating-point numbers (FP32), thus providing significant benefits for seismic modelling. Nevertheless, the inherent limitation of fewer 16-bit representations in FP16 may lead to severe numerical overflow, underflow and floating-point errors during computation. In this study, to ensure stable wave equation solutions and minimize the floating-point errors, we use a scaling strategy to adjust the computation of FP16 arithmetic operations. For optimal GPU floating-point performance, we implement a 2-way single instruction multiple data (SIMD) within the floating-point units (FPUs) of CUDA cores. Moreover, we implement an earthquake simulation solver for FP16 operations based on curvilinear grid finite-difference method (CGFDM) and perform several earthquake simulations. Comparing the results of wavefield data with the standard CGFDM using FP32, the errors introduced by FP16 are minimal, demonstrating excellent consistency with the FP32 results. Performance analysis indicates that FP16 seismic modelling exhibits a remarkable improvement in computational efficiency, achieving a speedup of approximately 1.75 and reducing memory usage by half compared to the FP32 version. [ABSTRACT FROM AUTHOR]

Prior research has introduced the Single-Instruction-Multiple-Data paradigm for DNA computing (SIMD DNA). It offers the potential for storing information and performing in-memory computations on DNA, with massive parallelism. This paper introduces three new SIMD DNA operations: sorting, shifting, and searching. Each is a fundamental operation in computer science. Our implementations demonstrate the effectiveness of parallel pairwise operations with this new paradigm. [ABSTRACT FROM AUTHOR]

Despite the enormous technical and financial advantages of cloud computing, security and privacy have always been the primary concerns for adopting cloud computing facilities, especially for government agencies and commercial sectors with high-security requirements. Homomorphic encryption (HE) has recently emerged as an effective tool in ensuring privacy and security for sensitive applications by allowing computing on encrypted data. One major obstacle to employing HE-based computation, however, is its excessive computational cost, which can be orders of magnitude higher than its counterpart based on the plaintext. In this paper, we study the problem of how to reduce the HE-based computational cost for general matrix multiplication, i.e., a fundamental building block for numerous practical applications, by taking advantage of the single instruction multiple data operations supported by HE schemes. Specifically, we develop a novel element-wise algorithm for general matrix multiplication, based on which we propose two HE-based general matrix multiplication algorithms to reduce the HE computation cost. Our experimental results show that our algorithms significantly outperform the state-of-the-art approaches of HE-based matrix multiplication. [ABSTRACT FROM AUTHOR]

We investigate how to port the standard interior-point method to new exascale architectures for block-structured nonlinear programs with state equations. Computationally, we decompose the interior-point algorithm into two successive operations: the evaluation of the derivatives and the solution of the associated Karush-Kuhn-Tucker (KKT) linear system. Our method accelerates both operations using two levels of parallelism. First, we distribute the computations on multiple processes using coarse parallelism. Second, each process uses SIMD/GPU accelerators locally to accelerate the operations using fine-grained parallelism. The KKT system is reduced by eliminating the inequalities and the state variables from the corresponding equations. We demonstrate our method's capability on the supercomputer Polaris, a testbed for the future exascale Aurora system. Each node is equipped with four GPUs, a setup amenable to our two-level approach. Our experiments on the stochastic optimal power flow problem show that the reduction method is 50x faster than the sparse linear solver HSL MA57 running in serial on the CPU, and 6x faster than Pardiso running in parallel on CPU on the same number of processes. [ABSTRACT FROM AUTHOR]

With the rapid expansion of process mining implementation in global enterprises distributed across numerous branches, there is a critical requirement to develop an application qualified for real-time operation with fast and precise data integration. To address this challenge, computational parallelism emerges as a feasible solution to accelerate data analytics, with graphical processor unit (GPU) computing currently trending for achieving parallelism acceleration. In this study, we developed a process mining application to optimize parallel and distributed process discovery through a combination of central processing unit (CPU) and GPU computing. The use of this computing combination is leveraged for executing multi-windowing threads within multi-instruction, multiple data (MIMD) in the CPU for streaming distributed event logs, using multi-instruction, single data (MISD) within the CPU to deploy a large footprint pipeline to the GPU, and then utilizing single instruction, multiple data (SIMD) to execute global thread discovery within the GPU. This method significantly accelerates performance in real-time distributed discovery. By reducing branch divergence in SIMD on the global thread GPU parallelism, it outperformed local-thread CPU execution in deterministic discovery, speeding up from 10 to 40 times under specific conditions using a novel min-max flag algorithm implemented within the main steps of the process discovery. [ABSTRACT FROM AUTHOR]

Sepsis is a syndrome of organ dysfunction caused by a dysregulated immune response to infection, with high morbidity and mortality. At present, there have been many advances in the study of its pathogenesis, especially the cardiac dysfunction caused by sepsis, namely sepsis-induced myocardial dysfunction, SIMD, which has received widespread attention. The mechanisms of SIMD mainly include excessive release of inflammatory mediators, impaired mitochondrial function, autophagy, apoptosis and myocardial dysfunction. This article reviews the pathogenesis of SIMD and elaborates on the progress in its treatment, aiming to improve the prognosis of patients with SIMD and sepsis. [ABSTRACT FROM AUTHOR]

It is significant to note that 50% of patients with sepsis show cardiac insufficiency. Ginsenoside-Rg1 (G-Rg1) has been shown to have a cardiovascular protective effect. However, whether G-Rg1 is involved in the mechanism of action of sepsis-induced myocardial damage (SIMD) is unclear. This study aimed to investigate the protective effect of G-Rg1 on SIMD and to further investigate its mechanism and mechanisms of regulation of downstream pathways. An in vivo model of sepsis was established in mice by cecal ligation and puncture (CLP), and mice was administered intraperitoneally 35 or 70 mg/kg G-Rg1 after surgery. The damage to cardiac tissue was detected by hematoxylin and eosin (HE) staining. Forkhead transcription factor O subfamily member 3a (FOXO3A) in SIMD mice was detected by immunohistochemistry. Apoptosis in mouse myocardial tissue was determined by TUNEL staining. The effect of G-Rg1 on SIMD cardiomyocytes was evaluated by incubating the cells with lipopolysaccharide to induce inflammation as an in vitro model of SIMD. Cardiomyocyte viability and apoptosis were evaluated by cell counting kit-8 (CCK-8) and flow cytometry. Lactate dehydrogenase (LDH), creatine kinase-MB (CK-MB), cardiac troponin I (cTnI), and Fe2+ markers of heart damage were detected by the kit. The concentrations of tumor necrosis factor alpha (TNF-a) and interleukin-1beta (IL-1ß) in heart tissue and H9c2 cells were determined by ELISA. The factors related to the focal adhesion kinase (FAK)/protein kinase B (AKT)-FOXO3A signaling pathway were determined by RT-qPCR and Western blot. High-dose G-Rg1 had a significant inhibitory effect on SIMD mouse model and lipopolysaccharide (LPS)-induced H9c2 cardiomyocytes, reducing serum levels of LDH, CK-MB, and cTnI concentrations, which effectively alleviated SIMD. G-Rg1 restored the abnormally elevated levels of TNF-a, IL-1ß, and iron ions and promoted the expression of antiapoptotic protein B-cell lymphoma 2 (Bcl-2) expression, inhibiting apoptosis and inflammatory responses. In addition, G-Rg1 reversed the inhibitory effect of G-Rg1 on LPS-induced H9c2 cardiomyocyte injury through activation of the FAK/AKT signaling pathway and up-regulation of FOXO3A. G-Rg1 promoted the activation of the FAK/AKT signaling pathway and up-regulation of the protein expression levels of pathway-associated proteins, p-FAK and p-AKT. Therefore, G-Rg1 mediated the FAK/AKT-FOXO3A signaling pathway and played a role in the treatment of SIMD. We conclude that G-Rg1 inhibited apoptosis and inflammation of cardiomyocytes induced by sepsis and reduced iron ion levels by regulating FAK/AKT-FOXO3A signaling pathway. [ABSTRACT FROM AUTHOR]

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There is still a lack of effective treatment for sepsis-induced myocardial dysfunction (SIMD), while the pathogenesis of SIMD still remains largely unexplained. RNA sequencing results (GSE267388 and GSE79962) were used for cross-species integrative analysis. Bioinformatic analyses were used to delve into function, tissue- and cell- specificity, and interactions of genes. External datasets and qRT-PCR experiments were used for validation. L1000 FWD was used to predict targeted drugs, and 3D structure files were used for molecular docking. Based on bioinformatic analyses, ten differentially expressed genes were selected as genes of interest, seven of which were verified to be significantly differential expression. Bucladesine was considered as a potential targeted drug for SIMD, which banded to seven target proteins primarily by forming hydrogen bonds. It was considered that Cebpd , Timp1 , Pnp , Osmr , Tgm2 , Cp, and Asb2 were novel disease genes, while bucladesine was a potential therapeutic drug, of SIMD. • The pathogenesis of sepsis-induced myocardial dysfunction remains largely unexplained. • This study produced a new RNA sequencing dataset of heart tissue from mouse models. • Seven novel disease genes of sepsis-induced myocardial dysfunction were screened. • Bucladesine was considered as a potential targeted drug of these genes. [ABSTRACT FROM AUTHOR]

Sepsis-induced myocardial dysfunction (SIMD) is a severe complication in sepsis, manifested as myocardial systolic dysfunction, which is associated with poor prognosis and higher mortality. Mitophagy, a self-protective mechanism maintaining cellular homeostasis, plays an indispensable role in cardioprotection. This study aimed to unveil the cardioprotective effects of Baricitinib on LPS-induced myocardial dysfunction and its effect on mitophagy. Herein, we demonstrated that LPS induced severe myocardial dysfunction and initiated mitophagy in septic mice hearts. Despite the initiation of mitophagy, a significant number of apoptotic cells and damaged mitochondria persisted in the myocardium, and myocardial energy metabolism remained impaired, indicating that the limited mitophagy was insufficient to mitigate LPS-induced damage. The JAK2-AKT-mTOR signaling pathway is activated in LPS-induced cardiomyocytes and in the hearts of septic mice. Baricitinib administration remarkably improved cardiac function, suppressed systemic inflammatory response, attenuated histopathological changes, inhibited cardiac cell apoptosis and alleviated myocardial damage in septic mice. Furthermore, Baricitinib treatment significantly enhanced PINK1-Parkin-mediated mitophagy, increased autophagosomes, decreased impaired mitochondria, and restored myocardial energy metabolism. Mechanically, the limited mitophagy in septic myocardium was associated with increased p-ULK1 (Ser757), which was regulated by p-mTOR. Baricitinib reduced p-ULK1 (Ser757) and enhanced mitophagy by inhibiting the JAK2-AKT-mTOR signaling pathway. Inhibition of mitophagy with Mdivi-1 reversed the cardiac protective and anti-inflammatory effects of Baricitinib in septic mice. These findings suggest that Baricitinib attenuates SIMD by enhancing mitophagy in cardiomyocytes via the JAK2-AKT-mTOR signaling pathway, providing a novel mechanistic and therapeutic insight into the SIMD. [Display omitted] • The JAK2-AKT-mTOR pathway limits cardiac mitophagy activation in septic mice. • Baricitinib improves cardiac function in septic mice by enhancing mitophagy. • Inhibiting mitophagy reverses Baricitinib's cardiac protection benefit. • Baricitinib treatment is a promising therapeutic strategy for SIMD. [ABSTRACT FROM AUTHOR]

Background and Objectives: The future demands of multimedia and signal processing applications forced the IC designers to utilize efficient high performance techniques in more complex SoCs to achieve higher computing throughput besides energy/power efficiency improvement. In recent technologies, variation effects and leakage power highly affect the design specifications and designers need to consider these parameters in design time. Considering both challenges as well as boosting the computation throughput makes the design more difficult. Methods: In this article, we propose a simple serial core for higher energy/power efficiency and also utilize data level parallel structures to achieve required computation throughput. Results: Using the proposed core we have 35% (75%) energy (power) improvement and also using parallel structure results in 8x higher throughput. The proposed architecture is able to provide 76 MIPS computation throughput by consuming only 2.7 pj per instruction. The outstanding feature of this processor is its resiliency against the variation effects. Conclusion: Simple serial architecture reduces the effect of variations on design paths, furthermore, the effect of process variation on throughput loss and energy dissipation is negligible and almost zero. Proposed processor architecture is proper for energy/power constrained applications such as internet of things (IoT) and mobile devices to enable easy energy harvesting for longer lifetime. [ABSTRACT FROM AUTHOR]

This paper studies the use of NEON instructions for the implementation of elliptic curve cryptographic primitives on ARM Cortex-A processors. Starting from the analysis of point arithmetic formulas in different coordinate systems it was possible to identify several operations with no data dependency. Then, these operations were conveniently grouped in pairs to perform them in parallel using the NEON engine. Following this approach, dual NEON-based multiplications and squarings in the finite field ... are proposed. Furthermore, these dual ... operations are also used to speed up multiplications and squarings over the field extension ...2 . Finally, after integrating them into the point addition and point doubling formulas, we measure their impact on the execution time of scalar multiplications on elliptic curves defined over both finite fields. By using a mixed C/NEON implementation approach our solution is easily scalable at run time to support different curve sizes. Experiments conducted on the ARM Cortex-A9 processing system embedded in the Xilinx XC7Z020 device reported performance improvements of the NEON-based scalar multiplication between 32% and 38% and between 9% and 34% compared to a conventional implementation of the same operation on 254-bit, 384-bit and 510-bit curves over ... and ...2 respectively. [ABSTRACT FROM AUTHOR]

The well-known Smith-Waterman (SW) algorithm is the most commonly used method for local sequence alignments, but its acceptance is limited by the computational requirements for large protein databases. Although the acceleration of SW has already been studied on many parallel platforms, there are hardly any studies which take advantage of the latest Intel architectures based on AVX-512 vector extensions. This SIMD set is currently supported by Intel's Knights Landing (KNL) accelerator and Intel's Skylake (SKL) general purpose processors. In this paper, we present an SW version that is optimized for both architectures: the renowned SWIMM 2.0. The novelty of this vector instruction set requires the revision of previous programming and optimization techniques. SWIMM 2.0 is based on a massive multi-threading and SIMD exploitation. It is competitive in terms of performance compared with other state-of-the-art implementations, reaching 511 GCUPS on a single KNL node and 734 GCUPS on a server equipped with a dual SKL processor. Moreover, these successful performance rates make SWIMM 2.0 the most efficient energy footprint implementation in this study achieving 2.94 GCUPS/Watts on the SKL processor. [ABSTRACT FROM AUTHOR]

Abstract Single-instruction multiple-data (SIMD) architecture is a promising and widely used avenue for enhancing performance. Most of current multicore systems adopt this technique in which each core is equipped with an SIMD engine. However, these SIMD engines are frequently underutilized in single-thread applications. A typical reason is that only one SIMD engine can be utilized for a single thread, even if other SIMD engines are idle, and abundant data-level parallelism (DLP) can be exploited. To address this problem, we propose SIMD Stealing , which is an architectural support for multicore systems that provide the capability of dynamically adjusting the number of SIMD engines during application execution. This approach includes hardware modification and compilation extension, which can improve SIMD efficiency significantly in DLP applications. Experiment results show that SIMD stealing achieves an energy-delay product (EDP) reduction of approximately 53% for kernels and an EDP reduction of 34% for applications on average, with a small area overhead. [ABSTRACT FROM AUTHOR]

Over the last decade, to improve the necessary accuracy and reliability of the existing global positioning system (GPS), incorporation with new constellations such as European Galileo navigation system and the update of the Russian Global Navigation Satellite System (GLONASS) attract a lot of attentions. In software integrations, the most important challenge is the calculation load which should be solved using suitable techniques. The parallel nature of this application causes graphic processing unit (GPU) and multi-core platform as a low cost and effective solution for the implementation of a software receiver. In this paper, in order to accelerate GPS acquisition, a hybrid parallel algorithm based on GPU and multi-core CPU is designed and implemented on two systems with GT630 and GT630M GPU. Experimental results show that the proposed algorithm is 2.2 times faster than sequential algorithm in one-core implementation and 4 times faster in quad core. On the other hand, the proposed parallel acquisition algorithm on GPU-based 2-core is 15% faster than acquisition on 4-core without GPU, which shows the effective role of GPU in parallelism of this application. [ABSTRACT FROM AUTHOR]

Abstract Accurately predicting key combustion phenomena in reactive-flow simulations, e.g., lean blow-out, extinction/ignition limits and pollutant formation, necessitates the use of detailed chemical kinetics. The large size and high levels of numerical stiffness typically present in chemical kinetic models relevant to transportation/power-generation applications make the efficient evaluation/factorization of the chemical kinetic Jacobian and thermochemical source-terms critical to the performance of reactive-flow codes. Here we investigate the performance of vectorized evaluation of constant-pressure/volume thermochemical source-term and sparse/dense chemical kinetic Jacobians using single-instruction, multiple-data (SIMD) and single-instruction, multiple thread (SIMT) paradigms. These are implemented in pyJac, an open-source, reproducible code generation platform. Selected chemical kinetic models covering the range of sizes typically used in reactive-flow simulations were used for demonstration. A new formulation of the chemical kinetic governing equations was derived and verified, resulting in Jacobian sparsities of 28.6–92.0% for the tested models. Speedups of 3.40–4.08 × were found for shallow-vectorized OpenCL source-rate evaluation compared with a parallel OpenMP code on an avx2 central processing unit (CPU), increasing to 6.63–9.44 × and 3.03–4.23 × for sparse and dense chemical kinetic Jacobian evaluation, respectively. Furthermore, the effect of data-ordering was investigated and a storage pattern specifically formulated for vectorized evaluation was proposed; as well, the effect of the constant pressure/volume assumptions and varying vector widths were studied on source-term evaluation performance. Speedups reached up to 17.60 × and 45.13 × for dense and sparse evaluation on the GPU, and up to 55.11 × and 245.63 × on the CPU over a first-order finite-difference Jacobian approach. Further, dense Jacobian evaluation was up to 19.56 × and 2.84 × times faster than a previous version of pyJac on a CPU and GPU, respectively. Finally, future directions for vectorized chemical kinetic evaluation and sparse linear-algebra techniques were discussed. [ABSTRACT FROM AUTHOR]

The revised simplex algorithm (RSA) is a typical algorithm for solving linear programming problems. Many theoretical modifications have been done to make the algorithm more efficient, but almost all of them were based on single-instruction single-data architecture processors (CPUs), which could not make full use of the inherent parallel characteristics of RSAs. We propose a novel single-instruction multiple-data architecture processor (GPU) based on the RSA in this paper. The intensive matrix manipulations of a traditional RSA are offloaded to the GPU, which helps to make full use of its powerful parallel processing ability. We implemented the GPU-based RSA on compute unified device architecture (CUDA). Numerical experiments on randomly generated linear programs show that the GPU-based RSA can not only find the correct optimal solutions, but can also reach a speed of up to 100 times as fast as that of a CPU-based RSA: it also runs 3 to 11 times as fast as MATLAB. [ABSTRACT FROM AUTHOR]

Abstract The power consumption is a key metric to design computing platforms. In particular, the variety and complexity of current applications fueled an increasing number of run-time power-aware optimization solutions to dynamically trade the computational power for the power consumption. In this scenario, the online power monitoring methodologies are the core of any power-aware optimization, since the incorrect assessment of the run-time power consumption prevents any effective actuation. This work proposes PowerTap , an all-digital power modeling methodology for designing online power monitoring solutions. In contrast with state-of-the-art solutions, PowerTap adds domain-specific constraints to the data-driven power modeling problem. PowerTap identifies the power model iteratively to balance the accuracy error of the power estimates and the complexity of the final monitoring infrastructure. As a representative use-case, we employed a complex hardware multi-threaded SIMD processor, also considering different operating clock frequencies. The RTL implementation of the identified power model targeting an Xilinx Artix 7 XC7A200T FPGA highlights an accuracy error within 1.79% with an area overhead of 9.95% (LUT) and 3.87% (flip flops) and an average power overhead of 12.17 mW regardless of the operating conditions, i.e., number of software threads and operating frequency. [ABSTRACT FROM AUTHOR]

Abstract Processor vendors have been expanding Single Instruction Multiple Data (SIMD) extensions to exploit data-level-parallelism in their General Purpose Processors (GPPs). Each SIMD technology such as Streaming SIMD Extensions (SSE) and Advanced Vector eXtensions (AVX) has its own Instruction Set Architecture (ISA) which equipped with Special Purpose Instructions (SPIs). In order to exploit these features, many programming approaches have been developed. Intrinsic Programming Model (IPM) is a low-level concept for explicit SIMDization. Besides, Compiler's Automatic Vectorization (CAV) has been embedded in modern compilers such as Intel C++ compiler (ICC), GNU Compiler Collections (GCC) and LLVM for implicit vectorization. Each SIMDization shows different improvements because of different SIMD ISAs, vector register width, and programming approaches. Our goal in this paper is to evaluate the performance of explicit and implicit vectorization. Our experimental results show that the behavior of explicit vectorization on different compilers is almost the same compared to implicit vectorization. IPM improves the performance more than CAVs. In general, ICC and GCC compilers can more efficiently vectorize kernels and use SPI compared to LLVM. In addition, AVX2 technology is more useful for small matrices and compute-intensive kernels compared to large matrices and data-intensive kernels because of memory bottlenecks. Furthermore, CAVs fail to vectorize kernels which have overlapping and non-consecutive memory access patterns. The way of implementation of a kernel impacts the vectorization. In order to understand what kind of scalar implementations of an algorithm is suitable for vectorization, an approach based on code modification technique is proposed. Our experimental results show that scalar implementations that have either loop collapsing, loop unrolling, software pipelining, or loop exchange techniques can be efficiently vectorized compared to straightforward implementations. [ABSTRACT FROM AUTHOR]

Motivation Pairwise sequence alignment is undoubtedly a central tool in many bioinformatics analyses. In this paper, we present a generically accelerated module for pairwise sequence alignments applicable for a broad range of applications. In our module, we unified the standard dynamic programming kernel used for pairwise sequence alignments and extended it with a generalized inter-sequence vectorization layout, such that many alignments can be computed simultaneously by exploiting SIMD (single instruction multiple data) instructions of modern processors. We then extended the module by adding two layers of thread-level parallelization, where we (a) distribute many independent alignments on multiple threads and (b) inherently parallelize a single alignment computation using a work stealing approach producing a dynamic wavefront progressing along the minor diagonal. Results We evaluated our alignment vectorization and parallelization on different processors, including the newest Intel® Xeon® (Skylake) and Intel® Xeon PhiTM (KNL) processors, and use cases. The instruction set AVX512-BW (Byte and Word), available on Skylake processors, can genuinely improve the performance of vectorized alignments. We could run single alignments 1600 times faster on the Xeon PhiTM and 1400 times faster on the Xeon® than executing them with our previous sequential alignment module. Availability and implementation The module is programmed in C++ using the SeqAn (Reinert et al. 2017) library and distributed with version 2.4 under the BSD license. We support SSE4, AVX2, AVX512 instructions and included UME: SIMD, a SIMD-instruction wrapper library, to extend our module for further instruction sets. We thoroughly test all alignment components with all major C++ compilers on various platforms. Supplementary information Supplementary data are available at Bioinformatics online. [ABSTRACT FROM AUTHOR]

This paper analyzes the suitability of single-instruction multiple data (SIMD) extensions of current microprocessors under radiation environments. SIMD extensions are intended for software acceleration, focusing mostly in applications that require high computational effort, which are common in many fields such as computer vision. SIMD extensions use a dedicated coprocessor that makes possible packing several instructions in one single extended instruction. Applications that require high performance could benefit from the use of SIMD coprocessors, but their reliability needs to be studied. In this paper, NEON, the SIMD coprocessor of ARM microprocessors, has been selected as a case study to explore the behavior of SIMD extensions under radiation. Radiation experiments of ARM CORTEX-A9 microprocessors have been accomplished with the objective of determining how the use of this kind of coprocessor can affect the system reliability. [ABSTRACT FROM AUTHOR]

Heterogeneity, parallelization and vectorization are key techniques to improve the performance and energy efficiency of modern computing systems. However, programming and maintaining code for these architectures poses a huge challenge due to the ever-increasing architecture complexity. Task-based environments hide most of this complexity, improving scalability and usage of the available resources. In these environments, while there has been a lot of effort to ease parallelization and improve the usage of heterogeneous resources, vectorization has been considered a secondary objective. Furthermore, there has been a swift and unstoppable burst of vector architectures at all market segments, from embedded to HPC. Vectorization can no longer be ignored, but manual vectorization is tedious, error-prone and not practical for the average programmer. This work evaluates the feasibility of user-directed vectorization in task-based applications. Our evaluation is based on the OmpSs programming model, extended to support user-directed vectorization for different SIMD architectures (i.e., SSE, AVX2, AVX512). Results show that user-directed codes achieve manually optimized code performance and energy efficiency with minimal code modifications, favoring portability across different SIMD architectures. [ABSTRACT FROM AUTHOR]

The efficiency of a pleasingly parallel application is studied for several computing platforms. A real world problem, i.e., Monte-Carlo numerical simulations of stratospheric balloon envelope drift descent is considered. We detail the optimization of the SIMD parallel codes on the K40 and K80 GPUs as well as on the Intel Xeon Phi. We emphasize on loop and task parallelism, multi-threading and vectorization, respectively. The experiments show that GPU and MIC permit one to decrease computing time by non negligeable factors, as compared to a parallel code implemented on a two sockets CPU (E5-2680-v2) which finally allows us to use these devices in operational conditions. [ABSTRACT FROM AUTHOR]

Simulators help computer architects optimize system designs. The limited performance of simulators even of moderate size and detail makes the approach infeasible for design-space exploration of future exascale systems. Analytic models, in contrast, offer very fast turn-around times. In this paper we propose an analytic multi-core processor-performance model that takes as inputs a) a parametric microarchitecture-independent characterization of the target workload, and b) a hardware configuration of the core and the memory hierarchy. The processor-performance model considers instruction-level parallelism (ILP) per type, models single instruction, multiple data (SIMD) features, and considers cache and memory-bandwidth contention between cores. We validate our model by comparing its performance estimates with measurements from hardware performance counters on Intel Xeon and ARM Cortex-A15 systems. We estimate multi-core contention with a maximum error of 11.4 percent. The average single-thread error increases from 25 percent for a state-of-the-art simulator to 59 percent for our model, but the correlation is still 0.8, a high relative accuracy, while we achieve a speedup of several orders of magnitude. With a much higher capacity than simulators and more reliable insights than back-of-the-envelope calculations it makes automated design-space exploration of exascale systems possible, which we show using a real-world case study from radio astronomy. [ABSTRACT FROM PUBLISHER]

Graphics Processing Units (GPUs) have become the accelerator of choice for data-parallel applications, enabling the execution of thousands of threads in a Single Instruction - Multiple Thread (SIMT) fashion. Using OpenCL terminology, GPUs offer a global memory space shared by all the threads in the GPU, as well as a local memory space shared by only a subset of the threads. Programmers can use local memory as a scratchpad to improve the performance of their applications due to its lower latency as compared to global memory. In the SIMT execution model, data locking mechanisms used to protect shared data limit scalability. To take full advantage of the lower latency that local memory affords, and to provide an efficient synchronization mechanism, we propose GPU-LocalTM as a lightweight and efficient transactional memory (TM) for GPU local memory. To minimize the storage resources required for TM support, GPU-LocalTM allocates transactional metadata in the existing memory resources. Additionally, GPU-LocalTM implements different conflict detection mechanisms that can be used to match the characteristics of the application. For the workloads studied in our simulation-based evaluation, GPU-LocalTM provides from 1.1X up to 100X speedup over serialized critical sections. [ABSTRACT FROM PUBLISHER]

Summary: The single‐instruction multiple‐data (SIMD) computing capability of modern processors is continually improved to deliver ever better performance and power efficiency. For example, Intel has increased SIMD register lengths from 128 bits in streaming SIMD extension to 512 bits in AVX‐512. The ARM scalable vector extension supports SIMD register length up to 2048 bits and includes predicated instructions. However, SIMD instruction translation in dynamic binary translation has not received similar attention. For example, the widely used QEMU emulates guest SIMD instructions with a sequence of scalar instructions, even when the host machines have relevant SIMD instructions. This leaves significant potential for performance enhancement. We propose a newly designed SIMD translation framework for dynamic binary translation, which takes advantage of the host's SIMD capabilities. The proposed framework has been built in HQEMU, an enhanced QEMU with a separate thread for applying LLVM optimizations. The current prototype supports ARMv7, ARMv8, and IA32 guests on the X86‐64 AVX‐2 host. Compared with the scalar‐translation version HQEMU, our framework runs up to 1.84 times faster on Standard Performance Evaluation Corporation 2006 CFP benchmarks and up to 6.81 times faster on selected real applications. [ABSTRACT FROM AUTHOR]

The aim of this paper is to evaluate OpenMP, TBB and Cilk Plus as basic language-based tools for simple and efficient parallelization of recursively defined computational problems and other problems that need both task and data parallelization techniques. We show how to use these models of parallel programming to transform a source code of Adaptive Simpson’s Integration to programs that can utilize multiple cores of modern processors. Using the example of Belman-Ford algorithm for solving single-source shortest path problems, we advise how to improve performance of data parallel algorithms by tuning data structures for better utilization of vector extensions of modern processors. Manual vectorization techniques based on Cilk array notation and intrinsics are presented. We also show how to simplify such optimization using Intel SIMD Data Layout Template containers. [ABSTRACT FROM AUTHOR]

Abstract: Fog and mobile edge computing is a paradigm that augments resource‐scarce mobile devices with resource‐rich network servers to enable ubiquitous computing. Smartphone applications rely on code offloading techniques to leverage high‐performance computing opportunities available on edge and cloud servers for compute‐intensive applications. Mobile (ARM) and edge/cloud (x86) architectures are heterogeneous and necessitate dynamic binary translation for compiled code migration that increases the application execution time. The application execution time and energy consumption should be lesser on the edge/cloud server as compared with the local mobile execution for optimal offload. Multimedia‐based applications contain a large set of single instruction multiple data (SIMD) instructions that are compute and resource intensive. However, dynamic binary translation techniques of SIMD instructions lose the parallelism and optimization because of inefficient vector‐to‐scalar translation. We present a framework for SIMD instruction translation and offloading for mobile devices (SIMDOM) in cloud and edge environments. The SIMDOM framework reduces the execution overhead of migrated vectorized multimedia application by using vector‐to‐vector instruction mappings. The framework maps and translates ARM SIMD intrinsic instructions to x86 SIMD intrinsic instructions such that an application programmed for the mobile platform can be executed on the cloud server without any modification. The offload decision is based on inputs from the device energy, network, and application profilers. Experiments show that SIMDOM framework provides 84.78%, 3.41%, and 79.93% energy, time, and performance efficiency, respectively, compared with local offload‐disabled execution. Compared with compiled code offloading, the SIMDOM framework provides 55.99%, 57.50%, and 96.23% energy, time, and performance efficiency, respectively. [ABSTRACT FROM AUTHOR]

GPGPU accelerated computing has revolutionized a broad range of applications. To serve between the ever-growing computing capability and external memory, the on-chip memory is becoming increasingly important to GPGPU performance for general-purpose computing. Inherited from the traditional CPUs, however, the contemporary GPGPU on-chip memory design is suboptimal to the SIMT (single instruction, multiple threads) execution. In particular, the on-chip first-level data (L1D) cache thrashing, resulting from insufficient capacity and imbalanced usage, leads to a low hit rate and limits the overall performance. In this study, we reform the contemporary on-chip memory design and propose an integrated and balanced on-chip memory (IBOM) architecture for high-performance GPGPUs. It first virtually enlarges the L1D cache size by an integrated architecture that exploits the under-utilized register file (RF) with lightweight ISA, compiler and microarchitecture supports. Then with sufficient capacity, it is able to improve the cache usage by a set balancing technique that exploits the under-utilized set resources. In our proposed IBOM design, the register and cache accesses are amenable to normal pipeline operations with simple changes. It adequately exploits the size inversion in GPGPU on-chip memory, and enables optimized utilization of the precious resources for higher performance and energy efficiency with even smaller on-chip memory size. The experiment results demonstrate that the proposed IBOM design can offer an average of 29.6 percent increase in L1D hit rate and in turn 3X performance improvement for the cache-sensitive applications. [ABSTRACT FROM AUTHOR]

This paper presents fast computational techniques applied to modelling the RFX-mod fusion device. An integral equation model is derived for the current distribution on the active coils of the conducting structures, and the input-output transfer functions are computed. Speed-up factors of about 200 can be obtained on hybrid CPU-GPU parallelization against uniprocessor computation. [ABSTRACT FROM AUTHOR]

Recent trends in SIMD architecture have tended toward longer vector lengths, and more enhanced SIMD features have been introduced in newer vector instruction sets. However, legacy or proprietary applications compiled with short-SIMD ISA cannot benefit from the long-SIMD architecture that supports improved parallelism and enhanced vector primitives, resulting in only a small fraction of potential peak performance. This article presents a dynamic binary translation technique that enables short-SIMD binaries to exploit benefits of new SIMD architectures by rewriting short-SIMD loop code. We propose a general approach that translates loops consisting of short-SIMD instructions tomachine-independent IR, conducts SIMD loop transformation/ optimization at this IR level, and finally translates to long-SIMD instructions. Two solutions are presented to enforce SIMD load/store alignment, one for the problem caused by the binary translator's internal translation condition and one general approach using dynamic loop peeling optimization. Benchmark results show that average speedups of 1.51× and 2.48× are achieved for an ARM NEON to x86 AVX2 and x86 AVX-512 loop transformation, respectively. [ABSTRACT FROM AUTHOR]

Counting the number of ones in a binary stream is a common operation in database, informationretrieval, cryptographic and machine-learning applications. Most processors have dedicated instructions to count the number of ones in a word (e.g. popcnt on ×64 processors). Maybe surprisingly, we show that a vectorized approach using SIMD instructions can be twice as fast as using the dedicated instructions on recent Intel processors. The benefits can be even greater for applications such as similarity measures (e.g. the Jaccard index) that require additional Boolean operations. Our approach has been adopted by LLVM: it is used by its popular C compiler (Clang). [ABSTRACT FROM AUTHOR]

The second generation of the audio video coding standard (AVS2), which has been issued as IEEE 1857.4, doubles the coding efficiency of AVS1 and H.264/AVC. However, the advanced techniques in AVS2 also dramatically increase the computational complexity. The research on a commercial encoder for AVS2 is still at an early stage. In this paper, we propose the first fast intra-encoding platform for AVS2, which we term iAVS2. The platform uses numerous speedup methods, including code optimization, single-instruction multiple-data acceleration, and fast algorithms for almost all the time-consuming modules. To meet different application scenarios, five different speed levels are designed in iAVS2 to provide flexible tradeoffs between compression efficiency and encoding speed. The experimental results show that the fastest speed level of iAVS2 can accelerate the AVS2 reference software (RD12.0) by $144\times $ on average. Compared with the well-known HEVC encoder platform $\times 265$ , iAVS2 can provide over 10% bit rate saving at a similar coding speed. For the UHD and 1080 sequences, iAVS2 outperforms $\times 265$ at all speed levels. [ABSTRACT FROM PUBLISHER]