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A single-machine scheduling problem with new maintenance activities is examined in this paper. In the scheduling literature, it is often assumed that the interval between maintenance activities is fixed or within a specified time frame. However, this assumption may not hold true in many real-world situations, such as the maintenance activities in wafer manufacturing of semiconductor. Before the wafer manufacturing process starts, it is imperative that the wafers go through a number of cleaning operations to avoid contamination. Using a cleaning agent as the main material of wafer cleaning, the contamination will be dissolved and removed from wafer surface. In case of contamination being accumulated substantial and going beyond a permitted value, the cleaning agent is highly likely to damage the wafer surfaces. Thus, the interval between maintenance activities in the wafer manufacturing process is deemed irregular. The objective function of the proposed problem is to minimise total completion time. Addressing the problem, a binary integer programming model is formulated in this paper. Furthermore, with the research problem being NP-hard, a heuristic based on two special properties is proposed to address the problem. To evaluate and validate the proposed heuristic, a new lower bound is further developed. Extensive experiments have been conducted showing that the proposed heuristic efficiently yields a near-optimal solution with an average percentage error of 15.4 from lower bound. [ABSTRACT FROM AUTHOR]

To effectively analyse and evaluate the performances of closed-loop automated material handling system (AMHS) with shortcut and blocking in semiconductor wafer fabrication system, a modified Markov chain model (MMCM) has been proposed. The system characteristics, such as vehicle blockage and system’s shortcut configuration, are well considered in the MMCM. The state space explosion problem and computational challenge due to the increase of AMHS scale can be effectively eliminated. With production data from Interbay material handling system of a 300-mm semiconductor wafer fabrication line, the proposed MMCM is compared with simulation analysis model. The results demonstrate that the proposed MMCM is an effective modelling methodology for AMHS’s performance analysis at system design stage. [ABSTRACT FROM PUBLISHER]

In semiconductor wafer fabrication facilities, order-lot pegging is the process of assigning wafer lots to orders and meeting the due dates of orders is considered one of the most important operational issues. In many cases of order-lot pegging, some orders cannot be fulfilled with the current wafers in the lots being processed, necessitating the release of additional new wafer lots into the wafer fabrication facility. In this paper, we propose a simultaneous decision model for order-lot pegging and wafer release planning in semiconductor wafer fabrication facilities, and develop a Lagrangian heuristic for solving the model. The results of computational experiments conducted using randomly generated problem instances that mimic actual field data from a Korea semiconductor wafer fabrication facility indicate that the performance of the Lagrangian heuristic is superior to that of a practical greedy algorithm for practical-sized problem instances. The results also point to how sensitivity analysis can be used to answer important managerial questions for effective management of the semiconductor wafer fabrication process. [ABSTRACT FROM AUTHOR]

In this study, we propose an effective real-time scheduling method based on the timetabling technique for the cluster tool. Instead of considering the no-wait assumption generally adopted in almost all of the previous literature, we take wafer transfer delay into consideration, which implies that a wafer can stay at the current chamber for a certain, limited time before proceeding to the next chamber. In order to improve the total cycle time, an additional pulling procedure to the timetabling is introduced and applied. Numerical examples show that the proposed method gives effective schedules in real time even for practical-sized problems. [ABSTRACT FROM AUTHOR]

Automatic material handling system (AMHS) is becoming more important in 300 mm wafer fabrication factories (fab). Effective and efficient design and control of AMHS has become more critical particularly in capacity planning. The major concept of the AMHS capacity determination model is to maintain the originally designed optimal production throughput or cycle time of products. In order to maintain fab’s throughput or cycle time of products, WIP (work in process) portfolio of the constraint or the fastest workstation should be kept. Based on this concept, a GI/G/m queuing model based on FCFS (First-come-first-serve) dispatching rule of AMHS is applied to determine the required number of vehicles. Basically, products should be transported to the specific workstation (constraint or fastest workstation) before the workstation finishes the existing process; therefore, sufficient WIP in front of this specific workstation should be kept. Under this condition, the probability that transportation time exceeds product processing time under a certain transportation capacity level can be calculated by the proposed model. Hence, we can get the required capacity of AMHS to achieve the probability target set in advance. Due to the capacity of AMHS can be set according to the acceptable probability of non-exceeding the processing time of the constraint or fastest workstation, the level of WIP in front of this workstation can be kept. It also can be ensured that AMHS will not affect the production performance as well as keep the reasonable investment level. [ABSTRACT FROM PUBLISHER]

This paper examines the capacitated lot-sizing and scheduling problem (CLSP) with sequence-dependent setup times, time windows, machine eligibility and preference constraints. Such a problem frequently arises in the semiconductor manufacturing industry by which this paper is motivated. A mixed integer programming (MIP) model is constructed for the problem. Two MIP-based fix-and-optimise algorithms are proposed in which the binary decision variables associated with the assignment of machines are first fixed using the randomised least flexible machine (RLFM) rule and the rest of the decision variables are settled by an MIP solver. Extensive experiments show that the proposed algorithms outperform the state-of-the-art MIP-based fix-and-optimise algorithms in the literature, especially for instances with high machine flexibility and high demand variation. [ABSTRACT FROM PUBLISHER]

This paper is dedicated to the scheduling problem of multi-cluster tools with process module residency constraints and multiple wafer product types. The problem is formulated as a non-linear programming model based on a set of time constraint sets. An effective algorithm called the time constraint sets based (TCSB) algorithm is presented as a new method to schedule the transport modules to minimise the makespan of a number of wafers. In approach, time constraint sets are maintained for all the resources and necessary operations to exploit the remaining production capacities during the scheduling process. To validate the proposed algorithm on a broader basis, a series of simulation experiments are designed to compare our TCSB algorithm with the benchmark with regard to cluster factor, configuration flexibilities and the variation of the processing times and residency constraint times. The results indicate that the proposed TCSB algorithm gives optimal or near optimal scheduling solutions in most cases. [ABSTRACT FROM PUBLISHER]

In this paper, a real-time closed loop control dispatching heuristic (RCLC) algorithm is proposed to address the scheduling problem of parallel batch machines with incompatible job families, limited waiting time constraints, re-entrant flow and dynamic arrivals in the diffusion and oxidation areas of a semiconductor wafer fabrication system (SWFS), which is known to be strongly NP-hard. The basis of this algorithm is the information of lots in the buffer when the parallel batch machines are idle and available. In RCLC, if the number of any family lots is less than the maximum batch size, the dispatching heuristic can be seen as a pull–pull–push–push (P4) strategy; otherwise, a genetic algorithm (GA). A look-itself strategy, P4 strategy and GA can build a closed loop control system. The experiments are implemented on the Petri nets-based real-time scheduling simulation platform of SWFS, and demonstrate the effectiveness of our proposed method. [ABSTRACT FROM AUTHOR]

In this article, the model predictive control scheme is studied for a class of multiple-input multiple-output linear systems with different transient trajectories among the outputs. To eliminate the transient errors among the outputs, a modified model predictive control scheme is designed making one output track following the reference while the other outputs track following this output instead of the reference. Utilizing the specified output as the alternative reference for all the other outputs, a constructive model predictive control scheme is developed to diminish the differences of the transient-state trajectories among each output such that both the uniformity of the transient-state trajectories and the optimal steady-state trajectories are achieved. The effectiveness of the proposed transient uniformity model predictive control scheme is demonstrated in the experiment of the semiconductor wafer manufacturing baking process. The experimental results show that the transient uniformity model predictive control scheme has successfully reduced the integral square error of transient-state uniformity between any two outputs by 90% as compared to the conventional model predictive control scheme. The robustness of the proposed scheme has also been experimentally evaluated in the presence of external disturbance and plant modeling inaccuracy. [ABSTRACT FROM AUTHOR]

A real-time dispatching heuristic derived from an optimal binary integer programming model (i-RTD) to minimise the makespan of the automatic wet-etch station (AWS) scheduling problem with a chemical draining constraint is presented. Each chemical bath is drained and refilled every several days. This draining process, known as chemical dumping in the industry, occurs during the middle of a process and interrupts production. This chemical draining event creates a need for intelligent flow shop scheduling so that all baths are optimally utilised and so that jobs can skip a bath being drained and move to the next bath without interruption. The production losses from these interruptions can be minimised by optimally sequencing jobs before they enter the AWS. This paper first creates the binary integer programming (BIP) model to exactly describe the AWS scheduling problem, which later forms the basis for the i-RTD model to generate an efficient solution in real time. This unique heuristic accounts for the chemical draining constraint, time window constraint, zero wait constraint, and real-time constraint and represents a new dispatching paradigm of considerable practical interest. [ABSTRACT FROM AUTHOR]

Cluster tools have been increasingly used for semiconductor manufacturing. While there have been many studies on cluster tool scheduling, most of them have focused on full work cycles in which identical work cycles are repeated. However, in reality, there are significant transient periods during which an empty tool begins to process new wafers or finishes processing and becomes empty. We should minimise the lengths of transient periods, so that a cluster tool quickly enters a desirable steady schedule for full work cycles or finishes operations quickly. We should also regulate wafer delays within chambers, because they cause wafer quality variation or failures. In this paper, we propose scheduling strategies for transient periods to meet those requirements. We prove that for the close-down period, the earliest starting policy that starts each operation as soon as the preceding operations complete minimises the close-down period while regulating the wafer delays. We also show that for the start-up period, the latest starting policy that starts each operation as late as possible while meeting the deadlines specified by the starting times of the given steady schedule minimises the start-up period. Finally, we suggest a way of minimising the total makespan by optimising the steady schedule. [ABSTRACT FROM AUTHOR]

Wafer sorting is one of the most critical processes involved in semiconductor device fabrication. This study addresses the wafer sorting scheduling problem (WSSP), with minimisation of total setup time as the primary criterion and minimisation of the number of testers used as the secondary criterion. In view of the strongly NP-hard nature of this problem, a simple and effective iterated greedy heuristic is presented. The performance of the proposed heuristic is empirically evaluated by 480 simulation instances based on the characteristics of a real wafer testing shop-floor. The experimental results show that the proposed heuristic is effective and efficient as compared to the state-of-art algorithms developed for the same problem. It is believed that this study has developed an approach that is easy to comprehend and satisfies the practical needs of wafer sorting. [ABSTRACT FROM AUTHOR]

As a semiconductor supply chain becomes widespread and the competition pressure is very fierce, the detrimental effects of increasing varieties and variations are magnified in the supply chain. But many important issues, such as different service priorities, adaptability, controllability and scalability of performance metrics, have not been addressed in the literature. Conventional modelling techniques of supply chain operations are no longer effective for supply chain configuration. Therefore, a proposed empirical model was first built to catch up the relationship between supply-chain configuration and metrics under the influence of the variability sources. Next, an optimal supply chain configuration model is formulated as a polynomial goal programming model to accommodate different goal objectives. Finally, an efficient solution methodology is further developed to find out the optimal supply chain configuration. Our results show that our proposed approach can easily be adapted to the practices in semiconductor supply chain, and the solution methodology developed in this paper is truly promising. [ABSTRACT FROM AUTHOR]

This paper tackles a large-scale and uncertain scheduling problem of semiconductor wafer fabrication system. Two kinds of uncertainties are considered here, including the machine breakdowns and the fluctuations of processing times. Instead of using the traditional rigid schedule, we propose a novel concept of operation-group-based soft schedule which is used as the new decision variable of the studied problem. The inherent idea of this concept is to make some critical scheduling decisions at the beginning of the scheduling horizon, and allow the remaining decisions to be made during the execution of the initial soft schedule. Furthermore, an operation-group-based soft scheduling approach (OGSSA) is proposed to deal with the uncertainties, which contains an offline optimization layer and an online dispatching layer. In the offline optimization layer, a prediction-based decomposition scheduling method is proposed to generate a soft schedule, and a global scheduling objective prediction model is constructed to evaluate the soft schedule. Then, the initial soft schedule is released to the online dispatching layer, and an online heuristic rule is designed to decide in real time, which operations and when to process. The computational results on the practical production data demonstrate the effectiveness of OGSSA under uncertain production environments. [ABSTRACT FROM AUTHOR]

This paper proposes a system called CDID for diagnosing semiconductor fabrication process. CDID can identify the carry-over defect type that contributed to a defective cluster captured by an in-line inspection tool during a specific fabrication processing step. Let Rx be a defective cluster captured by an in-line inspection tool during the fabrication processing step psi . First, CDID would identify the defect type of Rx by comparing the image of Rx with the images in reference wafer maps of previous defect clusters captured at psi . Let dj be the identified defect type. CDID would use rules of inferences for identifying the root cause of dj . CDID would utilize dj as a trigger for the appropriate defect specification rules using the standard rules of inferences. Based on established and well-known causes of defects, CDID composes rule-based defect specifications in the form of propositional logic’s premises. The premises are triggered by applying the inference rules. By applying the defect specification rules recursively using the inference rules, CDID can identify the root cause of dj . The quality of CDID has been experimentally evaluated by measuring its prediction accuracy. Results revealed marked prediction accuracy. [ABSTRACT FROM AUTHOR]

A robotic cluster tool involves many activities whose time is subject to some disturbance, thus leading to the activity time variation. It results in wafer sojourn time fluctuation in a process module, which may in turn violate wafer residency time constraints. Some wafer fabrication requires a revisiting process. With wafer revisiting, the effect of activity time variation on wafer sojourn time fluctuation is so complicated that no analysis was reported to the best knowledge of the authors. It is vitally important to accurately analyze it. To do so, this paper adopts a Petri net model to describe the dynamical behavior of cluster tools. With this model, a real-time control policy is proposed to offset the effect of the activity time variation on wafer sojourn time fluctuation as much as possible. Then, the wafer sojourn time delay is analyzed and algorithms are developed to calculate its exact upper bound. With the proposed method, one can check if a given schedule is feasible under bounded activity time variation. Some practical examples are given to show the application of the proposed approach. [ABSTRACT FROM PUBLISHER]

Overlay variations occur frequently in lithography process, which should be controlled within the tolerance to guarantee the better pattern resolutions. The operational optimization of overlay aims to predict the unknown overlay variations and compensate them into the wafer production. Due to the uncertain yield, the overlay data for learning are usually incomplete, which makes the overlay optimization very challenging. This paper proposes a novel overlay optimization framework called low-rank manifold optimization (LRMO), which provides new insight to address incomplete overlay data via exploiting low-rank property. First, LRMO can use effectively the correlations from incomplete overlay data, which builds a low-rank model for overlay optimization. In addition, LRMO resorts to Riemannian optimization and designs an efficient algorithm for this low-rank model. The proposed LRMO algorithm analyzes the manifold structure of the overlay data and computes accurate overlay variations with a low computational complexity. The experiments validate that LRMO obtains satisfying performance on the operational optimization of overlay variations. [ABSTRACT FROM AUTHOR]

Fab-level discrete-event simulation is an important practical tool for the analysis and optimization of semiconductor wafer fabricators. In such facilities, a clustered photolithography tool (CPT) is by far the most expensive tool and often the capacity bottleneck. In this paper, we consider linear, affine, flow line, and detailed models of CPTs for use in fab-level simulation. We develop extensions to affine and flow line models and demonstrate exactly how to convert raw CPT data into the various models. Using a detailed CPT model based on industry data as the baseline, numerical experiments are conducted to test the models’ fidelity for cycle time, lot residency time, and throughput. We also compare the computational burden of each model class. Further simulations are conducted to test the models’ robustness to changing fab conditions, e.g., when lot size or train size changes. Flow line models are shown to be more accurate and robust than linear or affine models and require approximately 200 times less computation than detailed models. [ABSTRACT FROM AUTHOR]

In this paper, a supply chain simulation testbed for the semiconductor industry is proposed. We start by identifying requirements for such reference datasets, and then we identify the main building blocks. The nodes of the supply chain that represent semiconductor wafer fabrication facilities (wafer fabs) are built on a simulation model from the measurement and improvement of manufacturing capacity project. We present two techniques to reduce the modeling and computational burden that are able to deal with load-dependent cycle times in single front-end and back-end facilities and in the overall network. The first method models in detail only the bottlenecks in the nodes of the supply chain, while the second one uses empirical distributions for cycle time and throughput. The quality of these reduction techniques is assessed by comparing the detailed model and the models with a reduced level of detail. We present an application scenario for the testbed by simulating a semiconductor supply network. In addition, the usage of the testbed is discussed. [ABSTRACT FROM PUBLISHER]

Motivated by applications to root-cause identification of faults in multistage manufacturing processes that involve a large number of tools or equipment at each stage, we consider multiple testing in regression models whose outputs represent the quality characteristics of a multistage manufacturing process. Because of the large number of input variables that correspond to the tools or equipments used, this falls in the framework of regression modeling in the modern era of big data. On the other hand, with quick fault detection and diagnosis followed by tool rectification, sparsity can be assumed in the regression model. We introduce a new approach to address the multiple testing problem and demonstrate its advantages over existing methods. We also illustrate its performance in an application to semiconductor wafer fabrication that motivated this development. Supplementary materials for this article are available online. [ABSTRACT FROM AUTHOR]

A semiconductor wafer undergoes various processing steps before it is transformed from a plain silicon wafer to one populated with thousands of integrated circuits. Each of these processing steps is susceptible to specific types of defects. Some defects may not be captured by in-line inspection tools or may not be sampled during defect review-scanning electron microscope and are carried over multiple processing steps. Such defects can be discovered at the end of the fabrication procedure, which requires process engineers to trace back the manufacturing processes that caused these defects. Despite the success of most current methods that detect defects during wafer fabrication, most of these methods are inable to accurately associate the source of an individual defect type to a specific semiconductor processing step. We believe that this limitation can be overcome by considering the carry-over of defect signatures rather than individual defects. We propose in this paper a system called step-defect contribution analyzer (SDCA) that detects defect signatures on semiconductor wafers and overcomes the limitations outlined above. SDCA allows process engineers to trace back and associate the source of a final defectivity discovered at the end of the fabrication procedure to specific defect signatures carried over multiple process zones. We experimentally evaluated the quality of SDCA by measuring its prediction accuracy. Results revealed marked prediction accuracy. [ABSTRACT FROM PUBLISHER]

Transition from 300 to 450 mm wafer fabrication is the current trend in the semiconductor industry due to the benefits of higher productivity and lower production cost. However, the increased size and weight of 450 mm wafers will cause handling and transport problems, which prompts the need of an effective and capable automated material handling system (AMHS). Some researchers have proposed using conveyor-based AMHS as the next-generation transport means for 450 mm wafer fabrication. However, the lack of effective dispatching rules will make a conveyor-based AMHS to remain suffering traffic-jam problems and unable to prioritize lots to meet customer needs. In this research, a dispatching rule called 'heuristic preemptive dispatching rule using stocker (HPDS)' is proposed to control wafer movements in a conveyor-based AMHS for 450-mm wafer fabrication. Simulation has been conducted and the results showed the HPDS outperformed the differentiated preemptive dispatching (DPD) in terms of average variable time that includes block and waiting times. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing companies have constructed large fabs to enhance their competitive advantage. A large fab has many advantages, such as low cost, short cycle time and flexibility. Nevertheless, the advantages from the expansion of production capacity are not infinite, and a large fab scale increases the risk of production management. This work presents a model to determine the best capacity scale, where the production performance and cost are the major factors. Previous simulation experiments demonstrated that increasing the capacity scale improves the production cycle time significantly only when the utilization of the bottleneck machine is fixed. Therefore, the product cycle time is the major production performance index to determine the capacity scale of a fab. The GI/G/m queuing model is applied to build up the queue time equations of the bottleneck machine. Moreover, differentiation is used to find the number of bottleneck machines with queue times below the minimum required. The optimal number of bottleneck machines can be set based on the calculation result. Based on the performance result, the equipment cost per wafer can be taken into account for the final capacity scale determination. Additionally, an example is described and a simulation model is developed to validate the proposed model. [ABSTRACT FROM AUTHOR]

A key parameter of the linear programming (LP) models widely used for production planning in industry and academia are the lead times, the estimated delay between material becoming available to a resource and its completion at that resource. Lead times are commonly treated as exogenous, workload-independent parameters and assumed to be integer multiples of the planning period. Although formulations with non-integer lead times have been implemented in industry, we are unaware of any studies systematically evaluating their performance. In this paper, we compare the performance of LP models with and without non-integer lead times by simulating the execution of the resulting release plans. We also compare their performance to that of a formulation incorporating workload-dependent lead times using nonlinear clearing functions. We find that the performance of the models with non-integer lead times is substantially better than those with integer lead times, and often superior to that of the much more complex clearing function models. These results suggest that whenever reasonable estimates of the lead times are available, non-integer lead times should be used due to their simplicity of implementation and excellent performance. [ABSTRACT FROM AUTHOR]

Estimating job cycle time is an important task for a semiconductor manufacturer as it helps to strengthen relationships with customers and is also conducive to the sustainable development of the manufacturer. The research trend in this field has moved toward the development of hybrid methods, especially those that are classification-based. Most existing methods use pre-classification; however, such methods have several drawbacks, such as incompatibility with the estimation method and unequal sizes of different job groups. In contrast, a post-classification approach has great potential, and therefore is used as a basis for the new approach in this study. In the proposed methodology, a systematic procedure is established to divide jobs into several groups according to their estimation errors. In this way, the classification and estimation stages can be combined seamlessly because they optimize the same objectives. A real case is used to evaluate the effectiveness of the proposed methodology and the experimental results support its superiority over several existing methods. The shortcomings of the existing methods based on pre-classification are also clearly illustrated. [ABSTRACT FROM AUTHOR]

In semiconductor manufacturing, production ramp-up is a necessary phase before a new technology is introduced because it affects not only the time-to-market, but also the time-to-volume (the time to reach mass production). In production ramp-up, engineering lots are implemented in order to collect data for product and equipment qualification, and they are expected to achieve short cycle times (CTs) and high throughputs. On one hand, the increment of the amount of engineering lots will disrupt the smoothness of the manufacturing flow and cause work-in-process (WIP) bubbles. On the other hand, to ensure the feasibility of the production plan, some throughput and CT targets must be achieved. There is a need to determine an appropriate wafer start mix to strike a balance between the conflicting objectives. However, the complexity and stochasticity existing in the semiconductor manufacturing process makes it a very difficult task. This paper modeled the wafer start mix determination problem and proposed an efficient methodology, called progressive simulation optimization (PSO), based on the simulation metamodeling techniques to handle this problem. The goal was to find the optimal wafer start mix that enables maximum throughput of engineering lots, while satisfying the requirement of CT of normal lots (NL). A numerical study was conducted to evaluate the performance of the proposed PSO, and an empirical study based on real data was conducted to validate the viability of the proposed methodology in practice. [ABSTRACT FROM PUBLISHER]

In this paper, we discuss scheduling problems motivated by a real-world production setting found in 300-mm semiconductor wafer fabrication facilities (wafer fabs). Front opening unified pods (FOUPs) transfer wafers in 300-mm wafer fabs. Several orders can be grouped in one FOUP. We study lot and single item processing environments. The total weighted tardiness (TWT) and the weighted number of tardy orders (WNTO) objectives are considered. Mixed integer programming (MIP) formulations are presented for the scheduling problems. We prove that the researched scheduling problems are NP-hard. Grouping genetic algorithms (GGAs) are proposed to form the content of the FOUPs. We compare the performance of the GGAs with another GA from the literature available for the problem with TWT measure based on randomly generated problem instances. It turns out that the GGA outperforms the heuristic from the literature for both environments. For the WTNO measure, we assess the performance of the GGA approach using MIP formulations for small-size problem instances and a GA-based heuristic for large-size problem instances. Again, the GGA performs well with respect to solution quality and amount of computing time. [ABSTRACT FROM AUTHOR]

Because of the high requirement for quality, the surfaces of prime wafers have to be flat and without damages. During the first machining process in wafer manufacturing, the defects introduced by wire sawing must be removed by the subsequent lapping, grinding, and polishing processes. Therefore, the quality of sliced wafer is very important. Fixed diamond wire saw, on which the diamond grains are coated as abrasives, has become the major tool to slice ingot into wafers. Ductile-regime machining is an attractive process to achieve crack free surface on brittle materials in abrasive machining process. The depth of cut of the abrasive is a hint for the transition between ductile- and brittle-regime machining. In order to understand the cutting behavior in fixed diamond wire sawing, this paper presents an investigation of depth of cut per abrasive based on the wire profile model developed by the authors. The simulation results show that the larger depths of cut are unavoidable in fixed diamond wire sawing because of the random position and size distribution of diamond grains on the wire. Although the number of active abrasives and the depths of cut at the bottom of slicing groove are larger than those at the side of the groove, few larger diamond grains may introduce larger depths of cut and cracks on the side, which is the sliced wafer surface. Effects of process parameters to the depth of cut distributions are also analyzed. The variation in number of active abrasives in cutting zone as well as their depth of cut shows the possibility to increase process productivity without increasing the depths of cut of the diamond grains. Consequently, the surface quality could be remained without further deterioration. [ABSTRACT FROM AUTHOR]

In semiconductor manufacturing, wafer fabrication is followed by chip assembly where individual dies are assembled as a packaged chip. In between, dies are tested in terms of their electrical properties and those which fail to pass the “wafer test” are filtered out. However, some faulty dies pass the test and cause a packaged chip to fail in the final test. The inaccuracy of the wafer test leads to waste in manufacturing time and cost. In this paper, we propose to predict the result of the final test at the die-level before assembly using wafer test items and four derivations concerning wafer map features: 1) distance of the die from the wafer center; 2) previous final yield at the die position; 3) wafer test fail rate for the adjacent dies; and 4) abnormalities of the wafer map pattern. We build prediction models with these variables using a random forest algorithm. Preliminary experimental results on actual data show that the use of these derived variables improves the prediction performance with a statistical significance, thus merits further investigation. [ABSTRACT FROM AUTHOR]

Scheduling for wafer fabrication of advanced technology nodes entails complicated constraints such as limited waiting times. Focusing on real settings, this paper aims to develop a novel genetic algorithm of multi-subpopulation parameters with hybrid estimation of distribution (MSPHEDA) to solve the present problem effectively and efficiently. To estimate the validity of this approach, ten scenarios were simulated on the basis of empirical data as the basis to compare the performance of MSPHEDA and other heuristic methods for minimizing makespan and reducing the total exceeded limited waiting time. The results have shown practical viability of the proposed approach. [ABSTRACT FROM AUTHOR]

Discrete-event simulation is a well-established and rather successful method in some semiconductor companies, while other companies do not use simulation at all. Simulation is used for performance assessment and decision-making. This paper focuses on the methodological and practical issues that have to be addressed to build, use, and maintain simulation models for a semiconductor wafer fabrication facility (wafer fab). We describe and discuss the main steps of a simulation study in this domain. We seek to highlight the main issues and present alternative ways to address them. Common pitfalls in using discrete-event simulation in semiconductor manufacturing and how they can be avoided are also discussed. [ABSTRACT FROM AUTHOR]

As a clustered photolithography tool (CPT) in semiconductor wafer manufacturing can cost as much as US$100 million, it must be operated efficiently. To maximize throughput, wafers are generally admitted to a CPT opportunistically, that is, as soon as they are available and the tool can accept them. Here, our goal is to develop release methods that retain throughput but increase manufacturing agility. As Petri net methods prove intractable, we develop a heuristic based on the use of flexible flow line models for the CPT. Such models are appropriate when the tool throughput for each class of wafers is dictated by the bottleneck process time plus unavoidable robot handling overhead. The heart of the heuristic is a lexicographic multiple objective linear program (LMOLP). It first ensures that wafers exit the tool as early as possible and subsequently delays the wafer admission to minimize the mean residency time. [ABSTRACT FROM PUBLISHER]

Some wafer fabrication processes require a wafer to visit some processing modules in a cluster tool multiple times, leading to a wafer revisiting process. They may pose wafer residency time constraints, i.e., a wafer can stay in a module for a limited time after it is processed. Although techniques exist for scheduling cluster tools with either wafer residency time constraints or wafer revisiting, it is much more challenging to schedule tools with both of them. Considering that atomic layer deposition is a typical wafer revisiting process, this paper intends to schedule a dual-arm cluster tool dealing with it. Based on the analysis of such a tool’s properties, a novel scheduling strategy called modified 1-wafer cyclic scheduling is derived. With this strategy, necessary and sufficient schedulability conditions are presented. If schedulable, highly efficient scheduling algorithms are developed to obtain a feasible and optimal schedule together with a way to implement the obtained one. Illustrative examples are given to show the application of the proposed approach. [ABSTRACT FROM PUBLISHER]

Semiconductor enterprises should continue to provide more capacity to meet the demands of the highly competitive semiconductor markets. Photolithography is usually the bottleneck process with the most expensive equipment in a semiconductor wafer fabrication system. Usually, photolithography area controls the performance of whole semiconductor manufacturing system. To improve the performances of the photolithography area with dynamic dispatching combination rules, a dynamic scheduling method based on Kohonen neural network (KNN) was proposed in this paper. A dynamic scheduling framework is also proposed. The method has been integrated into the dynamic scheduling framework. A KNN-based sample learning algorithm for selecting best combination rules is presented. Finally, the results of simulation experiments indicate that the proposed method is effective and feasible in real-time scheduling of semiconductor fabrication system under both closed-loop release policy and open-loop release policy. [ABSTRACT FROM AUTHOR]

While flow line models have been studied for decades, excepting some cases with three servers or less, their equilibrium probabilities remain elusive. As such, approximations based on aggregation or decomposition methods are generally employed. In this paper, by focusing on flow lines with deterministic service durations and a renewal arrival process, we develop exact methods for steady-state analysis. Our starting point is the investigation of recursions for customer delay based on exact decomposition methods. We demonstrate that the delay a customer faces in each server possesses a Markovian property. For discrete-time flow lines, we obtain a multidimensional discrete-time time-homogeneous Markov chain for the delays; there are an infinite number of balance equations for the equilibrium probabilities. Exploiting a similarity between our system and the GI/D/1 queue allows us to reduce these to a finite number of balance equations that can be solved numerically. We also investigate the implications for continuous-time flow lines and consider an example inspired by production time windows in semiconductor manufacturing. To our knowledge, these are the first results that allow one to exactly obtain the equilibrium probabilities in flow lines consisting of more than three servers. [ABSTRACT FROM PUBLISHER]

Estimating the cycle time of a job is meaningful in many ways for managing a wafer fabrication factory (wafer fab). However, this estimation is not easy, due to the complexity and uncertainty of the wafer fabrication environment. Recently, a number of hybrid methods have been proposed to improve the accuracy of estimating the cycle time of a job. Most of these methods used job classification, especially pre-classification. Among these methods, several were based on post-classification and achieved even better performances. Such post-classification-based methods were improved in this study by considering the required parameter adjustment instead of the estimation error. Thus, it is possible to classify jobs into more than two categories at the same time. From the view of neurocomputing, this study established a systematic and effective procedure to divide the input examples to an artificial neural network into several parts that can be better handled by different artificial neural networks. A real case was also used to illustrate the applicability of the proposed methodology. The effectiveness of the proposed methodology over several existing methods has been confirmed by statistical tests. [ABSTRACT FROM AUTHOR]

A multi-cluster tool is composed of a number of individual cluster tools linked by buffering modules (BMs). The capacity of a BM can be one or two. Aiming at finding an optimal one-wafer cyclic schedule, this paper explores the effect of two-space BMs on the performance of a multi-cluster tool. A Petri net (PN) model is developed to model it by extending resource-oriented PNs. The dynamic behavior of robot waiting and tasks, process modules, and buffers is well described by the model. This paper shows that there is always a one-wafer cyclic schedule that reaches the lower bound of the cycle time of a process-bound tool. Furthermore, a closed-form algorithm is revealed to find such a schedule for the first time for such multi-cluster tools. Illustrative examples are given to show the application and power of the proposed method. [ABSTRACT FROM AUTHOR]

Jet and Flash Imprint Lithography has proven to be a viable alternative to optical lithography for fabrication of sub 30nm nanostructures for large volume semiconductor manufacturing. Machine throughput, overlay and process defectivity that meet and exceed the International Technology Roadmap for Semiconductors (ITRS) are essential for commercial viability of any new lithography technology. Jet and Flash Imprint Lithography uses an inkjet head to dispense a grid of liquid drops on the wafer surface to match the volume requirements of the pattern being imprinted. Wafer shape modulation has been shown to increase imprinting speed significantly by reducing air bubble trapping in the drop interstitial sites. A wafer shape modulation chuck that can address arbitrary field locations and sizes on a wafer with a novel actuation scheme that minimizes the number of actuators while increasing imprinting speed and reducing process defects significantly is presented. [ABSTRACT FROM AUTHOR]

During semiconductor manufacturing process, massive and various types of interrelated equipment data are automatically collected for fault detection and classification. Indeed, unusual wafer measurements may reflect a wafer defect or a change in equipment conditions. Early detection of equipment condition changes assists the engineer with efficient maintenance. This study aims to develop hierarchical indices for equipment monitoring. For efficiency, only the highest level index is used for real-time monitoring. Once the index decreases, the engineers can use the drilled down indices to identify potential root causes. For validation, the proposed approach was tested in a leading semiconductor foundry in Taiwan. The results have shown that the proposed approach and associated indices can detect equipment condition changes after preventive maintenance efficiently and effectively. [ABSTRACT FROM AUTHOR]

To maintain competitive advantages, semiconductor industry has strived for continuous technology migrations and quick response to yield excursion. As wafer fabrication has been increasingly complicated in nano technologies, many factors including recipe, process, tool, and chamber with the multicollinearity affect the yield that are hard to detect and interpret. Although design of experiment (DOE) is a cost effective approach to consider multiple factors simultaneously, it is difficult to follow the design to conduct experiments in real settings. Alternatively, data mining has been widely applied to extract potential useful patterns for manufacturing intelligence. However, because hundreds of factors must be considered simultaneously to accurately characterize the yield performance of newly released technology and tools for diagnosis, data mining requires tremendous time for analysis and often generates too many patterns that are hard to be interpreted by domain experts. To address the needs in real settings, this study aims to develop a retrospective DOE data mining that matches potential designs with a huge amount of data automatically collected in semiconductor manufacturing to enable effective and meaningful knowledge extraction from the data. DOE can detect high-order interactions and show how interconnected factors respond to a wide range of values. To validate the proposed approach, an empirical study was conducted in a semiconductor manufacturing company in Taiwan and the results demonstrated its practical viability. [ABSTRACT FROM AUTHOR]

With the rapid change of manufacturing environments, semiconductor fabricators are forced to make continuous investments in advanced technology to maintain their competitive advantage. Wafer fabrication (fab) performance evaluations are important for examining past operations such as the capacity and resource allocation. In addition, forecasting provides useful information for what-if analyses to anticipate useful strategies early to avoid potential losses. However, the integration of performance evaluation and forecast based on a consideration of the relative performance along the time horizon has rarely been addressed. In particular, the part of performance evaluation is to generate the relative performance in a period with rolling data. Then, the forecast part is to build a model for performance prediction based on the result of present performance. This study aimed to construct a performance forecast model by integrating data envelopment analysis and a back-propagation neural network for performance evaluation and forecast, respectively. Empirical data from a leading semiconductor company in Taiwan was used to test the proposed model. The results provide basic information and early alarms to adjust the resource allocation before the future performance declines. The empirical analysis demonstrated the practical feasibility of the proposed approach. [ABSTRACT FROM AUTHOR]

Purpose – This paper aims to investigate the changes in tensile properties of novel functionally graded materials (FGMs) and wafer structures created by direct metal deposition (DMD) additive manufacturing (AM) technology. Design/methodology/approach – Laser-assisted DMD was used to create two innovative sets of metallic structures – the functionally graded and wafer-layered structures – using pairs of six different engineering alloys in different combinations. These alloys were selected due to their high popularity within a diverse range of industries and engineering applications. The laser-assisted DMD was selected as a suitable technique to create these complex structures because of its capability to deposit more than one alloy powder at a time. After creation of these structures, their tensile strength was tested in a series of tensile tests and the results were compared with those of single alloy samples. Findings – It was observed that the mechanical properties of FGMs and wafer structure samples were clearly different from those of the single alloy samples, a fact which creates a whole pool of opportunities for development of new materials or structures with desired mechanical properties that cannot be achieved in single alloy parts. Originality/value – The study demonstrates the application of the DMD process to produce unique structures and materials, which would be high in demand in engineering applications, where metallic parts are exposed to high loads and where excessive tensile stresses may adversely affect the performance of such parts. [ABSTRACT FROM AUTHOR]

The article presents case studies related to the indent-and cleaving method developed by LatticeGear LLC, cleaving solutions provider for semiconductor industry. Topics discussed include effectiveness of the method as compare to manual cleaving, factors related to the scribe-and-cleaving method and sample-preparation success through the indent-and-cleaving technique. Several tables are also presented related to the comparison of the methods.

We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 x 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm²/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm²/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes. [ABSTRACT FROM AUTHOR]