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Solid-state qubits integrated on semiconductor substrates currently require at least one wire from every qubit to the control electronics, leading to a so-called wiring bottleneck for scaling. Demultiplexing via on-chip circuitry offers an effective strategy to overcome this bottleneck. In the case of gate-defined quantum dot arrays, specific static voltages need to be applied to many gates simultaneously to realize electron confinement. When a charge-locking structure is placed between the quantum device and the demultiplexer, the voltage can be maintained locally. In this study, we implement a switched-capacitor circuit for charge-locking and use it to float the plunger gate of a single quantum dot. Parallel plate capacitors, transistors, and quantum dot devices are monolithically fabricated on a Si/SiGe-based substrate to avoid complex off-chip routing. We experimentally study the effects of the capacitor and transistor size on the voltage accuracy of the floating node. Furthermore, we demonstrate that the electrochemical potential of the quantum dot can follow a 100 Hz pulse signal while the dot is partially floating, which is essential for applying this strategy in qubit experiments.

Electrons and holes confined in quantum dots define an excellent building block for quantum emergence, simulation, and computation. In order for quantum electronics to become practical, large numbers of quantum dots will be required, necessitating the fabrication of scaled structures such as linear and 2D arrays. Group IV semiconductors contain stable isotopes with zero nuclear spin and can thereby serve as excellent host for spins with long quantum coherence. Here we demonstrate group IV quantum dot arrays in silicon metal-oxide-semiconductor (SiMOS), strained silicon (Si/SiGe) and strained germanium (Ge/SiGe). We fabricate using a multi-layer technique to achieve tightly confined quantum dots and compare integration processes. While SiMOS can benefit from a larger temperature budget and Ge/SiGe can make ohmic contact to metals, the overlapping gate structure to define the quantum dots can be based on a nearly identical integration. We realize charge sensing in each platform, for the first time in Ge/SiGe, and demonstrate fully functional linear and two-dimensional arrays where all quantum dots can be depleted to the last charge state. In Si/SiGe, we tune a quintuple quantum dot using the N+1 method to simultaneously reach the few electron regime for each quantum dot. We compare capacitive cross talk and find it to be the smallest in SiMOS, relevant for the tuning of quantum dot arrays. These results constitute an excellent base for quantum computation with quantum dots and provide opportunities for each platform to be integrated with standard semiconductor manufacturing., Main text: 8 pages, 6 figures. Supporting Info: 5 pages, 3 figures

We investigate the structural and quantum transport properties of isotopically enriched Si28/SiO228 stacks deposited on 300-mm Si wafers in an industrial CMOS fab. Highly uniform films are obtained with an isotopic purity greater than 99.92%. Hall-bar transistors with an oxide stack comprising 10 nm of Si28O2 and 17 nm of Al2O3 (equivalent oxide thickness of 17 nm) are fabricated in an academic cleanroom. A critical density for conduction of 1.75×1011cm-2 and a peak mobility of 9800cm2/Vs are measured at a temperature of 1.7 K. The Si28/SiO228 interface is characterized by a roughness of Δ=0.4nm and a correlation length of Λ=3.4nm. An upper bound for valley splitting energy of 480μeV is estimated at an effective electric field of 9.5 MV/m. These results support the use of wafer-scale Si28/SiO228 as a promising material platform to manufacture industrial spin qubits.