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This article presents two principles that make multiple time coding lines (TCLs)-based time-to-digital converter (TDC) implementation in field-programmable gate array (FPGA) device more efficient. A pseudo-segmented delay line allows for saving many logical resources by effective utilization of programmable logic block elements. A chopped TCL improves measurement resolution and precision and takes advantage of a global clock network skew. Both designs were implemented in a Kintex-7 FPGA chip, manufactured by Xilinx in 28-nm CMOS process, and compared to well-known TCL solutions, that is, a commonly used “plain” architecture and a tuned delay line. All four designs, working in a single and multiple configurations, were tested and compared in terms of resource utilization, measurement resolution, and precision. Designed TDCs employed in a one channel timestamps-based interpolating time counter allowed to get mean resolution of 1 ps and precision even below 4 ps using up to ten TCLs.

Nowadays state-of-the-art time-to-digital converters (TDCs) are commonly implemented in field-programmable gate array (FPGA) devices using different variations of the wave union method. To take full advantage of this method many design challenges need to be overcome, one of which is an efficient data encoding. In this work, we describe in detail an effective algorithm to decode raw output data from a newly designed multisampling wave union TDC. The algorithm is able to correct bubble errors and detect any number of transitions, which occur in the wave union TDC output code. This allows us to reach a mean resolution as high as 0.39 ps and a single shot precision of 2.33 ps in the Xilinx Kintex-7 FPGA chip. The presented algorithm can be used for any kind of wave union TDCs and is intended for partial hardware implementation.

This article presents an idea, design and test results of a new time-to-digital converter (TDC) implemented in an FPGA device. The high resolution of 13 ps and measurement range of 3.4 ns are achieved based on a two-stage time interpolation (TI). In the first and second stages of the TI we have used the Vernier delay line and a single tapped delay line, respectively. This solution provides respectable metrological parameters without the need to use a clock signal, and significantly saves the logical resources of an integrated circuit (IC). The proposed method, generally based on two different variants of the discrete delay line, is easy to design and implement in digital ICs. For experimental verification, the TDC was implemented in a single programmable device from family Virtex-7 (Xilinx).

The wave union is a one of the most popular method implemented recently in programable devices for precise measurements of time intervals. Due to the excellent metrological parameters provided by this method, it is used in different variants in both FPGA and ASIC devices. In this paper we present an in-depth analysis focused exclusively to this method. Various implementations are compared and general conclusions are formulated.

A novel time-to-digital converter principle is presented that introduces multisampling capability to the wave union method. The design employs two wave union launchers for both start and stop signals. For test purposes the converter was implemented in Kintex-7 FPGA device (Xilinx). During the initial experimental verification a mean resolution (LSB) of up to 0.7 ps and precision even below 4.7 ps (RMS resolution better than 3.3 ps) were achieved. The design is FPGA logic resource saving comparing to similar solutions but requires much effort during implementation and data encoding.

A new time interval/frequency generator with a jitter below 5 ps is described. The time interval generation mechanism is based on a phase shifting method with the use of a precise DDS synthesizer. The output pulses are produced in a Spartan-6 FPGA device, manufactured by Xilinx in 45 nm CMOS technology. Thorough tests of the phase shifting in a selected synthesizer are performed. The time interval resolution as low as 0.3 ps is achieved. However, the final resolution is limited to 500 ps to maximize precision. The designed device can be used as a source of high precision reference time intervals or a highly stable square wave signal of frequency up to 50 MHz.

This paper presents a time-to-digital converter (TDC) with pseudo-segmented delay line implemented in 28 nm field-programmable gate array (FPGA) device (Kintex-7 XC7K160T, Xilinx). The TDC employs a carry chain based delay line wherein each tap is connected to multiple flip-flops. Proposed solution gives the same measurement resolution and comparable precision improvement as using multiple time coding lines (TCL) but allows to save logical resources available in FPGA chip. The TDC was tested in timestamps based time interval counter operating at 700 MHz clock and provides 1.1 ps resolution and 5 ps precision.

A high-resolution time interval digitizer based on a novel method of averaging the width of a cyclically repeated pulse is described. Information about the measured time interval is contained in the width of a pulse that circulates in a discrete delay loop and is measured by counting with the use of a high frequency multiphase clock. Such a digitizer implemented in a programmable device Cyclone (Altera) resulted in the high resolution of 8.7 ps and the measurement uncertainty of 30.4 ps within the measurement range of 13.5 ns. Both the resolution and precision may be controlled relatively easily and independently on microelectronic technology used.

This paper presents the design, operation and test results of an integrated time digitizer (TD) that operation principle is based on counting of clock periods and multiphase in-period interpolation. The 720 MHz clock signal used as a time base provides 1.39 ns coarse timing resolution that is improved in the interpolation stage to 43 ps as a result of employing 32-phase clock. The digitizer is implemented in a versatile Field- Programmable Gate Array (FPGA) device (Kintex-7, 28 nm CMOS, Xilinx). Both the conversion method involved and technological platform used provide possibility of adjusting main TD’s parameters due to customer needs, so the measurement range (1.49 s) can be easily extended by increasing the capacity of binary counter, while the further improvement in resolution may be obtained by multiplication of clock phases. Moreover, due to timestamping method applied for registering of input events the number of measurement channels may also be customized.

We presents the design and test results of a picosecond-precision time interval measurement module, integrated as a System-on-Chip in an FPGA device. Implementing a complete measurement instrument of a high precision in one chip with the processing unit gives an opportunity to cut down the size of the final product and to lower its cost. Such approach challenges the constructor with several design issues, like reduction of voltage noise, propagating through power lines common for the instrument and processing unit, or establishing buses efficient enough to transport mass measurement data. The general concept of the system, design hierarchy, detailed hardware and software solutions are presented in this article. Also, system test results are depicted with comparison to traditional ways of building a measurement instrument.

We present the design, operation, and test results of a new integrated time interval (TI) counter that provides high resolution (1.9 ps), low measurement uncertainty (below 4.5-ps rms in advanced measurement modes), and wide measurement range (above 1 h, easily extendable). Fundamental for the counter, TI measurements are simultaneously performed in eight independent channels, while the advanced configuration of input channels improves either the precision (up to 3 ps) or the measurement speed (up to $91.2 \times 10^{6}$ registered events/s). The functional flexibility and high speed are achieved based on the timestamp (TS) principle that makes possible registering on the common time scale events appearing at counter inputs and then measuring the time intervals between any registered events. The high precision is obtained by employing two-stage inner interpolation with an eight-phase clock in the first stage of interpolation and an equivalent time coding delay line in the second one. The time counter is integrated in a single, cost-effective field programmable gate array chip manufactured in a 28-nm CMOS process.

We present the design, implementation, and test results of an integrated time digitizer based on a new conversion method that applies multiedge coding in independent coding lines. The proposed method eliminates an existing technological limitation of resolution inherent in the methods based on standard time coding delay lines, which causes that the value of resolution cannot be lower than the propagation time of the fastest delay element in the line. The developed method allows increasing the resolution proportionally to the number of signal edges coded and lines involved. An interpolating time counter designed by applying the six-edge coding in three independent coding lines provides subpicosecond resolution (902 fs), high precision (

A new field-programmable gate array (FPGA) based digital-to-time converter (DTC) is described that has a unique feature of pulse train generation with very high resolution. As a proof of concept the DTC design was implemented in Spartan-6 FPGA device (45 nm CMOS, Xilinx). The converter generates either absolute delay related to trigger signal or pulse sequence with variable relative delays between pulses. In both cases the resolution of delays is about 20 ps. The time interval between two pulses is generated with jitter below 4.5 ps. An important advantage of the design is also relatively easy implementation.

This paper presents the design, implementation, and test results of a multichannel time interval and frequency counter developed as a desktop instrument. The counter contains four main functional modules for (1) performing precise measurements, (2) controlling and fast data processing, (3) low-noise power suppling, and (4) supplying a stable reference clock (optional rubidium standard). A fundamental for the counter, the time interval measurement is based on time stamping combined with a period counting and in-period two-stage time interpolation that allows us to achieve wide measurement range (above 1 h), high precision (even better than 4.5 ps), and high measurement speed (up to 91.2 × 106 timestamps/s). The frequency is measured up to 3.0 GHz with the use of the reciprocal method. Wide functionality of the counter includes also the evaluation of frequency stability of clocks and oscillators (Allan deviation) and phase variation (time interval error, maximum time interval error, time deviation). The 8-channel measurement module is based on a field programmable gate array device, while the control unit involves a microcontroller with a high performance ARM-Cortex core. An efficient and user-friendly control of the counter is provided either locally, through the built-in keypad or/and color touch panel, or remotely, with the aid of USB, Ethernet, RS232C, or RS485 interfaces.

We present the design, operation and test results of a time-to-digital converter based on multiphase clock and implemented in Kintex-7 FPGA (Xilinx). Proposed solution involves a Vernier delay line constructed with the use of Look-Up Tables and interconnect resources. Taking advantage of rising amount of available interconnect resources in modern FPGA devices a various number of phase segments in multiphase clock can be obtained with relatively high uniformity. The solution with 6, 8, 13 and 15 phases is presented and full PVT variation tests are performed and discussed.

We present the design and test results of a new time-to-digital converter based on the cyclic pulse shrinking method and implemented in a field-programmable gate array (FPGA) device. The pulse shrinking is realized in a loop containing two complementary delay lines. The first line shrinks, and the second line stretches the duration time of a circulating pulse; hence, the length ratio of the lines determines the pulse-shrinking capability of the converter. This resolution control mechanism is different from the bias adjustment typically used in complementary metal-oxide-semiconductor (CMOS) application-specific integrated circuit (ASIC) pulse-shrinking elements. Two forms of representation of a measured time interval (the pulse width and the time interval between two pulses) are utilized in the described converter to improve the efficiency of resolution control. To diminish the jitter of the edges of a circulating pulse and, consequently, to increase the precision of the converter, a two-stage conversion is introduced. The first stage, having a low resolution, rapidly shortens the measured pulse, thus limiting the number of cycles, whereas the second stage provides a final high resolution within a narrow time interval range. The optimal resolution of the first conversion stage is theoretically derived. Mostly, the same logical resources of the FPGA device are utilized in both conversion stages; thus, the overall area overhead of the converter is reduced. The converter has a resolution of 42 ps and a measurement uncertainty of below 56 ps within the measurement range of 11.5 ns. The converter has been implemented in a general-purpose reprogrammable device Spartan-3 (Xilinx).

We present a design, FPGA-based implementation and test results of a new three-channel time interval counter developed for a project called Legal Time Distribution System (LTDS). The main aim of the counter is to gather information about time drift of clocks involved into the LTDS, then to evaluate their stability, and finally to select the most stable one as a local clock. The counter provides a high measurement precision ( 1s) that are obtained by combining period counting with two-stage time interpolation. The time counter is implemented in a universally available and relatively cheap programmable device from family Spartan-6 (Xilinx).

The paper describes a new method for time-to-digital conversion that allows achieving the conversion resolution far below the propagation time of the fastest delay buffer in integrated circuit (IC). The method is a combination of the multi-edge time coding and time digitization in independent coding lines. The implementation of such combination and assessment of its effectiveness are the main aims of this research. The article also describes the main design issues that were solved during the implementation of method in an FPGA device. They include: the generation of a pattern square signal with a certain amount of edges and possibly minimal delays between them, the elimination of bubble errors and reduction of internal interferences in IC.

This paper presents the design, operation and test results of a modular multichannel time interval counter built with the use of programmable devices. Its resolution is below 45 ps and the measurement range reaches 1 s. The counter contains 6 independent measurement modules, each built with the use of precise time counter implemented in a single FPGA (Field Programmable Gate Array) device Spartan-3 (Xilinx). To obtain both high precision and wide measurement range the counting of periods of a reference clock is combined with the two-stage interpolation within a single period of clock signal [1]. The interpolation involves a four-phase clock in the first interpolation stage and a time coding line in the second interpolation stage [2]. Modular architecture of the time counter increases its versatility and reliability. The measurement precision of device model is better than 150 ps in a full measurement range. As the acid test the time differences between signals of 1 PPS (Pulse Per Second) from tested clock sources and the reference 1PPS signal was also performed.

We present the design, implementation and test results of an integrated time-to-digital converter based on a new method with multi-edge coding in independent coding lines. The method allows to achieve high resolution below 1 ps and short conversion time of about 3 ns. When used in an interpolation time counter it provides standard measurement uncertainty below 6 ps. The converter has been implemented in a readily available and cheap programmable device Spartan-6 (Xilinx). Applying a multiple coding for time digitization in independent coding lines let us decrease the number of parallel coding lines needed to obtain the same high resolution by averaging. This leads to significant reduction of required logical resources of programmable device. Additionally, the high rate of conversion (above 1 million conversions per sec.) has been achieved.

This paper describes the design and test results of time interval counter featuring the single-shot precision of 7.5 ps root mean square (rms) and measurement range of 1 ms. These parameters have been achieved by combining direct counting method with a two-stage interpolation within a single clock period. Both stages of interpolation are based on the use of tapped delay lines stabilized by delay locked loop mechanism. In the first stage, a coarse resolution is obtained with the aid of high frequency multiphase clock, while in the second stage a sub-gate delay resolution is achieved with the use of differential delay line. To reduce the nonlinearities of conversion and to improve the precision of measurement, a novel segmented delay line is proposed. An important feature of this segmented delay line is partial overlapping of measurement range and resulting enhancement of both resolution and precision of time interval counter. The maximum integral nonlinearity error of the fine-stage interpolators does not exceed 16 ps and 14 ps in START and STOP interpolators, respectively. These errors have been identified by statistical calibration procedure and corrected to achieve single-shot precision better than 7.5 ps (rms). The time counter is integrated in a single ASIC (Application Specific Integrated Circuit) chip using a standard cost-effective 0.35 μm CMOS (Complementary Metal Oxide Semiconductor) process.

A new design of fully integrated time counter is presented for application in laser ranging systems with 3 cm resolution. The counter is implemented on a single FPGA chip with amorphous antifuse structures. The counter contains two time-to-digital converters, each having 200 ps resolution least-significant bit (LSB) within a 10 ns range and a 32-bit, 100 MHz real-time counter. The control software and a versatile user interface, developed with the aid of the Delphi tools, are also described. At an ambient temperature of we achieved a random error of 129 ps or 0.65 LSB. This is equivalent to a random error in the distance measurement equal to about 2.1 cm. The power consumption of the integrated counter is 5.2 mW when the clock is disconnected, which rises to about 390 mW in the active mode. Un nouveau design d'un compteur d'intervalles de temps entierement integre est presente pour des applications dans les systemes laser de mesure de distance avec une resolution de 3 cm. Le compteur est implante dans un circuit FPGA a structures amorphes `antifuse'. Le compteur contient deux convertisseurs temps-chiffre possedant chacun la resolution de 100 ps du bit le moins significatif (LSB) dans l'intervalle de 10 ns et un compteur temps-reel de 32 bits, 100 MHz. Sont egalement decrits: le logiciel de controle et l'interface flexible utilisateur developpes avec DELPHI. A temperature ambiante de nous avons obtenu l'erreur aleatoire de 129 ps soit 0,65 LSB, ce qui correspond a une erreur de distance d'environ 21 mm. La consommation d'energie du circuit integre est de 5,2 mW avec l'horloge 100 MHz deconnectee augmentant jusqu'a 390 mW en mode actif.

A new design of a time-to-digital converter (TDC) implemented on an FPGA chip with amorphous antifuse structures is presented. Time coding with 200-ps resolution (LSB), 10-ns range, and very short conversion time is realized by two tapped delay lines working in-a differential mode. Thanks to the local feedback loops, the output from the delay line is obtained directly in "1-out-of-N" code and then converted to 6-bit natural binary. Within the temperature range from 0/spl deg/C to 45/spl deg/C, the time offset at the output is constant, the resolution changes by /spl plusmn/0.02 LSB, and the offset-corrected integral linearity error is less than 1 LSB.

Dynamic development in science and technology in the second half of the twentieth century caused, among others, an increase in the interest in methods and techniques for precise measurement of time interval that elapses between two physical events. The main objective of the meters which are used for such purposes is the creation of a numerical representation of the measured time interval with as high accuracy and precision as possible. Since the result of measurement is usually presented in digital form, this operation is called a time-to-digital (T/D) conversion, while measuring devices are universally called time-to-digital converters (TDCs). In this chapter, the most representative methods and techniques used for the measurement of time interval with high resolution and precision are described. This includes time stretching, time-to-amplitude followed by amplitude-to-digital conversion, the counting method, direct time-to-digital conversions with a digital delay line in the single and Vernier versions, as well as single- and two-stage interpolation methods.

One of the recent methods to increase the precision of time-to-digital (T/D) conversion is based on the use of multiple independent time coding lines (TCLs). The number and configuration of TCLs influence the resolution and precision of conversion. We considered and tested 14 different variants of such lines involving up to 16 TCLs. Obtained results indicate the optimal way of using independent coding lines, which leads to significant improvement in equivalent resolution (up to 11 times) and precision (above 2 times) of T/D conversion in comparison with traditional technique based on a single TCL.

This paper presents the design, operation and test results of an interpolating time counter with a multi-edge coding principle implemented in the second stage of interpolation. The counter is implemented in an FPGA device (Spartan-6, Xilinx) and provides a 2.7 ps resolution, 8 ps precision and 1 s measurement range. The development of such a high performance instrument needs to solve several design problems. The main of them are an implementation of a pattern generator and elimination of bubble errors. We designed and tested two pattern generators based respectively on look-up tables and fast carry chains. The former one is simpler for implementation while the latter allows to control parameters of the pattern signal. This control feature is especially important for the quality of T/D conversion that depends, among others, on the complexity of the pattern signal. We tested three variants of TDC based in turn on coding of three rising, three falling or six alternated edges.

The design of a novel time-to-digital converter based on the cyclic pulse shrinking method and implemented in an FPGA (Field Programmable Gate Array) device is proposed. The pulse shrinking is realized by two complementary delay lines made as built-in carry chains. In the first line the noninverted pulse is being shrunk while in the second one the inverted pulse is being stretched. The converter resolution depends on the length ratio of the lines. To avoid the influence of any circuit element apart from the lines on the resolution, the information about a measured time interval is transmitted between the lines as a time interval between two pulses representing the leading and trailing edges of the original pulse. To increase the precision of converter a two-stage conversion is introduced. The low-resolution first stage shortens substantially the conversion time and provides a wide measurement range whereas the second stage provides a high resolution. The designed two-stage converter has a resolution of 42 ps and the measurement uncertainty below 56 ps within the whole measurement range. The two-stage structure is obtained as modification of a single-stage converter featuring the resolution of 75 ps and the maximum measurement uncertainty of 150 ps, which is also described in this paper.

The quantization error in interpolating time counters is analyzed for three models of interpolator and for correlated and uncorrelated input events representing the start and end of the measured time interval. The analysis is related to the currently most common two-stage time interpolation method and based on data from several up-to-date integrated time counters. The main aim of this discussion is to find a general and accurate method for presentation and calculation of the quantization error in real, non-ideal time counters. We propose a novel graphical representation of the error, which may be useful for analysis of time counters with any interpolation method used.