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Liposomes composed of egg phosphatidylcholine and cholesterol were modified with the temperature-responsive polymer poly(N-isopropylacrylamide-co-N, N-dimethylacrylamide) (P(NIPAAm-co-DMAAm)), and exhibited reversible surface properties with temperature. Completely reversible liposome aggregation due to P(NIPAAm-co-DMAAm) hydration/dehydration was demonstrated over four successive cycles of heating and cooling. The P(NIPAAm-co-DMAAm) polymer was hydrated during cooling, which dispersed the liposomes. The rigidity of the liposomal membrane was one of the factors in the reversible aggregation, as was the modification density of the polymer on the liposomes. A low density on relatively rigid liposomes could maintain the polymer property of reversible hydrated layers below critical solution temperature (LCST) boundary. Above the LCST, temperature-responsive polymers could also transport negatively charged liposomes into cells. The reversible behavior of the temperature-responsive polymer-modified liposomes has not been reported previously and could enable new applications for switching deposit forms as alternative drug carriers.

We consider the initial value problem to the Isobe-Kakinuma model for water waves and the structure of the model. The Isobe-Kakinuma model is the Euler-Lagrange equations for an approximate Lagrangian which is derived from Luke's Lagrangian for water waves by approximating the velocity potential in the Lagrangian. The Isobe-Kakinuma model is a system of second order partial differential equations and is classified into a system of nonlinear dispersive equations. Since the hypersurface $t=0$ is characteristic for the Isobe-Kakinuma model, the initial data have to be restricted in an infinite dimensional manifold for the existence of the solution. Under this necessary condition and a sign condition, which corresponds to a generalized Rayleigh-Taylor sign condition for water waves, on the initial data, we show that the initial value problem is solvable locally in time in Sobolev spaces. We also discuss the linear dispersion relation to the model.

This study reports the development of temperature-responsive polymer/silica hybrid nanoparticles and their application to temperature-dependent intracellular uptake of hydrophobic encapsulated fluorescence molecules. Amphiphilic diblock copolymer comprising a temperature-responsive segment, poly( N -isopropylacrylamide- co - N , N -dimethylacrylamide) [P(NIPAAm- co -DMAAm)] and a trimethyoxysilyl-containing hydrophobic segment was synthesized ( PBM- b -ND ); this amphiphilic diblock copolymer self-assembled in an aqueous solution, and temperature-responsive polymer/silica hybrid fluorescence nanoparticles were fabricated via a base-catalyzed sol–gel process. The fluorescence probe rhodamine DHPE or boron dipyrromethene derivative was encapsulated into the polymer core with a silica network in a stable manner. Other types of polymer/silica hybrid fluorescence nanoparticles were also developed using either homo-PNIPAAm ( PBM- b -N ) or homo-PDMAAm ( PBM- b -D ) segments, instead of P(NIPAAm- co -DMAAm). While PBM- b -D did not exhibit a temperature-dependent phase transition (hydrophilic characteristic), PBM- b -N and PBM- b -ND exhibited temperature-dependent phase transition (hydrophilic/hydrophobic) at 32 °C and 38 °C, respectively. The cellular uptake of PBM- b -N was clearly observed at both 37 °C and 42 °C, while the cellular uptake of PBM- b -D was minimal at these temperatures. On the other hand, significant enhancement in the intracellular uptake of PBM- b -ND was observed at 42 °C, compared to its uptake at a lower temperature of 37 °C. These results indicated that temperature-responsive polymer/silica hybrid nanoparticle, PBM- b -ND demonstrate potential for applications in theranostics with cancer therapy via the combination of local drug delivery and local hyperthermia, as well as for monitoring treatment effectiveness with fluorescence imaging.

The 100-gigabit Ethernet (100GbE) was standardized as IEEE 802.3ba in 2010 [1]. The optics module must be equipped with a “gearbox” LSI-which switches between 10×10Gb/s data signals on the physical-coding-sublayer side and 4×25Gb/s data signals on the physical-media-dependent side. A gearbox LSI based on 0.13 μm SiGe BiCMOS consumes 8W of power [2], which is about half of the total power consumption of the optics module. Aiming to reduce the power consumption, a 50Gb/s 2:5 DEMUX based on CMOS technology is developed [3]. In addition, since the architecture in reference [2] consists of two LSIs (MUX and DEMUX), loop-back operation, which is required in the IEEE standard, is impossible. In response to these circumstances, we have developed a 100GbE gearbox LSI combining a 10:4 MUX and a 4:10 DEMUX. This gearbox LSI — implemented in 65nm CMOS — decreases power dissipation by 75% compared to that of a conventional LSI.

A 12.3-mW 12.5-Gb/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer/demultiplexer (MUX/DEMUX), and a global clock-distribution network. To reduce power consumption, a low-swing voltage-mode driver with pulse-current boosting and an LC resonant-clock distribution with distributed on-chip inductors are used in the transmitter, while a symbol-rate phase detector (SPD) using a three-stage sense amplifier and phase-rotating phase-locked loop (PLL) with variable delay are used in the receiver. The transceiver operates at a bit error rate (BER) of 10-12 or less through a 20-cm test board with total attenuation of -12.1 dB while consuming power of 0.98 mW/(Gb/s) per transceiver.

A 10 Gb/s receiver with a digital CDR uses a track-and-hold-type linear phase detector (LPD) and charge-redistribution first-order ΔΣ modulator. It has low quantization error and high loop bandwidth due to the use of the LPD and maintains the advantages of a digital CDR such as low power consumption, small area, fast locking time, and low-jitter recovery clock because no internal VCO is needed. The CDR tracking bandwidth is 20 MHz and high-frequency jitter tolerance is 0.42 UIpp at 10-12 BER. Power consumption of LPD is 2.6 mW while the entire receiver consumes 65 mW.

The effects of 16 lectins isolated from foodstuff on the transport system across human intestinal Caco-2 cell monolayers were investigated by using four fluorescent markers: lucifer yellow (LY) for the paracellular pathway, fluorescein (FL) for the monocarboxylic acid transporter-mediated pathway, rhodamine 123 for the P-glycoprotein-mediated efflux pathway, and calcein for the multidrug resistance associated protein-related efflux pathway. The transepithelial electrical resistance (TER) values for the monolayers were also measured. WGA from wheat germ, ABA from white mushroom, AOL from Aspergillus oryzae, and CSL3 from chum salmon eggs (each at 100 µg/mL) decreased the TER value by 20-40% which resulted in increased LY transport. These lectins, as well as such other lectins as SBA from soybean, RBA from rice bran, and Con A from jack bean, affected other transport pathways too. These results indicate that the lectins modulated the transepithelial transport system in different ways, probably because of their specific binding characteristics toward Caco-2 cell monolayers.

The world's first CMOS "gearbox LSI" based on 65-nm CMOS technology-namely, a 2-W 100-gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer-was developed. Its power consumption is 75% lower than that of a conventional SiGe-based gearbox LSI. The power consumption of its 12.5-Gb/s interface is 0.98 mW/(Gb/s), while that of its 25- Gb/s interface is 14 mW/(Gb/s).

For the people involved with multi-Gb/s chip-to-chip serial links, reducing power dissipation per Gb/s to less than 1mW/(Gb/s) (i.e., 1pJ/b) has been a long-held goal. Several years ago, the power dissipation of these links was in the range of about 10 to 20mW/(Gb/s). In 2007, Poulton et al. developed a 14mW 6.25Gb/s transceiver with power efficiency of 2.2mW/(Gb/s) [1]. Thereafter, there were some efforts aiming to reduce power of each building block in a transceiver [2, 3]. This paper presents a 12.3mW 12.5Gb/s complete transceiver (including CDR, MUX/DEMUX, and global clock distribution)in 65nm CMOS with power efficiency of 0.98mW/(Gb/s). To achieve low power, a resonant-clock distribution with distributed on-chip inductors and a low-swing voltage-mode driver with pulse-current boosting are used in the transmitter, while a symbol-rate comparator/phase detector using 4-stage sense amplifier and phase-rotating PLL with variable delay are used in the receiver.

A CDR circuit and a phase detector are the key building blocks of high-speed interconnect systems. Today, most CDR circuits use bang-bang phase detectors. These phse detectors have several advantages, including low power consumption, a simple circuit structure, and compatibility with digital circuits [1,2]. However, bang-bang phase detectors have the intrinsic drawback of large quantization noise. Therefore, the CDR loop bandwidth must be relatively low to mitigate the effect of the quantization noise by time averaging. In particular, digital CDRs operated in a Δ-modulation loop are susceptible to quantization noise. On the other hand, linear phase detectors (LPDs) do not exhibit quantization noise and therefore by using them one can potentially increase the CDR bandwidth to achieve improved jitter tolerance. However, conventional LPDs, such as the Hogge phase detector, which detect the phase difference as a pulse width, cannot be easily incorporated in a digital CDR [3]. In this paper, a 10Gb/s receiver is described that is equipped with a track-and-hold-type LPD as well as a charge-redistribution ΔΣ modulator for incorporation in a digital CDR. The 10Gb/s receiver exhibited low quantization errors and high loop bandwidth that are due to the use of a linear phase detector while it maintains the advantages of a digital CDR circuit, such as low power consumption, small area occupation, fast locking time, and a low-jitter recovered clock because an internal VCO is not needed. The tracking bandwidth of the CDR circuit is about 20MHz, and the power consumption of the receiver is 65mW

IT systems such as servers and routers need high-speed lower- power area-efficient chip-to-chip interconnections through backplane boards. These interconnections must overcome signal degradation due to the large insertion loss of low-cost boards. In this work, a 90nm CMOS 8Gb/s transceiver is developed. A TX 5- tap FFE, an RX analog equalizer, and a 2-tap DFE combined with a 2-threshold eye-tracking CDR achieve a BER of less than 10-12 through a 160cm backplane board with -36.8dB loss at 4GHz and a transceiver power consumption of 232mW (transmission efficiency of 1.2Gb/sxdB/mW).

A wireless sensing chip for biological assay is fully operational in a sample solution. The IC monolithically integrates a biological sensor, an RF communication circuit, and a coupling coil on a 2.5/spl times/2.5 mm/sup 2/ chip in 0.35 /spl mu/m CMOS technology. Detection of single nucleotide polymorphism (SNP) in DNA is successfully carried out by the chip.

A newly developed DNA measurement method for multiple single nucleotide polymorphism (SNP) typing using a radio-frequency identification (RFID) sensor chip was demonstrated. The RFID sensor chip monolithically integrates a sensor, amplifier, analog-to-digital converter (ADC), and a passive wireless communication interface for receiving commands and transmitting data on a 2.5×2.5 mm2 silicon chip. For the simultaneous multitarget measurement, anticollision control and peak-power suppression are essential. To assign a unique identification number (UID) for the identification of multiple sensor chips, a reproducible random number generator circuit (RRG) was designed and installed on the chip. Peak-power consumption was reduced to 1018 µW by a clock gating of functional circuit blocks. Multiple SNP typing was carried out by simultaneously operating five RFID sensor chips (four with photosensors and one with a temperature sensor). The target DNA was captured on the sensor chips, and SNPs were detected by observing bioluminescence. Finally, the observed data were wirelessly transmitted to the reader.