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Time dependent dielectric breakdown (TDDB) reliability is studied on interfacial layer (IL)/high-K gate stack of Gate-All-Around Nanosheet (GAA-NS) N- and P-type Field Effect Transistors (FETs) with volume-less multiple threshold voltage (multi-Vt) integration scheme enabled by the dual dipoles (n-dipole and p-dipole). We report for the first time Key TDDB Modeling parameters: voltage acceleration exponent (VAE), Weibull slope ( $\beta$ ), and activation energy (E a ) and show robust TDDB reliability in multi-Vt NS transistors enabled by different dipoles.

We report that n-dipole and p-dipole (dual dipoles) can be co-integrated to provide a more flexible volumeless multiple threshold voltage(multi-Vt) solution in FinFET and Nanosheet (NS) technologies. The p-dipole process for dual dipoles co-integration is identified. When the Vt shift is less than 100m V, the mobility is slightly degraded, but other properties are not clearly affected. The improved pFET performance is from the Vt reduction. The dipole co-integration also provides a novel method for Vt definition via dipole Vt compensation. Our selective dipole enablement can implement near bandedge (BE) multi- Vt for high performance application.

In this paper, full bottom dielectric isolation (BDI) is first demonstrated on horizontally stacked Nanosheet device structures with Lmetal 12 nm. The comparison of full BDI scheme vs punch through stopper (PTS) scheme has been systematically studied. By comparing off-state leakage current, short channel behavior and effective capacitance (Ceff) for both schemes, we show that BDI could potentially provide: 1) good immunity of sub-channel leakage due to process variation (from parasitic "fat-Fin" which is unique in Nanosheet structure); 2) power-performance co-optimization.

In Nanosheet (NS) device architecture, it is much more challenging than FinFET to develop a suitable multiple threshold voltage (multi-Vt) integration with more restrictive requirement on the dimensions due to the critical dimension scaling and complex structure. In this abstract, we reported an innovative integration scheme to enable volumeless multi-Vt and metal multi-Vt to provide the multi-Vt solutions in NS technology for high performance computing (HPC) and low-power applications. We developed a new volumeless multi-Vt for NS to solve the device geometry constraint and offer more margin and the opportunity for further sheet-to-sheet spacing (Tsus) reduction. Furthermore, metal gate boundary control (MGBC) was developed to enable variable NS widths on the same wafer to satisfy both HPC and low-power applications.

A baseline TiAl-containing ALD electrode is established, with properties in line with reported workfunction (WF) materials for scaled RMG nFETs, values below 4.6eV requiring a 25A layer. Furthermore, a novel ALD metal-compound material, MX, is shown to enable at least 10A further scaling of the electrode stack due to its superior scavenging power. It can be finely tuned by the film thickness, allowing for a remarkable 20-30meV WF delta per ALD cycle over a minimum 600meV range. The wet etchability of the electrodes makes multi-Vt and dual-WF integration possible. MX does not degrade transfer characteristics and reliability of RMG FinFETs, while the thinner nWF electrode enables reduced gate resistance, as verified down to 20nm metal gate lengths. For the first time, taking advantage of the MX compound scavenging power to control oxygen filaments, we demonstrate an all-ALD HfO 2 -based ReRAM. Forming voltages match those achieved by optimized PVD contacts, while scaling the active electrode thickness by a factor of 4x, down to 5nm. Conformality of the layers enables vertical-ReRAM architectures with reduced line resistance. We conclude the developed electrode can facilitate both logic scaling beyond the 10nm node, and 3D memory technology.

In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.

For the first time, high electron mobility in tensile-strained SiGe channel nFinFETs outperforming Si is reported to explore the feasibility of high performance SiGe CMOS. To examine the electron mobility behaviors in SiGe channel, a series of tensile-strained SiGe nFinFETs are fabricated on various strain relaxed buffer layers by taking into account the minimum threading dislocation density and strain engineering. For SiGe $(\text{Ge} > 20\%)$ nFinFETs, we identify the existence of additional electron trapping site close to the conduction band edge in IL/HK, leading to the abnormal Vt shift, PBTI degradation, and low electron mobility. We also fabricated short-channel SiGe nFinFETs, which exhibit excellent cut-off behavior and electrostatics (SS ∼65mV/dec and DIBL ∼18mV at $\mathrm{V}_{\text{DD}}=0.7\mathrm{V}$ ). In addition, the dynamic performance of tensile-strained SiGe CMOS against Si CMOS is evaluated by TCAD simulation based on experimental data.

We demonstrated more than 3 pairs of threshold voltage (Vt) devices by volume-less multiple Vt (multi-Vt) scheme plus dual work function metals (WFM) without performance and reliability degradation on 20nm gate length FinFET CMOS devices. Vt shifts over 200 mV were achieved for both nFET and pFET. The volume-less nature of this multi-Vt scheme relieves replacement metal gate (RMG) challenges and opens the path to offer multi-Vt solution for future highly scaled technologies.

This paper addresses novel approaches at material and integration fronts for gate applications. Material wise, new n work function metal (WFM) material is explored to address the need for reducing gate resistance and maintaining proper Vt at 20A or less WFM thickness. Integration wise, next generation dipole is tested with various process sequences to address the need in lowering overall thermal budget at the gate level for advanced architectures, such as scaled FinFET and Nanosheets.

The impact of oxygen containing plasma treatment on the electrical properties of gate stack is evaluated by measuring the interfacial layer thickness as a function of plasma treatment condition and by characterizing electrical parameters, such as threshold voltage (V t ), mobility, and interfacial trap density. X-ray photoelectron spectroscopy (XPS) measurements show that exposure to an oxygen containing plasma can result in interfacial layer growth when not protected by work function metal. This direct exposure may also result in the incorporation of positive charges into the dielectric layer. Incorporating positive charges into the dielectric layer results in a positive shift of V t. This is further verified by the fact that the hole mobility is degraded after plasma processing. This impact to hole mobility is negated when the work function metal is in place to act as a diffusion barrier between the oxygen containing plasma and the dielectric layers.

Leakage in Si/SiGe CMOS FinFET is examined. Si cap passivation effectively improves SiGe pFET Dit, subthreshold slope, and mobility, which improves pFET DC performance by 20%. SiGe GIDL is higher than Si by a factor of 9, though GIDL is limited to 50pA/um. SiGe GIDL reduction knobs to meet Si counterpart are demonstrated. The results open the door to the next stage of Si/SiGe CMOS FinFET such as low power and low leakage applications.

We report for the first time that replacement metal gate (RMG) work function metal (WFM) modulates the interface defects in Silicon and SiGe MOSFETs. Changing the effective work function (eWF) towards nFET band edge provides lower interface defects and higher mobility than eWF near the pFET band edge for both Si and SiGe substrates. Reducing the electric field across the dielectric (via eWF) improves bias temperature instability (BTI) for both n & pMOSFETs beyond expectation. Breakdown voltage increases and gate leakage decreases with increasing eWF for both n & pMOSFETs. Therefore, multi-Vt MOSFETs by RMG metal gate exhibit differentiated reliability as well as differentiated performance for both Si and SiGe channel materials.

In this paper, we report multi-threshold-voltage (multi-Vt) options for stacked Nanosheet gate-all-around (GAA) transistors. V t can be modulated through workfunction metal (WFM) thickness as well as the inter-nanosheet spacing (T sus ), the combination of which may be leveraged to increase the number of undoped V t offerings within a CMOS device menu relative to a FinFET CMOS device menu, which fundamentally does not have T sus as a V t tuning option. Hence we propose our multi-V t scheme by taking advantage of the unique structure of stacked GAA transistor.

Strained Si 1−x Ge x channel pFinFETs and planar pFETs are fabricated on a strain relaxed buffer virtual substrate to comparatively study the electrical impact of strain and Ge content in the Si 1−x Ge x channel. By comparing the transistor electrical properties of Si 1−x Ge x pFETs on SRB with Si 1−x Ge x pFETs on Si substrate, we successfully decouple the influence of strain and Ge content in the Si 1−x Ge x channel on device performance such as gate stack quality, reliability, and carrier transport. Based on these understandings, dual channel Si/Si 1−x Ge x FinFETs on the SRB with the optimized surface orientation is proposed to further improve the device performance.

In this paper, we discuss a technique for selective GeO x -scavenging which creates a GeO x -free interfacial layer (IL) on Si 1−x Ge x substrates. This process reduces interface trap density (N it ) and increases high-field hole mobility in Si 1−x Ge x pFETs. In addition, we identify the existence of electronic defect levels close to the Si 1−x Ge x band edges associated with the Ge surface concentration at the Si 1−x Ge x /IL interface. These electronic defects act as carrier scattering centers severely degrading the channel mobility and modulate the device threshold voltage. By successfully eliminating the GeO x component in the IL and electronic defects states at the Si 1−x Ge x /IL interface, high channel carrier mobility over a wide range of inversion carrier density in compressively-strained Si 1−x Ge x channel pFETs is demonstrated.

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

We investigate the mechanism of interfacial layer formation on Si 1−x Ge x (0 1−x Ge x (x 1−x Ge x channel is presented to understand the surface atomic configuration of Si 1−x Ge x channel as well as mobility enhancement mechanism.

With the increasing prevalence of complex device integration schemes, tri layer patterning with a solvent strippable hardmask can have a variety of applications. Spin-on metal hardmasks have been the key enabler for selective removal through wet strip when active areas need to be protected from dry etch damage. As spin-on metal hardmasks require a dedicated track to prevent metal contamination, and are limited in their ability to scale down thickness without comprising on defectivity, there has been a need for a deposited hardmask solution. Modulation of film composition through deposition conditions enables a method to create TiO2 films with wet etch tunability. This paper presents a systematic study on development and characterization of PEALD deposited TiO2-based hardmasks for patterning applications. We demonstrate lithographic process window, pattern profile, and defectivity evaluation for a tri layer scheme patterned with PEALD based TiO2 hardmask and its performance under dry and wet strip conditions. Comparable structural and electrical performance is shown for a deposited vs a spin-on metal hardmask.

Hot carrier reliability is studied in replacement metal gate (RMG) Si1-xGex (x = 20%) channel p-FinFETs with high-k gate dielectrics. In this study, we show that: (1) interface state generation and hole-trapping contribute to the HC damage under high-Vg (∼Vd) stress conditions; (2) hot electron injection is the dominant degradation mechanism for low- and mid-Vg biases, which are more representative stress conditions during typical CMOS logic circuit operation. We also found that excessive electron trapping in ultra-scaled SiGe pFinFETs can reduce the effective channel length and significantly increase the off-state leakage current (Ioff).

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

Gate resistance, middle of line resistance, and back end of line resistance in modern metal-gate CMOS increase drastically as the dimensions of the gates, interconnects and vias scale down close to or below the bulk electron mean free paths (MFPs) of the metal materials. These resistances, especially the gate resistance, impose more and more significant RC delay to CMOS circuits and become significant concerns in sub-22-nm CMOS. In order to optimize the metal-gate materials and structures for low resistance, accurate metal resistance model is needed. In this letter, we propose an analytical metal resistance model applicable for metal wires and films even with sub-MFP sizes. Our model includes scattering effects from surfaces, interfaces, and grain boundaries, and has been successfully verified on $W$ metal gates with the feature sizes ranging from 20 to 70 nm.

With the motivation to employ BaO–B2O3–ZnO for high performance capacitors by using viscous flow/liquid phase sintering, the microstructures, phases, and dielectric properties of BaO–B2O3–ZnO films prepared by pulsed laser deposition were examined as a function of heat-treatment. The glass transition temperature (Tg) and crystallization temperature of the films are ~ 536 °C and 640 °C, respectively. The phases in the films are quite complicated after heat-treated above 700 °C until 900 °C where the film is dominated by a single phase. Zn concentration is reduced after heat-treatment at high temperature due to segregation and evaporation. The dielectric constant of the film decreases with the increasing heat-treatment temperature, probably due to Zn reduction, Si diffusion, and crystallization of the film. Experimental data shows that ~ 700 °C is the optimal temperature to use the low melting glass BaO–B2O3–ZnO to make high performance capacitors by viscous flow/liquid phase sintering.

SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1–4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1–4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.

We demonstrate a technique for selective GeO x -scavenging which creates a GeO x -free IL on Si 1−x Ge x substrates. This process reduces N it by >60% to 2e11 and increases high-field mobility at N inv =1e13 cm−2 by ∼1.3× in Si 0.6 Ge 0.4 pFETs with sub-nm EOT.

Long-lived and high-energy-density betavoltaics have a great potential as power supplies for remote and hostile environmental conditions, where volume power density and/or power lifetime are very important considerations. In this paper, we provide new results to aid in the design and optimization of betavoltaics made with Si space solar cells and beta sources. The new results were obtained by using a customized low-energy electron accelerator to characterize the radiation-hardened high-efficiency Si space solar cells while varying the electron beam energy and electron beam current density, i.e., electron beam flux. The betavoltaic conversion efficiency of Si space solar cells increases until 60 keV and then decreases with the increasing electron beam energy. The maximum efficiency (6%) obtained at the electron beam energy of 60 keV suggests that Pm-147 would be a good beta source to make high-efficiency nuclear batteries. The radiation ionization energy is ~ 3.90 eV per electron-hole pair for Si space solar cells. Some radiation damage-induced performance degradation was also observed when the Si space solar cells were exposed to the bombardment of 62-keV electrons with fluence up to 4.92 × 1018betas/cm2, which is equivalent to the radiation from a semi-infinite Pm-147 layer for ~ 2.26 years. The results in this paper suggest that beta-particle entrance window, betavoltaic cells' configuration structure, and device properties such as charge carriers' diffusion length are very important factors to be engineered to improve the conversion efficiency for practical betavoltaics.

In this paper, we develop a multiplicative model to simulate the tungsten (W) film resistivity and gate resistance for replacement metal gate (RMG) with W electrode. Our multiplicative model predicts that TiN fill offers the lower gate resistance than TiN/W fill for highly scaled gate lengths. By absorbing the results from our model into the real RMG FinFET devices, we observe that TiN fill provides ∼6.4 % performance improvement compared to TiN/W fill. Meanwhile, the employment of gate conductance for gate stack film thickness monitoring is also described in our work.

The kinetics of hydrogen in preparing amorphous boron carbide (a-B5C:H) thin films was studied. The hydrogen concentration of a-B5C:H thin films formed by plasma-enhanced chemical vapor deposition (PECVD) from a single-source precursor (o-B10C2H12) is ∼35–50 at.% as determined by nuclear reaction analysis. The hydrogen concentration of the a-B5C:H thin films is an exponential function of the precursor flux during the deposition. After annealing, the hydrogen concentration in the a-B5C:H thin films decreases with the increasing annealing temperature. The kinetics of hydrogen removal during annealing is controlled predominantly by its dissociation from PECVD radicals in the a-B5C:H thin films. The activation energy of about 0.14 eV is related to hydrogen dissociation from B–H bonds, but higher activation energy (∼0.44 eV) is required to strip the hydrogen atoms from C–H bonds in the thin films.

B4C boron carbide thin films deposited by radio frequency magnetron sputtering in the temperature ranging from room temperature to 650 °C are amorphous. In this article, pair distribution function (PDF) and Fourier transform infrared (FTIR) spectroscopy were used to characterize the short range order (SRO) structure of amorphous B4C thin films. FTIR spectra indicated that icosahedrons exist in the amorphous B4C thin films. The existence of icosahedrons was further verified by the PDFs of amorphous B4C thin films, which were derived from digital selected area electron diffraction patterns. Furthermore, by comparing the PDFs of amorphous B4C thin films with those of three crystalline boron modifications and three structural models of boron carbides (B4C or B10C2), the SRO structure of amorphous B4C thin film was revealed to be similar to that of β-rhombohedral boron, but with the peak shifted to shorter distance.

A new route to synthesis of Ag(2)O micro-/nanostructures, including a mixture of cubes, pyramids, triangular plates, pentagonal rods, and bars, has been developed by pulsed excimer laser ablation of bulk silver in water using polysorbate 80 as surfactant. The polysorbate 80 played an important role in the formation of the Ag(2)O structures, and similar structures could be obtained in polysorbates 20 and 40 aqueous solutions. We have proposed a mechanism to explain the formation of Ag(2)O structures. This laser ablation method provides a unique approach to discover and fabricate new Ag(2)O morphologies.

Boron carbide thin films were deposited by radio frequency (RF) magnetron sputtering and characterized by X-ray photoelectron spectroscopy (XPS), Raman spectroscopy, and high resolution transmission electron microscopy. The results reveal that the structure of thin films deposited at substrate temperatures lower than 350 °C is amorphous. We found that there are four chemical states for carbon in amorphous boron carbide thin films deposited by RF magnetron sputtering. One is the segregated carbon in form of the graphitic inclusions in the thin film identified by Raman spectroscopy and Raman mapping using two strong peaks at ~ 1360 cm − 1 and ~ 1590 cm − 1 , but the XPS results show that the graphitic inclusions do not connect to the substrate directly. On the surface the carbon forms C=O bonds characterized by the peak of C1s core level at 285.0 eV besides B–C bonds in the boron carbide with the peak of C1s being at 282.8 eV. The detailed analysis of B–C bonds in the boron carbide shows that there are two states for carbon atoms in B–C bonds: in the C–B–C models with C1s peak at 282.3 eV and in the icosahedra with C1s peak at 283.3 eV.

Herein we show how the unique temporal and thermal events occurring during the pulsed excimer laser ablation of an Al target in water result in hollow Al2O3 micro/nanoparticles with smooth surfaces and an amorphous structure. We demonstrate that the hollow particles are formed on laser-induced bubbles from laser ionized/evaporated liquid during the ablation. The fabrication of hollow particles can be improved by the addition of ethanol to the water, and the particles contain crystalline Al. Our work and the associated mechanism represent a new paradigm to fabricate hollow particles directly from bulk material; that is, the excimer laser ablation produces nanoclusters from the target and bubbles from the liquid, and the bubble interfaces trap the nanoclusters, resulting in the formation of hollow particles.

We report the fabrication of permalloy nanoparticles by pulsed excimer laser ablation of a permalloy (Fe19Ni81) target in sodium dodecyl sulfate aqueous solution and the subsequent laser-induced assembly, sintering, and fragmentation of the nanoparticles. Specifically, permalloy nanoparticles with diameters of 400−600 nm were observed to assemble into fullerene-like hollow microparticles. Laser irradiation caused sintering of the assembled particles, which showed Wulff construction and ledge growth behavior and finally resulted in smooth shells. Laser−particle interactions also caused fragmentation of the micro/nanoparticles. When the particle concentration is high, laser fragmentation rather than laser ablation dominates due to enhanced light absorption and scattering. The experiments reveal the dynamic process of the nano- and microparticle formation, demonstrating the rich processing environment of laser ablation in liquid.

The deformation behavior and mechanisms of Ti-1023 alloy were studied in the temperature range of 650–900 °C and strain rate range of 0.001–10 s −1 by compression and tensile tests. The results show that in a limited strain rate range of 0.001–0.1 s −1 , the kinetic rate equation is obeyed and a linear fit is obtained at all the temperatures. The apparent activation energy is 322 kJ/mol in the α-β region and 160 kJ/mol in the β region, respectively. Power dissipation maps of this alloy developed by using Gleeble test data show three domains in the tested range. Superplasticity, marked by abnormal elongation at 700 °C, occurs in the temperature range of 650–750 °C and at strain rates below about 0.03 s −1 . Large grain superplasticity takes place in the temperature range of 750–850 °C and strain rates range of 0.001–0.03 s −1 . Dynamic recrystallization occurs in the temperature range of 850–900 °C and at strain rates below about 1 s −1 . The instability maps of this alloy were also developed.

We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generation deep trench embedded DRAM to provide an ultra-dense (0.0174um2) memory solution for industry leading ‘scale-out’ processor design. A broad range of Vts is enabled on chip through a unique dual workfunction process applied to both NFETs and PFETs. This enables simultaneous optimization of both lowVt (HP) and HiVt (LP) devices without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The SOI finFET's excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ∼0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for ‘scale-up’ enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm2 SoCs.

In order to optimise the hot die processes of Ti–10V–2Fe–3Al alloy, the effects of forging processes on the microstructures and mechanical properties were studied and processing maps were used to try to aid the process design. The results show that processing maps for Ti–10V–2Fe–3Al alloy exhibit three process ranges, but only the range near β transus is suitable for hot die forging of this alloy. The alloy forged at T β −30°C has a higher strength and ductility while the alloy forged at T β +30°C offers higher fracture resistance than the former. Process C, where the alloy was forged at T β +30°C to form the acicular α p and then at T β −30°C to get globular α p, was designed and the total amount of deformation equal to 50% was chosen. Through process C the alloy has a better combination of tensile properties and fracture resistance than any other processes because a proper mixture between globular α p and acicular α p is obtained.

With the increasing prevalence of complex device integration schemes, trilayer patterning with a solvent strippable hardmask can have a variety of applications. Spin-on metal hardmasks have been the key enabler for selective removal through wet strip when active areas need to be protected from dry etch damage. As spin-on metal hardmasks require a dedicated track to prevent metal contamination and are limited in their ability to scale down thickness without compromising on defectivity, there has been a need for a deposited hardmask solution. Modulation of film composition through deposition conditions enables a method to create TiO2 films with wet etch tunability. This paper presents a systematic study on development and characterization of plasma-enhanced atomic layer deposited (PEALD) TiO2-based hardmasks for patterning applications. We demonstrate lithographic process window, pattern profile, and defectivity evaluation for a trilayer scheme patterned with PEALD-based TiO2 hardmask and its performance under dry and wet strip conditions. Comparable structural and electrical performance is shown for a deposited versus a spin-on metal hardmask.

Three-dimensional zinc hydroxide/dodecyl sulfate (Zn(OH)2/DS) nanostructures self-assembled by nanolayers have been fabricated by pulsed laser ablation of bulk Zn in ethanol–water solution of sodium DS. The presence of ethanol causes defects in the hydroxyl group sites of Zn(OH)2 that partially form ZnO structures, which facilitate heterogeneous nucleation of secondary nanolayers, resulting in three-dimensional nanostructures. These results demonstrate that laser ablation in liquid can be used to fabricate complex nanostructures by controlling the nucleation and growth behavior of laser-produced species.

The electronic properties of a-Si:H vary with hydrogen passivation of dangling bond defects. It appears this effect is also operative in semiconducting amorphous hydrogenated boron carbide (a-B5C:H). Therefore, the ability to quantify the amount of hydrogen will be key to development of the materials science of a-B 5 C:H. The results of an initial investigation probing the ability to quickly correlate hydrogen concentration in a-B 5 C:H films with infrared spectroscopy are reported. a-B 5 C:H thin films were growth on Si (111) substrates by plasma-enhanced chemical vapor deposition (PECVD) using sublimed orthocarborane and argon as the precursor gas. Nuclear reaction analysis (NRA) was performed to quantify the atomic concentration of H in the a-B 5 C:H films. While the observed vibronic structure does not show stretches due to terminal C-H or bridging B-H-B, analysis of the terminal B-H stretch at ∼2570 cm -1 gives a proportionality constant of A = 2 x 10 22 cm -2 . We conclude that the methods previously developed for correlating H concentration to infrared data in a-Si:H are similarly viable for a-B 5 C:H films.

Pulsed laser ablation in liquid (PLAL) has been well established as a facile method to produce nanoparticles from bulk materials, but it is still insufficient for fabricating anisotropic and complex nanostructures, especially without the use of surfactants. Here, we demonstrate that silver (Ag) nanosheets can be produced by pulsed excimer laser ablation of bulk Ag in water via laser re-processing of the laser-produced primary clusters. We also show that by combining PLAL and drop evaporation, rice-shaped Ag-Ag(2)O particles and their assemblies can be generated on Si substrates, because the interior flow of an evaporating colloidal drop could redistribute the laser-produced primary clusters, which results in the formation of complex nanostructures. These results show that PLAL is able to fabricate novel micro-/nanostructures while keeping its merit of "clean" fabrication.

Replacement metal gate (RMG) process requires gate fill with low resistance materials on top of work function tuning metals. Conventional titanium (Ti)-aluminum (Al) based RMG metal fill scheme for low resistance gate formation becomes challenging with further gate length scaling for 20nm node and beyond. In this work, we have demonstrated competitive low resistance gate formation at smaller than 25nm L gate using a novel cobalt (Co)-aluminum based metal fill scheme for extreme gate length scaling. Challenges in CMP for the implementation as well as assessment on resistance and device characteristics of this new low resistance fill scheme are also discussed.

Micro/nanoparticles were fabricated by pulsed-excimer-laser ablation of a Pt target in water. Three kinds of hollow Pt particles (coalesced by micrograins, assembled by nanocrystals or with smooth shells) were observed together with solid particles using different laser fluences (2.3-6.8 J cm(-2)) and after 6000 laser shots. We propose that the hollow particles were formed on laser-produced bubbles which provided thermodynamically preferred nucleation sites and diffusion sinks for the laser-fabricated Pt clusters or particles. Although the hollow particles are a small proportion, the results have extended the scope of particles that pulsed-laser ablation in liquid can fabricate, and have enriched the mechanistic scenario of laser ablation and nanostructure formation in liquid.

Boron carbon nitride (B-C-N) thin films are attractive due to their potential as hard coatings and as semiconductors with varying band gap. Both B-C-N (BC0.24N0.24) thin films and boron carbide (B4C) thin films were deposited by radio-frequency magnetron sputtering at room temperature. Also, the transition of boron carbide to B-C-N was studied by bombarding the boron carbide thin film by ∼1 uA/cm2 4 keV N+ ions. The results show that the UV-Vis transmittance of B-C-N thin films is better than that of amorphous boron carbide and both B-C and B-N bonds exist in our B-C-N thin films. The nitrogen in our B-C-N thin films bonded with boron causes the XPS B 1s core level to shift 2 eV from that in the B4C boron carbide thin film. Ion bombardment shows that the N+ ion primarily reacts with boron to form B-N and this reaction causes the environmental change of carbon in the thin film and then the XPS C 1s core level to shift to 283.5 eV from 282.8 eV.

Permalloy particles were fabricated by pulsed excimer laser ablation in distilled water and Tween 80 aqueous solution with the same laser parameters. Nearly spherical particles and irregular and porous fragments were obtained in water due to rapid condensation and growth of the laser ablated clusters. The products obtained in Tween 80 aqueous solution contained well-shaped spheres but some were laser sintered together via laser-particle interactions. Holes or pits were observed on the surface of some particles, which we consider were caused by laser induced bubbles in the liquid. Our results demonstrate the rich environment ablation in liquids can be for novel particle formation.

Permalloy (Ni81Fe19) nanoparticles with diameters of hundreds of nanometers have been successfully fabricated by pulsed laser ablation (PLA) in air, distilled water, pure ethanol and sodium dodecyl sulfate (SDS) aqueous solutions. The permalloy nanoparticles made in SDS solutions are typically spherical in shape. Lower laser energy with lower frequency leads to the formation of smaller permalloy nanoparticles. Higher concentration of SDS results in smaller nanoparticles. Lastly, we found some unusual permalloy nanoparticles with interesting morphologies made by PLA in air, distilled water and ethanol.

We report on the formation of hollow MgO particles by excimer laser ablation of bulk Mg in water and aqueous solutions of sodium dodecyl sulfate (SDS) and sodium citrate (SC). Lamellar nanostructures of Mg(OH)(2) also formed in water, but the formation could be avoided by the addition of SDS or SC. Laser ablation produced not only Mg species that were oxidized into MgO and Mg(OH)(2) in water, but also cavitation bubbles. The bubble interfaces trapped the MgO nanoparticles to decrease the surface free energy of the system, finally resulting in hollow particles.

Charge carrier lifetime is a critical parameter to improve the conversion efficiency of radioisotope power sources and the sensitivity of neutron detectors based on boron carbide thin films. The effective charge carrier lifetime in B4C boron carbide films has been investigated by using transient photoconductivity decay. The carrier lifetime depends on the characterization conditions as well as the structure of the films. The measured lifetime could be up to ∼1 ms in B4C film, which is much longer than that in conventional semiconductors. The photoresistance change in B4C films and the photovoltaic response of B4C/n-Si(100) heterojunctions have also been studied.