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Volatile Ovonic threshold switching (OTS) are promising not only as the selector in crossbar resistive switching memory arrays, but also as true random number generators (TRNG) by utilizing its probabilistic switching characteristics. However, investigation on the reliability of OTS-based TRNG is still lacking, which hinders its practical application. Previously, we found that switching probability is dependent on the pulse amplitude and width. In this work, we report that relaxation which happens during the time interval between pulses can cause switching probability drift. Optimizing the bit-generation waveform and modulating the pulse conditions could provide a practical solution, in addition to the impact of external bias and temperature. This work provides useful guidance for the\ud practical design and operation of OTS-based TRNGs.

Chalcogenides are attractive materials for microelectronics applications due to their ability to change physical, optical, and electrical properties under applied electric stimulus. One of the most recent interest in chalcogenides is their use to enable the development of a two-terminal selector device, which is a fast, volatile, resistance switching device. The electrical signature of Ovonic threshold switching (OTS) chalcogenide materials is well suited for such applications. While there are numerous known OTS materials, most of them contain toxic elements. There is hence a need to find environment-friendly OTS materials. For this to happen, we strive to predict electrical device parameters only from atomistic first-principles simulations of the chalcogenide materials, as this can be a faster and less expensive route to screen the performances of chalcogenide candidates. By mapping the experimentally measured set of electrical OTS materials into atomistic models and computing their electronic properties, we were able to identify correlations between computed properties such as the theoretical trap/mobility gaps, the local atomic coordination environments of the elements adopted in the material, and the experimentally measured first-fire/threshold/hold voltages, hold/leakage currents, or extracted trap density. These findings can guide in identifying OTS materials with predefined electronic properties, tailored to the requirements of specific microelectronics applications with only first-principles simulations.

With decreasing dimensions and increasing complexity, semiconductor devices are getting more difficult to fabricate. In particular the allowed deposition temperature becomes lower. Amorphous materials, which do not require annealing steps, are therefore becoming more interesting. First principles modelling of amorphous materials is, however, way more complex than modelling crystalline ones. Especially to screen for new materials, a fully ab initio approach is hence too expensive. We take on this challenge by employing a combination of high throughput first principles calculations and artificial intelligence (AI). We construct 4500 atomistic models, each containing 200-atoms, to capture the properties of amorphous phases of primary, X-O, and binary, X-Y-O, metal oxides. For these models, we calculate the relevant properties for a transistor channel. Expanding this exercise to more complex metal oxides would lead to a prohibitively large number of options. We solve this problem by training support vector regression models based on the data generated for the primary and binary oxides to predict the properties of ternary and more complex oxides. By combining the trained models, we construct an objective function that, at its minimum, points to the optimal composition in terms of electronic performances and material stability. After screening a series of objective functions, we identify the Zn-Mg-Al-O metal oxide (Zn and Mg around 40-50 at%, Al below 10 at%) as being the most interesting improvement to the current industry standard a-IGZO for the development of a high charge carrier mobility layer of a thin film transistor compatible with low deposition temperature requirements. It is predicted to combine an improvement in terms of electron mobility and chemical stability with respect to a-IGZO. This method, combining first principles calculated data with AI, is however not restricted to finding new materials for the active layer in a thin film transistor. From a general perspective, this approach can be used for any alloy or compound discovery problem, in which the pivotal material properties can be calculated for, in the order of a thousand, relevant one- and two-element materials.

ispartof: ACS APPLIED ELECTRONIC MATERIALS vol:4 issue:4 pages:1823-1831 status: published

We propose, for the first time, an indium gallium zinc oxide (IGZO)-based 2T1C compute cell (IGZO-cell) for analog in-memory computing. To assess the impact of an IGZO-cell-based array including the periphery on power and accuracy, a PyTorch framework was developed to analytically modeled analog components. The results are reported for a ResNet20 network on the Canadian Institute For Advanced Research-10 (CIFAR-10) benchmark. The state-of-the-art energy efficiency of 15 peta operations per second (POPS)/W including the periphery is achieved by using our proposed IGZO-cell with CMOS compatibility. Finally, it is shown that, with a properly trained neural network model, there is no degradation of test accuracy with 10% device to device variability for the IGZO devices.

The use of carbon-based (C-based) liners is investigated for RESET current reduction in self-heating, pillar-shaped phase-change memory (PCM) cells for storage class memory (SCM) technologies. The liner is inserted between the top electrode and the phase-change layer. A finite element analysis (FEA) is done to simulate the effect of this liner on the RESET current, using the melting current as a proxy. From this FEA, we see that the high resistance of the C-based liner increases the heat generation at the interface with the phase-change layer, changing the cell from being solely self-heated by the phase-change layer to a combination of the phase-change layer’s self-heating and heating from the C-based liner. The simulation results are validated against experimental results from fabricated pillar cells. We show the liner reduces the melting current of the pillar cell by 60%. The effect of the thickness of the C-based liner and the phase-change layer on the melting current is quantified, showing a strong dependence on the liner thickness and a weak dependence on the phase-change layer thickness. These findings can guide the design of PCM cells with high-resistance liners between the electrode and phase-change layer for RESET current reduction.

In this work, IGZO device integration is reported leveraging our 300mm-fab facilities. Our objective is mainly to gain insights into the process and material elements which drive the control of the performance parameters of IGZO nFETs. To control the final doping of the IGZO channel, it is well reported in literature that a final oxygen anneal can be applied to passivate the oxygen vacancies which are formed during the device fabrication. This technique is also used in our 300mm flow. As it might be expected, in front gate IGZO nFETs, the passivation efficiency is limited by the presence of the top metal gate stack. Therefore, it seems important to limit the formation of the oxygen vacancies during the deposition of the gate dielectrics. Three oxides were studied: SiO2, Al2O3 and HfO2 on top of the IGZO channel. After oxygen annealing, only PECVD-SiO2 shows a large recovery while for Al2O3 and HfO2, it remains low. This result challenges the implementation of conventional water-based high-K materials in gate first IGZO integration. Contrary to the use of undoped IGZO in the channel for IOFF control, contacts can rely on maximizing the oxygen vacancies to increase the dopant concentration in the S/D regions. When not done locally, it could be an extra source of variability. This doping is made through oxygen scavenging from IGZO by a thin metal contact barrier. Low specific contact resistivity down to 1x107 Ohm.cm2 is demonstrated when Ti is thinner than 5nm. With thicker barrier, the formation of TiO2 and specific alloys is taking place at the IGZO/Contact barrier interface. This is both confirmed by ab initio simulations and by advanced physical characterization techniques. Regarding the channel, X-ray diffraction techniques are extensively here since this is a nondestructive in-fab technique that provides detailed information about the crystallographic structure of the IGZO material. We show a typical spectrum where clear peaks/humps are seen and attributed to: 1. amorphous IGZO, 2. CAAC-IGZO and 3. a previously not reported, to the best of our knowledge, phase called here s-IGZO. The s-phase is only formed under certain conditions of power, temperature and oxygen flow during material deposition. Thick IGZO (>12nm) back-gated nFETs with active layers submitted to final O2 anneal are used to study the different phases of IGZO and their electrical impact on device parameters. In this configuration, the carrier transport preferentially occurs in the bottom half of the IGZO channel while the top half (SiO2/IGZO interface) mostly drives the electrostatic control of BG transistors. The amorphous IGZO has much reduced spread in VTH-ON and higher ID,LIN (~mobility) than that of CAAC-IGZO. Reliability tests have also been carried out to compare the two phases and the results show the existence of two competing PBTI degradation mechanisms for CAAC-IGZO. It is important to report the degradation over time and different VG stress because a cut line at a specific value could have shown no BTI degradation of CAAC-IGZO and then attributing an unfair benefit of this phase over the a-IGZO phase. Combining these findings to some other results where the sheet resistance of IGZO under hydrogen exposure depends on the phases, we can reasonably conclude that CAAC owns different doping levels in comparison to a-IGZO. Based on the previous learning about n-type dopant location in IGZO, we show that the performance of transistors keeps increasing when the channel length is reduced and scales with the channel width. A measure of the VTH-ON variation has been performed at the 300mm wafer scale from long to ~120nm LCH and down to 200nm WCH dimensions. The figure in attachement shows the Id-Vg curves of >100 Back Gated IGZO-nFETs with no failed devices detected. The standard variation of the VTH-ON across LCH and WCH is often less than 40mV with a minimum of 20mV. In conclusion, we have demonstrated in this study scaled IGZO nFETs with excellent VTH_ON control using an industry compatible 300mm process flow. This has been achieved thanks to a careful mapping of n-type doping in the three dimensions of the IGZO channel. While semi-crystalline IGZO seems to be more robust against hydrogen than that of amorphous-IGZO, a new IGZO phase is found to help boost ION at short channel. The demonstration of back-gate IGZO nFETs with low variability and relatively high drive will benefit to the top-gate architecture development. This will provide new opportunities for the IGZO-based devices like an “on-the-fly” VTH setting for the performance control of advanced applications. Figure 1

ispartof: 2022 INTERNATIONAL ELECTRON DEVICES MEETING, IEDM ispartof: International Electron Devices Meeting (IEDM) location:CA, San Francisco date:3 Dec - 7 Dec 2022 status: published

ispartof: 2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) ispartof: IEEE International Electron Devices Meeting (IEDM) location:CA, San Francisco date:11 Dec - 16 Dec 2021 status: published

We report for the first time a fully 300-mm stacking-compatible capacitor-less DRAM cell with >400s retention time by integrating two IGZO-TFTs in a 2T0C configuration. We optimize the single IGZO-TFT performances by engineering the materials surrounding the IGZO layer and the transistor layout parameters. We thus introduce a novel IGZO-TFT device and demonstrate a scaled transistor (W = 70 nm, L = 45 nm) with optimal V th reproducibility on 300-mm wafers. By integrating the IGZO-TFTs in a 2T0C configuration, we systematically assess reproducible long retention time for different transistor dimensions, thanks to the extremely low extracted IGZO-TFT off-current (~3x10-19A/µm).

Switching mechanism and its controllability in Ovonic Threshold Switching (OTS) devices are systematically investigated by using Si-Ge-As-Se quaternary system known as promising OTS materials. We newly demonstrate that selector device performance is flexibly tunable by controlling fall time of switching pulse as well as operation current. Meanwhile, As- and Si-incorporation are found to be beneficial in terms of stable operation and faster recovery. All results are consistently understandable by extended percolation cluster model, supported by ab-initio and Monte-Carlo simulations.

In this work we explore the composition space of the Ovonic Threshold Switch (OTS) selector device based on Si-Ge-As-Te material system. Physical Vapor Deposition (PVD) co-sputtering capabilities enabled the tuning of the As/Te ratio, Ge and Si content to increase the crystallization temperature TX>450°C. Guided by ab initio calculations, we optimize the composition and achieve stable endurance characteristics of more than 1011 cycles on 65nm devices fabricated on 300mm wafers. Finally, we propose a switching model that can predict the statistical distribution of the threshold voltage (VTH), explaining V TH drift and time-dependent instabilities.

In this abstract, we report for the first time the low-current performance enhancement combined with the improvement of the scaling potential in CBRAM devices by adopting an etch-friendly alternative material, Co, as active electrode, based on theoretical considerations and experimental results. Co is proven to yield, with respect to Cu, faster/lower voltage switching and more stable conductive filaments, irrespective of the switching layer, thanks to its higher cohesive energy. By further optimizing the switching layer, we show that the introduction of Co as active electrode is a breakthrough for boosting CBRAM performances, enabling fast and low-power switching, long endurance lifetime and optimal data retention.

We thoroughly benchmark the reliability of Cu-based CBRAM stacks with different switching layers against state-of-the-art OxRAM stacks. We optimize the switching conditions for maximizing the endurance lifetime in three CBRAM stacks, outlining the impact of the switching layer on the energy required for the switching operation and on the memory window. We show that CBRAM provide a larger memory window than OxRAM, but the switching energy is systematically higher, and the endurance lifetime is shorter. We also demonstrate that the larger memory window of CBRAM degrades over time and is thus only an apparent advantage with respect to OxRAM. Therefore, this study reveals that OxRAM devices investigated in this work are more suitable candidates than for applications targeting long data retention and low programming voltage.

Epitaxial In x Ga1– x As is grown by metal organic vapor phase epitaxy as replacement of polycrystalline silicon (Si) channel for high-density 3-D NAND memory applications. The most challenging steps to integrate In x Ga1– x As are thoroughly discussed; their impact on the electrical performances are investigated and the tunnel oxide (TuOx) quality is assessed. In x Ga1– x As channels with a diameter down to ~45 nm and different In concentrations are obtained after using two alternative surface preparation routes: HCl and Cl2. Thanks to the lower thermal budget involved, Cl2 seems the most suitable route to preserve the thickness of the TuOx. In x Ga1– x As channels with In concentration, x, higher than 0.45 have superior conduction properties compared with poly-Si channel, showing higher $I_{\mathrm { {on}}}$ and transconductance.

We demonstrate the fabrication of strontium titanate (STO) based metal-insulator-metal (MIM) capacitors with very-high dielectric constant (k∼118) and low leakage of 10−7 A/cm2 at ±1V for a ∼11nm thick dielectric using Ru as bottom electrode (BE) and top electrode (TE). The k enhancement is attributed to the formation of an ultrathin cubic SrRuO 3 phase at the Ru/STO bottom interface, acting as a template optimizing the STO crystal quality from the interface to the bulk. This interface quality is evidenced by the same k∼118 extracted from STO thickness series and relating to the bulk-k value. This achievement opens up an alternative integration roadmap for DRAM capacitors, moving from the current cup-shape to a denser pillar-shape design.

We study the impact of HPAP on SCC 3D NAND devices. We show that the process can reduce trap density but is leaving trap impact on devices V T unaffected. It is also shown, both by simulations and measurements, that further scaling could lead to the increase of single trap impact. Finally, we measure that despite largely improving devices electrical parameter, HPAP has no effect on memory performances (Program/Erase) or could slightly degrade it (Retention).

Co/LaSiO conducting bridge random access memory is a promising candidate for low power storage class memories due to its high endurance and short switching pulse width. Moisture has been hypothesized to be an important parameter in determining device retention. In this study, we anneal the LaSiO layers at different temperatures and pressures in order to reduce the absorbed moisture and improve retention. We evidence by Fourier transform infrared and x-ray reflectivity that the moisture content does not change with these anneal conditions. However, we find that increasing the amount of La–OH bonds is an effective way to improve the low resistance state retention.

We are demonstrating for the first time epi-based monocrystalline silicon macaroni channel 3-D NAND devices. The highly controllable channel replacement process sequence leads to > 95% yield, with excellent uniformity and reproducibility, proving its potential for manufacturability. The electron mobility of the channel is improved by a factor 30 compared to the polycrystalline macaroni Si channel, together with a reduction of the off state leakage. Furthermore, this channel replacement fabrication process does not affect memory performance and reliability. The performance benefits of this channel replacement technique make it a potential candidate for fabricating future 3-D NAND devices.

In this paper we demonstrate a unipolar selector based on Cu-based active layer. Volatile conductive bridge concept is explained by the means of electrical results and material properties such as device area, Cu-based active layer -thickness and composition. Beside the standard stack, the integration of a thin interfacial layer of 1nm metal oxide allows to improve VCB nonlinearity up to 6 decades, by decreasing initial current leakage to 1nA and switching V to 2.5V/1μs. Good endurance behavior is shown with more than 1E5 cycles obtained without degradation. Good switching temperature stability is demonstrated up to 125oC for both standard and HfO2/Cu-based stacks.

In this paper, Epi-Si process is used to investigate the impact of traps and grain boundaries in vertical 3D NAND. With this channel morphology, we show that the defects have a reduced impact on device performances compared to the usual poly-Si channel devices. These results are also confirmed and extrapolated to other geometry using 3D TCAD simulations.

An in-depth analysis of gate stack enhancements that enable multi-Gb 3D NAND products is performed. Alternative charge trapping layer, enhanced tunnel oxide based on the VariOT concept and metal gate with Al2O3 high-k liner have been proposed and evaluated. The most promising solutions were successfully integrated in 3D devices. Integration challenges of the replacement gate approach, required to have metal gate in 3D NAND, are also analyzed and discussed in detail.

We demonstrate for the first time a 20% [Ge] SiGe Macaroni channel in 3D NAND. Two alternative integration routes have been explored and High Pressure Annealing Process in D2 ambient has been applied to improve the channel and the channel-SiO2 interface. Electrical performance indicates that SiGe can improve channel conduction, with minimal impact on memory performance, but has intrinsically worse off-current properties than Si.

GeSe-based amorphous compounds are excellent candidates for the fabrication of Ovonic Threshold Switching (OTS) selectors in two-terminal high density Storage Class Memories (SCM) [1]. In the as-deposited state, the layer is amorphous but it can be transformed into a low-resistive state above a certain threshold voltage. Good thermal stability of the layers is of crucial importance [1] and is closely linked to the defectiveness [2], which also defines the carrier transport. In such OTS materials, the current cannot be described in terms of the classical drift-diffusion theory, assuming a well-defined band gap. Instead, it has been shown that carriers are localized in the deep potential of attractive traps, where they move by field-assisted hopping [3]-[5]. Characterization of the trap states is thus key to the understanding of the transport and the stability/drift of the layers. One of the standard methods to study deep level traps in semiconductors is Deep Level Transient Spectroscopy (DLTS), which has also been applied in the past to amorphous materials. The aim of the present paper is to apply this method to the study of the Physical Vapor Deposited GeSe layers on p-type silicon substrates. As will be shown, the observed hole traps around activation energies in the range of 0.2 eV to 0.5 eV exhibit a broad distribution of states and non-exponential trap filling kinetics. This will be discussed in view of the transport mechanisms in the layer. For DLTS, Metal-Insulator-Semiconductor (MIS) structures have been prepared by the deposition of 20 or 50 nm of GexSe1-x with x~0.5 on p-type CZ silicon substrates; deposition of an Al gate completes the fabrication of the devices, with a structure schematically represented in Fig. 1. The Capacitance-Voltage (C-V) characteristics typically exhibit a significant flat-band voltage shift with temperature T (Fig. 2), which should be accounted for when performing DLTS on such capacitors by adjusting the reverse and pulse bias. Comparing the results of two layers deposited under different conditions in Figs 3 and 4 indicates that the hole trap peak in DLTS changes both in amplitude (the trap concentration) and temperature position, i.e., the activation energy. The latter is derived from the slope of the modified Arrhenius plot of Fig. 5. Values in the range of 0.2 eV to 0.5 eV with respect to the valence band maximum in GeSe have been observed, which is in line with the density of states extracted from ab initio Density Functional Theory (DFT) calculations [2]. A final experimental observation is demonstrated in Fig. 6, showing the evolution of the hole trap filling as a function of the bias pulse time tp. Widely different behavior can be observed, which is not typical for point defects. In conclusion, it can be stated that the feasibility (and reproducibility) of DLTS on these structures has been validated. At the same time, it is clear that a meaningful extraction of the trap parameters should account for the specific transport mechanisms in the amorphous GeSe material. [1] B. Govoreanu et al., in 2017 Symp. On VLSI Technol. Dig. Of Techn. Papers, IEEE Explore, p. 92 (2017). [2] S. Clima et al., in Int. Electron Devices Meeting (IEDM17) Techn. Dig., IEEE Explore, p. 79 (2017). [3] D. Ielmini and Y. Zhang, J. Appl. Phys., 102, 054517 (2007). [4] D. Ielmini, Phys. Rev. B, 78, 035308 (2008). [5] A. Calderoni, M. Ferro, D. Ielmini and P. Fantini, IEEE Electron Device Lett., 31, p. 1023 (2010). Figure 1

In this paper, we investigate the effect of High Pressure Hydrogen or Deuterium Annealing on a vertical charge trapping NAND memory device. Strong improvement is obtained in Vt, subthreshold slope and drive current of the transistors by a better passivation of charge by either species in the bulk ONO memory stack, at the interface between ONO and Poly-Si channel, and in the bulk Poly-Si. Program / Erase and Retention remain identical, and no benefits could be observed by using D2 instead of H2 as passivating species in terms of robustness towards program/erase cycling damages.

In this article we use a novel method to assess the retention properties of a PCM line cell having a fast-growth chalcogenide material. We monitor the cell resistance during temperature-ramp experiments carried out after reset programming of the cells. The temperature-dependent resistance is modeled assuming the crystallization proceeds by the crystal growth of the amorphous/crystal interfacial front. The results show good reproducibility, excellent match with the measurements, and consistency with investigations using isothermal experiments. For a single temperature-ramp experiment this fast method allows the extraction of the activation energy for growth as well as the extrapolated temperature for 10 years retention lifetime. We use the method to investigate the influence of the length and thickness of the programmed amorphous mark on the retention lifetime. The results point to improved retention for thicker and longer amorphous marks, however the extrapolation of the results down to short marks suggests a limited reduction of the retention lifetime with the cell downscaling.

In this brief, we studied the endurance properties of an integrated phase-change line cell. The different characteristics typically observed during the endurance lifetime are described. The monitoring of the switching parameters of the cell (reset current and threshold voltage) during endurance testing could be correlated with a gradual degradation of the reset switching. The following conclusions were drawn: 1) The reset-switching degradation is closely associated to both an increase of the minimum reset current and a decrease of the obtained reset and set resistances, pointing to material change; 2) the extent of the degradation strongly depends on the reset pulsewidth, and it was found to scale with tm 3/2, tm being the melting time during reset pulse; however, higher reset currents did not quicken the onset of degradation; and 3) the tm 3/2 dependence together with polarity-dependent endurance tests suggests the contribution of an electrical-field-driven migration mechanism. Based on these insights, the extended endurance lifetime of more than 1010 cycles could be demonstrated, using short reset pulses, which could be further increased by changing reset polarity before stuck-set failure.

As an economically more attractive alternative to the classical thick graded strain-relaxed SiGe Buffer layers (SRB), we have developed a thin SRB based on a 200-nm-thick homogeneous Si 0.8 Ge 0.2 l ayer with a C-doping spike inserted in about the middle of the layer. This C-doping layer enhances strongly the relaxation of the layer to ∼ 80%, when compared to samples without C layer. The thin SRB shows threading defect densities ≤ 10 7 /cm 2 and a very smooth surface (RMS

A set of direct techniques were combined to resolve the carrier recombination, trapping and diffusion parameters in thin strain-relaxed SiGe buffer (SRB) layers in a contact-less way. The excess carrier density relaxation in a wide time scale from picoseconds to tens of microseconds was examined by the microwave absorption/reflection and light-induced reflection/grating transients. A decrease of recombination lifetime in nanosecond-time scale as a function of threading dislocations (TD) density was determined. The asymptotic hyperbolic-like carrier decay in the SRBs was ascribed to multi-trapping processes characterized by trapping coefficients Ktr > 10. Relaxation of multi-trapping in the disordered structure of the dislocation-rich SRBs was generalized by the stretched-exponent approach. The time-stretching index of 0.15 was found to be the same for dislocation-rich SRBs, containing different densities of TDs. Value of the lateral carrier ambipolar diffusion coefficient Da ≤ 0.13 cm2 s−1 was estimated. Peculiarities of the J–V characteristics of diodes fabricated in the SRBs were examined and attributed to the space charge limitation effects. These features correlate with carrier trapping and slow diffusion unveiled by transient techniques.