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Abstract: This paper analyses the performance of 5 nm gate length gate engineered oxide stack silicon on insulator (SOI) fin field-effect transistor (OS-Fin-FET) for the first time. The high dielectric (High-K) value of the material-based gate oxide stack structure increases both the analog and the radio frequency (RF) performance of the Fin-FET device when compared to standard single gate oxide material structures. The work function of the engineered gate structure further helps in advancing the performance of the device in terms of on current (Ion), off current (Ioff) and the ratio of Ion/Ioff. The proposed OS-FinFET device improves on current (Ion) of the device by 12% in comparison to the high-K dielectric gate oxide-based FinFET device. Simulation of the device is further extended to study different electrical characteristics of the proposed device under other biasing conditions, to estimate enhanced analog and RF performance where the device is highly suitable for low power and high-speed applications. Overall, the proposed device shows improvement in existing architectures of the devices. Technology computer-aided design (TCAD) tool is used to perform entire simulations of the proposed device with 5 nm gate length. Aim: To enhance analog and RF performance of the Fin-FET device at 5 nm gate length. Background: Design of the sub-10 nm Fin-FET device undergoes charge shearing phenomena because of the minimum distance between source and drain. This problem is addressed by using High-K spacer over substrate but it leads to increase in the channel resistance and adverse short channel effects. A combination of different high-K dielectric materials can eliminate this performance. Hence most of the studies concentrated on spacer region and failed to consider channel region. This study tries to improve analog performance of the device using the approach of gate engineering with gate stack approach. Objective: The main objective of this study is to increase on current (Ion) of the device by implementing gate engineering approach, by choosing dual work function-based gate with oxide stack approach. The High-K dielectric material-based gate oxide reduces leakage current, decreases off current which will increase the ratio of Ion/Ioff. Methods: The dual work function gate material is taken with gate oxide stack approach by considering different High-K dielectric materials like HfO2, TiO2 with thin SiO2 layer as the interactive layer. Simulation of the device is carried out using TCAD Tool and results are compared with existing literature, to validate the results. Results: The proposed architecture of the Fin-FET device delivers excellent results in terms of on current and subthreshold characteristics compared to existing literature. The proposed device gives high on current of 0.027 A and current ratio of 1.08X104. Conclusion: A complete comparative analysis is carried out with existing literature on the proposed device, where the proposed device resulted in high performance. The proposed device improves 12% compared to existing literature, which is highly suitable for low power applications.

This study aims for a new 11T static random access memory (SRAM) cell that uses power gating transistors and transmission gate for low leakage and reliable write operation. The proposed cell has a separate read and write path which successfully improves read and write abilities. Furthermore, it solves the row half select disturbance and utilises a row-based virtual ground signal to eliminate unnecessary bit-line discharge in the un-selected row, thus decreasing energy consumption. The cell also achieves low power due to the stack effect. To show the effectiveness of the cell, its design metrics are compared with other published SRAM cells, namely, conventional 6T, 10T, 9T, and power-gated 9T (PG9T). In standby mode, from 6.71 to 7.37% leakage power reduction is observed for this cell at an operating voltage of 1.2 V and 29.21 to 58.68% & 32.74 to 71.11% improvement for write & read power over other cells. The proposed cell exhibits higher write and reads static noise margins with an improvement of 13.54 and 63.28%, respectively, compared to conventional 6T SRAM cell. The cell provides write delay improvement from 29.77 to 49.40% and read delay improvement from 7 to 12% compared to 9T, 10T, and PG9T, respectively.

A novel 9T-SRAM architecture is proposed in this paper. It smartly integrates the source biasing and body-bias control schemes in designing an SRAM cell. The proposed cell consists of nine transistors with separate read/write ports. It uses a read word-line based body bias controller and two tail transistors in pull-down path to improve the design metrics. The main objective of the proposed architecture is to minimize the leakage current in an SRAM cell while improving the stability and reducing the read/write delays. The above design metrics of the circuit are compared with the conventional 6T, LP10T and WRE8T SRAM cells under process and temperature variations. It is observed that as compared to conventional SRAM, the proposed 9T SRAM architecture (8 × 16 arrays) reduces static power consumption by 98%, improves the read and write stability by 66.07 and 10.51% respectively. Again, the write delay is reduced to about 95% while read delay is minimized to about 64.1% under different body-bias voltages.

In this paper, we present a new 10T design for static random access memory (SRAM). The proposed design simultaneously aims to address stability, power and half select issues. The design metrics such as power, delay, and stability of the proposed design are compared with 7T, 11T, and 9T SRAM cells. It is observed that the proposed design reduces read and write power by 27.69% and 41.72% as compared to 11T and 9T SRAM cell. Furthermore, WSNM of the proposed SRAM is larger as compared to 7T, 9T and 11T. In addition, the RSNM is larger than 7T and 9T. The simulation result confirms that the proposed design is effective for low power application.

Leakage power dissipation is a serious concern in deep nanometer devices. Low power design methodology is often adopted in VLSI circuits and systems to minimize power; however, this is achieved at the cost of performance penalty. In this paper, we first review the existing circuit techniques for leakage minimization. A new circuit technique is then proposed which is designed intelligently by mixing a pair of dynamic threshold sleep transistors and a pair of helper transistors. The performance of the proposed technique is investigated in terms of area, power, delay and power---delay product. Extensive SPICE simulation with 32 nm process technology shows a significant reduction in power, delay and power---delay product.

A dynamic threshold voltage control strategy is presented in this paper to minimize leakage power while enhancing the speed and stability. The threshold voltage of driver and access transistor are tuned dynamically through a novel body-bias controller circuit. The word line signal level controls the action of the proposed body-bias controller. In order to reduce subthreshold leakage current, the threshold voltage of NMOS access and driver transistors are adjusted to a high value by applying a reverse body-bias. On the other hand, forward body-bias lowers the threshold voltage of NMOS access transistor thereby enabling faster read and writes operation. Simulation results shows that the proposed design is much better than conventional and other SRAM cells such as, NC SRAM, PP SRAM, WRE8T. The amount of leakage power reduction is as high as 41.071 % over conventional 6T SRAM cell when tested on (8 × 16) SRAM array. Whereas, the improvement in read and write delay is 30 and 15.81 % respectively.

Leakage power dissipation is the dominant contributor of total power dissipation in nanoscale complementary metal oxide semiconductor (CMOS) integrated circuits. CMOS technology scaling demands for a reduced power supply, low threshold voltage, high transistor density and reduced oxide thickness, which has led to significant increase in leakage power especially during standby mode. Here in this paper, at first we review some of the existing techniques for leakage minimization and pointed out their merits and shortcomings. We then propose a novel transistor level approach called leakage control NMOS transistor (LCNT) for leakage minimization. The proposed technique inserts two leakage control transistors (all N-type) within a standard CMOS logic circuit. The gate terminal of the leakage control transistors are connected with the drain of the pull-up transistors. Performance of the proposed technique is investigated in terms of area, power, delay, and power-delay product applying on some basic gates and benchmark circuits. The performance metrics of the proposed LCNT are then compared with other existing techniques. Extensive SPICE simulations were carried out using 32 nm predictive technology model. Simulation results indicate that the proposed technique is quite efficient in minimizing the leakage power which is found out to be 48.4 %.

Ever increasing demand for portable and battery-operated systems has led to aggressive scaling. While technology scaling facilitates faster and high-performance devices, at the same time it causes excessive power dissipation especially the leakage. Leakage power dissipation is now a dominating component of total power consumption in today's high-performance chip. So there is a tremendous need to limit the power dissipation in high-density chips, which has initiated many innovative techniques to develop in the design of low power circuits and systems. Nano-scaled very large-scale integration (VLSI) chips have ultra-thin gate oxide, very low threshold voltage, and have short channels. Therefore, leakage power dissipation has emerged as the most challenging issue in VLSI circuit and systems. In this paper, we present a general review of the state-of-the-art circuit level leakage minimization techniques since 1995. It also conceptually classifies the different techniques for leakage minimization. Furt...

Ever increasing demand for portable and battery-operated systems has lead to aggressive scaling. While technology scaling facilitates faster and high performance devices, at the same time it causes excessive power dissipation. Leakage power dissipation is now a dominating component of total power consumption in such portable devices. So there is a tremendous need to limit the power dissipation in high density chips which has initiated many innovative techniques to develop in the design of low power circuits and systems. Today's nano-scaled VLSI chips have ultra-thin gate oxide, very low threshold voltage and having short channels. As such leakage power dissipation has emerged as the most challenging issue in VLSI circuit and systems. This Chapter review and compare the state of the art circuit techniques for leakage minimization. It also conceptually classifies the different techniques of leakage minimization. Moreover, a detailed comparison based on trading-offs with other design parameters is also given along with leakage minimization.

In this paper, a comparison between Single Gate Fully Depleted SOI (SGSOI) and Double Gate Fully Depleted SOI (DGSOI) MOSFET with Si3N4 Spacer (insulator) around the Gate electrode at various different technology nodes are investigated. Simulations are done in ATLAS package of SIVACO tool. Further in this work, study of SON Devices (structure with air in place of buried oxide is termed as Silicon on Nothing (SON) are carried out. Simulation of Different values of Drive Current (Ion), Leakage Current (Ioff) and Transfer Characteristics (Id/Vg) are analysed in addition to compare and get a suitable conclusion of this study. For comparing the suppressed values of Short Channel Effects, Drain Induced Barrier Lowering (DIBL) with these different structuresarecalculated. All the structures are simulated for Single Gate as well as Double Gate in nanometerregime. Comparative results are given on the basis of the simulated results received by the double gate structure with Vertical Source and Drain (SD). Effect of Channel length reduction on its transfer characteristics and short channel effects are also studied. It has been found that SON structure shows larger threshold voltage value but small drive current as compare to SOI structures. Hence due to its low leakage current, it seems to be better for low power applications. Double gate SOI structure showsa sufficient drive current and less leakage current as compare to single gate SOI. For analysing the performance of the devices, Shockley-Read-Hall (SRH) Recombination, Radiative, Auger, and Surface Recombination models are deployed.

This paper presents a novel design to reduce sub threshold leakage current. The leakage controlled transistors are utilized to change dynamically the ground voltage level which is based on output voltage level of logic gate. The leakage controlled transistors (LCT's) are utilized to reduce the leakage power and static energy consumption (static power-delay product) while maintaining the performance of delay. Simulation result based on 32nm Berkeley predictive technology model shows that the proposed technique achieves better performance than conventional designs.

This paper presents a comprehensive survey and analysis of various subthreshold leakage power reduction techniques. Moreover, a new technique for low leakage and high speed is also proposed here. As the technology scales down to deep sub micron level, leakage power dissipation increases very rapidly due to the high transistor density, low threshold and ultrathin dielectric. The new proposed circuit technique includes NMOS sleep and helper transistors to reduce leakage current with appropriate W/L ratio. The proposed design gives high speed performance because it includes NMOS transistor in the design which is having higher electron mobility. Post layout simulation of XOR gate using microwind tool with 45nm Berkeley predictive technology model shows that the new circuit technique achieves significant power reduction during a standby mode with lesser delay.

Leakage power dissipation has become a dominating proportion of the total power dissipation. According to international technology roadmap semiconductor (ITRS), this directly affects the portable battery operated device like mobile phones. A detailed analysis of leakage reduction data retention leakage feedback approaches are discussed in this paper. We here propose a new design data retention scheme which consist PMOS helper transistors which reduces leakage current while saving exact logic state. Based on simulation with inverter chain using 32nm Berkeley predictive technology model, the proposed approach demonstrate that PMOS helper transistors leakage feedback technique reduces considerable amount of leakage in CMOS circuits.

Leakage power consumption has become serious concern for circuit designers. It is expected that leakage power will dominate the total power dissipation in future VLSI circuits. We here propose a new design named “NMOS leakage feedback” which reduces leakage current while saving exact logic state. The circuit technique includes addition of NMOS helper transistors to both pull-up and pull-down paths in order to reduce leakage current without affecting the other parameters of the circuit. Based on simulation with inverter chain using 32nm Berkeley predictive technology model, NMOS leakage feedback approach achieves less area, power and delay over leakage feedback approaches with proper W/L ratio.

In this paper we propose a new structure for NMOS based leakage feedback approach. The new proposed circuit technique includes NMOS only sleep transistors in parallel to both pull-up and pull-down paths which will reduce subthreshold current while saving the exact logic state. Based on 45nm Berkeley predictive technology model (BSIM 4), post layout simulation on microwind shows that as compared to conventional logic, the proposed design with a supply voltage of 0.9 V at 27°C achieves better power and delay performance than conventional design.

Now a day's low power Design is a essential requirement for This electronic document is a “live” template. The various components of your paper [title, text, heads, etc.] are already defined on the style hardware implementation. Technology moving into deep submicron region causes increase in leakage power. MTCMOS is promising technique for reducing leakage power but use of this technique results in delay overhead in active mode and data retention problem for sequential circuit. This paper propose a design technique for reducing the leakage power and data loss problem during sleep mode. Simulation results show that reduction in leakage power while preserving the state of the circuit.