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Lithography process variation as well as etch and topography have always been a stubborn challenge for advanced technology nodes, i.e. 14nm and beyond. This variability usually results in defects aggregating around the edge of the wafer and leading to yield loss. A very tight process control is the logical resolution for such issues, nevertheless it might not be possible, or it may slow down the whole design to silicon cycle time. Another degree of difficulty is detecting these defects in ORC and concluding an OPC fix. In this paper, we show that aerial image ORC checks could provide a very useful insight to these defects ahead of time, and that they correlate well with silicon defects highlighted by CFM scan. This early detection upstream enables us to conclude a generic OPC fix for such issues and also improves the total OPC process-window enhancement and eliminates these defects on silicon.

This paper describes a volume diagnosis infrastructure built on open-source software, which addresses practical challenges in a foundry environment by integrating various data sources from design, manufacturing process and test to enable rapid root-cause identification.

This column discusses the benefits of using IC design and wafer-processing test data for failure analysis.

Fast yield ramp is very important for a foundry during advanced process development and volume production. Logic and SRAM circuits are the major design blocks in advanced Integrated Circuits. Identification of systematic failures in logic and SRAM blocks using product test and diagnostics is critical to increasing the speed of yield learning in sub-40nm ICs. This paper highlights the importance of using logic and SRAM diagnosis for product yield ramp using three yield breakthroughs.

A fast, production-ready yield learning methodology to identify and score critical hotspot patterns in an integrated circuit (IC) design is presented. The methodology, named SpotMe, correlates simulation-based design hotspots with inline defect inspection and enables co-optimization of process simulation models and defect inspection methods. The methodology is demonstrated on a 28nm GLOBALFOUNDRIES testchip and is validated using volume diagnosis results.

The shrinking dimensions with advanced technologies pose yield challenges which require continuous enhancement of yield methodologies to quickly detect and fix the marginal layout features. In this paper, we present a practical approach to enhance the DFM and DEM capabilities suite provided by GLOBALFOUNDRIES for 28nm technology and beyond. The MDRT system has been implemented in the Product Lifecycle Management (PLM) system within GLOBALFOUNDRIES.