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An ultralow-power direct-conversion Bluetooth-low-energy (BLE) receiver (RX) front-end that employs current-reuse and subthreshold techniques is presented. A stacked and self-biased low-noise amplifier (LNA) with active balun consumes 400 μW and achieves a noise figure (NF) of 3.2-dB and a high gain (programmable from 18 to 31 dB), meeting the system specifications over the process, supply voltage, and temperature (PVT) variations. The RX front-end has a measured integrated NF of 5.2 dB from 50 KHz to 1 MHz that corresponds to a sensitivity of −95.1 dBm. At an RX gain of 47 dB, IIP3 was measured at −19.7 dBm. The LC VCO operates at twice the carrier frequency with a tuning range of 4.55 to 5.15 GHz in an integer-N phase-locked loop (PLL). An ultralow-power CML divider is used to generate the LO I/Q. The integrated phase noise (IPN) of the LO at 2.4 GHz is 0.83° with spot phase noise of −119.9 dBc/Hz at 3 MHz frequency offset. The PLL is entirely placed inside the VCO inductor resulting in an overall die area reduction of 8%. A 6-μW automatic dc offset-calibrator avoids saturation of consecutive baseband blocks. Multiple μW-level feedback control loops are used in the design to make it robust over PVT variations. The RX front-end prototype is implemented in a 40-nm LP CMOS process and occupies a silicon area of 0.7 mm2. [ABSTRACT FROM AUTHOR]

A 168-fs rms jitter, 48-MHz differential crystal oscillator based on a new active inductor biasing circuit achieves differential operation with low noise, power, and area overhead. This architecture has two significant advantages compared to the single-ended crystal oscillators that are normally used: 1) this circuit rejects power supply noise and interference which leads to lower jitter and 2) the crystal oscillator-induced spurious tones are smaller and therefore less detrimental to sensitive blocks (e.g., LNA) in RF radios. This paper theoretically analyzes the differential crystal oscillator and provides detailed design considerations. A prototype requires half the power and 80% less area than previously reported differential crystal oscillators. Implemented in a 28-nm LP CMOS process, it draws 1.5 mA from a 1-V supply and occupies 0.013 mm2. [ABSTRACT FROM AUTHOR]

We present a radio system that could be used in millimeter-scale wireless neural implants. The system is RF-powered and demonstrates Mbps data rates required for neuromodulation and recording applications. The radio transmits at 58 Mb/s and receives at 2.5 Mb/s maximum data rates. The transceiver uses a duplexer to achieve full-duplex communication via frequency-division duplexing at 1.74 and 1.86 GHz for TX and RX, respectively. The average power consumption of the transmitter is 93 \mu \textW at 58 Mb/s, while that of the receiver is 7.2 \mu \textW at 2.5 Mb/s. The transceiver was fabricated using 40-nm LP CMOS process and occupies 0.8 mm2 of die area. Including the off-chip duplexer, the system occupies 2 $\times $ 1.6 $\times $ 0.6 mm3. [ABSTRACT FROM AUTHOR]

A millimeter (mm) wave radio is presented in this work to support wireless MRI data transmission. High path loss and availability of wide bandwidth make mm-waves an ideal candidate for short range, high data rata communication required for wireless MRI. The proposed system uses a custom designed integrated chip (IC) mm-wave radio with 60 GHz as radio frequency carrier. In this work, we assess performance in a 1.5 T MRI field, with the addition of optical links between the console room and magnet. The system uses ON-OFF keying (OOK) modulation for data transmission and supports data rates from 200 Mb/s to 2.5 Gb/s for distances up-to 65 cm. The presence of highly directional, linearly polarized, on-chip dipole antennas on the mm-wave radio along with the time division multiplexing (TDM) circuitry allows multiple wireless links to be created simultaneously with minimal inter-channel interference. This leads to a highly scalable solution for wireless MRI. [ABSTRACT FROM AUTHOR]

A fully integrated 2\times2 CMOS transceiver at 60 GHz with energy harvesting capability in the transmitter mode and on-chip dipole antennas is demonstrated. The radio supports on-off-keying (OOK) modulation and a programmable data rate of 38 to 2450 Mb/s at a BER of less than 5\times10^-4. The power consumption of the transmitter scales with data rate from 100 \muW to 6.3 mW at 5 cm range and from 260 \muW to 11.9 mW at 10 cm range. This yields an energy efficiency of 2.6 pJ/b at 5 cm and 4.9 pJ/b at 10cm. The energy harvesting circuits operate at 2.45 GHz with an average efficiency of 33%. The harvesting antenna and its matching components are off-chip. The complete transceiver including the energy harvesting block and on-chip antennas occupies 1.62 mm^2 in 40 nm CMOS. [ABSTRACT FROM PUBLISHER]

A single-chip Bluetooth v2.1-compliant CMOS radio SoC that supports Enhanced Data Rates is implemented in standard 0.13 μm CMOS technology. All functions of a Bluetooth radio are integrated in the SoC, including RF, analog and digital parts. The RF transceiver features a polar transmitter, a two-point modulated fractional-N synthesizer, a 500 kHz IF receiver with first order low-pass analog filtering, and a Δ∑ ADC with 74 dB dynamic range. The total SoC die area is 9.2 mm2 with only 3.0 mm2 for analog and RF circuits. The basic-rate radio power consumption is below 30 mA for both receive and transmit. [ABSTRACT FROM AUTHOR]