19 results on '"Raghavasimhan Sreenivasan"'
Search Results
2. ALD Resist Formed by Vapor-Deposited Self-Assembled Monolayers
- Author
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David W. Porter, Raghavasimhan Sreenivasan, Paul C. McIntyre, Junsic Hong, and Stacey F. Bent
- Subjects
Silicon ,Chemistry ,Analytical chemistry ,chemistry.chemical_element ,Self-assembled monolayer ,Surfaces and Interfaces ,Chemical vapor deposition ,Condensed Matter Physics ,Octadecyltrichlorosilane ,Atomic layer deposition ,chemistry.chemical_compound ,Chemical engineering ,Resist ,Monolayer ,Electrochemistry ,General Materials Science ,Silicon oxide ,Spectroscopy - Abstract
A new process of applying molecular resists to block HfO2 and Pt atomic layer deposition has been investigated. Monolayer films are formed from octadecyltrichlorosilane (ODTS) or tridecafluoro-1,1,2,2-tetrahydrooctyltrichlorosilane (FOTS) and water vapor on native silicon oxide surfaces and from 1-octadecene on hydrogen-passivated silicon surfaces through a low-pressure chemical vapor deposition process. X-ray photoelectron spectroscopy data indicates that surfaces blocked by these monolayer resists can prevent atomic layer deposition of both HfO2 and Pt successfully. Time-dependent studies show that the ODTS monolayers continue to improve in blocking ability for as long as 48 h of formation time, and infrared spectroscopy measurements confirm an evolution of packing order over these time scales.
- Published
- 2006
3. Interface Layers for High-k/Ge Gate Stacks: Are They Necessary?
- Author
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Krishna C. Saraswat, Raghavasimhan Sreenivasan, Hyoungsub Kim, Takuya Sugawara, Chi On Chui, Paul C. McIntyre, F. S. Aguirre-Testado, David Chi, Robert M. Wallace, and Kang-ill Seo
- Subjects
Engineering ,business.industry ,Interface (Java) ,Science and engineering ,Gate stack ,Advanced materials ,business ,Engineering physics ,High-κ dielectric - Abstract
We discuss the effects of interface layers between high-k gate insulators and the Ge substrate on the electrical characteristics of Ge MOS devices. Our work has focused on both germanium oxynitride (GeOxNy) and tantalum oxynitride (TaOxNy) interface layers. We find that ultrathin interface layers of TaOxNy, a high permittivity diffusion barrier, produce greatly improved charge trapping characteristics and promising capacitance scaling for high-k/Ge gate stacks. Effects of interface layers on interface state density and the frequency dispersion of the capacitance-voltage (CV) behavior under inversion are also described.
- Published
- 2006
4. Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20-nm Gate Length
- Author
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Bruce B. Doris, Juntao Li, Ali Khakifirooz, Thomas N. Adam, Hong He, Qing Liu, Alexander Reznicek, Shom Ponoth, J. Kuss, Ghavam G. Shahidi, Kangguo Cheng, Nicolas Loubet, Pranita Kulkarni, and Raghavasimhan Sreenivasan
- Subjects
Materials science ,Channel length modulation ,Equivalent series resistance ,Reverse short-channel effect ,business.industry ,Silicon on insulator ,Nanotechnology ,Time-dependent gate oxide breakdown ,Electronic, Optical and Magnetic Materials ,Logic gate ,MOSFET ,Optoelectronics ,Electrical and Electronic Engineering ,business ,Communication channel - Abstract
We report high-performance extremely thin SOI MOSFETs fabricated with a channel thickness down to 3.5 nm, sub-20-nm gate length, and contacted gate pitch of 100 nm. At an effective channel length of 18 nm, a drain-induced barrier lowering of 100 mV is achieved by either thinning the channel to 3.5 nm or by applying a reverse back-gate bias to 6-nm channel MOSFETs. Moreover, minimal increase in series resistance is seen when the channel is scaled to 3.5 nm, resulting in no performance degradation with SOI thickness scaling.
- Published
- 2012
5. A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
- Author
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Jeffrey C. Shearer, Philip J. Oldiges, Soon-Cheon Seo, Terry A. Spooner, Matthew E. Colburn, Ravikumar Ramachandran, V. Sardesai, Kang-ill Seo, Dinesh Gupta, Richard G. Southwick, Xiao Sun, S. Stieg, H. Cai, S. Kanakasabaphthy, Vamsi Paruchuri, R. Sampson, Lars W. Liebmann, Walter Kleemeier, Kisik Choi, Deok-Hyung Lee, Christopher Prindle, R. Divakaruni, H. Shang, Abhijeet Paul, T. Gow, D. McHerron, Dechao Guo, Fee Li Lie, J. Nam, Neeraj Tripathi, Ruilong Xie, R. Kambhampati, Muthumanickam Sankarapandian, Balasubramanian S. Pranatharthi Haran, Carol Boye, James H. Stathis, B. Hamieh, John Iacoponi, Christopher J. Waskiewicz, Geum-Jong Bae, Derrick Liu, Sanjay Mehta, Reinaldo A. Vega, Terence B. Hook, Min Gyu Sung, Jay W. Strane, D.I. Bae, Robin Chao, Hoon Kim, F. Nelson, Theodorus E. Standaert, L. Jang, Erin Mclellan, M. Celik, S. Nam, Tae-Chan Kim, C.-C. Yeh, Sean D. Burns, P. Montanini, Charan V. V. S. Surisetty, Raghavasimhan Sreenivasan, Ju-Hwan Jung, B. Lherron, S.-B. Ko, E. Alptekin, Huiming Bu, Injo Ok, Jin Cho, Mukesh Khare, J. G. Hong, Gen Tsutsui, Andreas Scholze, Bomsoo Kim, D. Chanemougame, M. Mottura, M. Weybright, H. Mallela, K. Kim, Hemanth Jagannathan, Chanro Park, J. Jenq, Donald F. Canaperi, Young-Kwan Park, R. Jung, and Kangguo Cheng
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Materials science ,Dopant ,business.industry ,Limit (music) ,Gate stack ,Electrical engineering ,Silicon on insulator ,Optoelectronics ,Static random-access memory ,business ,Lithography ,Communication channel ,Power (physics) - Abstract
A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um 2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.
- Published
- 2014
6. Improvement in High-$k$$(hboxHfO_2/hboxSiO_2)$Reliability by Incorporation of Fluorine
- Author
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Krishna C. Saraswat, Raghavasimhan Sreenivasan, Paul C. McIntyre, and Kang-ill Seo
- Subjects
Materials science ,Negative-bias temperature instability ,Annealing (metallurgy) ,Gate dielectric ,Analytical chemistry ,chemistry.chemical_element ,Trapping ,Radiation ,Electronic, Optical and Magnetic Materials ,chemistry ,Fluorine ,Thermal stability ,Electrical and Electronic Engineering ,High-κ dielectric - Abstract
In this letter, we demonstrate that negative bias temperature instability of high-k (HfO2/SiO2) gate dielectric stacks can be greatly improved by incorporating fluorine and engineering its concentration depth profile with respect to HfO2/SiO2 interface. It was found that fluorine is easily incorporated in HfO2/SiO2 at low temperatures (les400degC) by F2 anneal in the presence of UV radiation. Fluorine tends to segregate at the HfO2/SiO2 interface and, to a lesser extent, diffuses into the underlying SiO2/Si interface. The HfO2 /SiO2 stacks with F addition show significantly reduced (
- Published
- 2006
7. Aggressively scaled strained silicon directly on insulator (SSDOI) FinFETs
- Author
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Raghavasimhan Sreenivasan, H. He, James Chingwei Li, T. Levin, Shogo Mochizuki, Ali Khakifirooz, Bruce B. Doris, Darsen D. Lu, Dechao Guo, Pouya Hashemi, Huiming Bu, Benjamen N. Taber, Gen Tsutsui, Frederic Allibert, Bich-Yen Nguyen, S. M. Mignot, Theodorus E. Standaert, Tenko Yamashita, Winston Chern, Alexander Reznicek, C-Y Chen, T-S King Liu, K. Rim, Kangguo Cheng, E. C. Wall, Yunpeng Yin, Nuo Xu, Nicolas Loubet, Veeraraghavan S. Basker, and Pierre Morin
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OR gate ,Materials science ,Silicon ,business.industry ,Silicon on insulator ,chemistry.chemical_element ,Strained silicon ,Strain engineering ,Semiconductor ,CMOS ,chemistry ,MOSFET ,Electronic engineering ,Optoelectronics ,business - Abstract
Strain engineering has been in the heart of CMOS technology for over a decade. However, the effectiveness of conventional strain elements, such as stress liners, embedded S/D stressors, and stress memorization, is significantly reduced when device gate pitch is scaled below 100 nm as needed for 14nm node and beyond. Substrate strain engineering, where the channel itself is formed out of a strained semiconductor, e.g. in the form of strained silicon directly on insulator (SSDOI) or strained SiGe-on-insulator has the advantage that the strain is independent of the device pitch or gate length as long as the active region is made sufficiently long and the strain is maintained throughout the device processing. We have already shown that in a FinFET structure the starting biaxial strain in the SSDOI substrate is converted to a more beneficial uniaxial strain, strain can be maintained throughout typical thermal processing, and demonstrated roughly 15% increase in NFET performance in deeply scaled FinFETs. However, this is still far less than the performance gain we reported recently in ETSOI devices. In this work, for the first time we report NFET performance gain in SSDOI FinFETs fabricated with contacted gate pitch (CGP) down to 64nm.
- Published
- 2013
8. Extremely thin SOI for system-on-chip applications
- Author
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Raghavasimhan Sreenivasan, J. Kuss, Ali Khakifirooz, Y. Le Tiec, Shom Ponoth, Nicolas Loubet, Bruce B. Doris, Zhibin Ren, Scott Luning, Kangguo Cheng, J. Gimbert, L. Grenouillet, Romain Wacquez, M. Vinet, Pranita Kulkarni, Qing Liu, Davood Shahrjerdi, T. Nagumo, J. Cai, and Alexander Reznicek
- Subjects
CMOS ,business.industry ,Computer science ,Electrical engineering ,Electronic engineering ,Silicon on insulator ,Embedded memory ,Node (circuits) ,System on a chip ,Static random-access memory ,business ,Cmos scaling ,Communication channel - Abstract
We review the basics of the extremely thin SOI (ETSOI) technology and how it addresses the main challenges of the CMOS scaling at the 20-nm technology node and beyond. The possibility of V T tuning with backbias, while keeping the channel undoped, opens up new opportunities that are unique to ETSOI. The main device characteristics with regard to low-power and high-performance logic, SRAM, analog and passive devices, and embedded memory are reviewed.
- Published
- 2012
9. Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS
- Author
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Walter Schwarzenbach, Davood Shahrjerdi, Prasanna Khare, Nicolas Loubet, Sebastian Naczas, Kangguo Cheng, Yu Zhu, Cecile Aulnette, Swati Mehta, Bruce B. Doris, T. Yamamoto, Qing Liu, Stefan Schmitz, J. Kuss, Vamsi Paruchuri, Scott Luning, Ghavam G. Shahidi, H. He, Alexander Reznicek, Pouya Hashemi, James Chingwei Li, Thomas N. Adam, Shom Ponoth, Toshiharu Nagumo, S. Holmes, Bich-Yen Nguyen, T. Levin, Ali Khakifirooz, Anita Madan, Raghavasimhan Sreenivasan, J. Gimbert, Mukesh Khare, Frederic Monsieur, Pranita Kulkarni, Nicolas Daval, and Z. Zhu
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Materials science ,Strain (chemistry) ,Silicon ,business.industry ,Silicon on insulator ,chemistry.chemical_element ,Epitaxy ,Silicon-germanium ,chemistry.chemical_compound ,chemistry ,CMOS ,Logic gate ,Electronic engineering ,Optoelectronics ,business - Abstract
High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/µm and 1.25mA/µm, and I eff of 0.95mA/µm and 0.70mA/µm at I off =100nA/µm and V DD of 1V, for NFET and PFET, respectively.
- Published
- 2012
10. Implant approaches and challenges for 20nm node and beyond ETSOI devices
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Sanjay Mehta, M. Vinet, Bruce B. Doris, Kangguo Cheng, Nicolas Posseme, Y. Le Tiec, Balasubramanian S. Pranatharthi Haran, Raghavasimhan Sreenivasan, Terence B. Hook, Mukesh Khare, Amit Kumar, Qing Liu, Nicolas Loubet, Scott Luning, V. Destefanis, S. Kanakasabapathy, Pranita Kulkarni, T. Levin, L. Grenouillet, Ali Khakifirooz, N. Berliner, Stefan Schmitz, J. Kuss, Ghavam G. Shahidi, and Shom Ponoth
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Computer science ,Two step ,Key (cryptography) ,Electronic engineering ,Silicon on insulator ,Node (circuits) ,Implant - Abstract
Two implantation based schemes were explored for ETSOI NFET devices targeted for the 20nm node. Amorphization of the thin SOI is a key issue for the implant pre RSD scheme. This can be alleviated by implanting through liner. Variability is the key issue for the implant post RSD scheme which can be alleviated by good process controls and by the use of a two step epitaxy scheme.
- Published
- 2011
11. Influences of Plasma Processed Interface Layers on Germanium MOS Devices with ALD Grown HfO2
- Author
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Yasuhiro Oshima, Paul C. McIntyre, Raghavasimhan Sreenivasan, and Takuya Sugawara
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Materials science ,Passivation ,business.industry ,Oxide ,chemistry.chemical_element ,Germanium ,law.invention ,Ion ,Capacitor ,Hysteresis ,chemistry.chemical_compound ,Stack (abstract data type) ,chemistry ,law ,Optoelectronics ,business ,Layer (electronics) - Abstract
Germanium and hafnium-dioxide (HfO2) stack structures' physical and electrical properties were studied based on the comparison of germanium and silicon based metal-oxide-semiconductor (MOS) capacitors' electrical properties. In germanium MOS capacitor with oxide/oxynitride interface layer, larger negative flat-band-voltage (Vfb) shift compared with silicon based MOS capacitors was observed. Secondary ion mass spectrum (SIMS) characteristics of HfO2-germanium stack structure with germanium oxynitride (GeON) interfacial layer showed germanium out diffusion into HfO2. These results indicate that the germanium out diffusion into HfO2 would be the origin of the germanium originated negative Vfb shift. Using Ta3N5 layer as a germanium passivation layer, reduced Vfb shift and negligible hysteresis were observed. These results suggest that the selection of passivation layer strongly influences the electrical properties of germanium based MOS devices.
- Published
- 2007
12. Effects of Nitrogen Reactive Species on Germanium Plasma Nitridation Processes
- Author
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Takuya Sugawara, Paul C. McIntyre, and Raghavasimhan Sreenivasan
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Materials science ,chemistry ,Hydrogen ,Silicon ,Inorganic chemistry ,Remote plasma ,chemistry.chemical_element ,Germanium ,Substrate (electronics) ,Nitride ,Nitrogen ,Nitriding - Abstract
Roles of reactive species of germanium and silicon plasma nitridation were investigated by comparing nitrogen plasma chemistry and oxynitride layer physical properties. In high pressure remote plasma nitridation process, hydrogen containing neutral radicals (NH* and H*) were important to nitride germanium and silicon substrates. This process required high substrate temperature to nitride germanium substrate, whereas silicon substrates could be nitrided at low substrate temperature. In low pressure RLSA plasma nitridation process, N2+ ion species acted as dominant reactive species. Using this process, germanium could be nitrided at low substrate temperature without hydrogen and high nitrogen concentration (~22at.%) GeON was obtained.
- Published
- 2006
13. Electrical properties of germanium/metal-oxide gate stacks with atomic layer deposition grown hafnium-dioxide and plasma-synthesized interface layers
- Author
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Raghavasimhan Sreenivasan, Takuya Sugawara, Yasuhiro Oshima, and Paul C. McIntyre
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Materials science ,Physics and Astronomy (miscellaneous) ,Silicon ,Analytical chemistry ,chemistry.chemical_element ,Germanium ,Dielectric ,law.invention ,Capacitor ,Atomic layer deposition ,chemistry.chemical_compound ,chemistry ,X-ray photoelectron spectroscopy ,law ,Layer (electronics) ,Hafnium dioxide - Abstract
The electrical properties of metal-oxide-semiconductor (MOS) capacitors composed of atomic-layer-deposited (ALD) hafnium-dioxide (HfO2) dielectrics and plasma-synthesized interface layers were investigated. MOS capacitor with oxynitride interface layer shows negative flatband voltage (Vfb) shift from the ideal value. Hafnium-alkylamide ALD process performed on a plasma nitrided silicon surface causes negative Vfb shift. Germanium MOS capacitors show additional negative Vfb shift (−0.5V). X-ray photoelectron spectroscopy shows evidence of germanium diffusion into the HfO2 layer. Germanium MOS capacitor with tantalum-oxynitride (TaON) interface layer shows superior electrical properties. These results indicate that the selection of the interface layer strongly influences germanium MOS capacitor electrical properties.
- Published
- 2007
14. High temperature phase transformation of tantalum nitride films deposited by plasma enhanced atomic layer deposition for gate electrode applications
- Author
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Raghavasimhan Sreenivasan, Krishna C. Saraswat, Takuya Sugawara, and Paul C. McIntyre
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Materials science ,Physics and Astronomy (miscellaneous) ,Ion plating ,Tantalum ,Analytical chemistry ,chemistry.chemical_element ,Chemical vapor deposition ,Amorphous solid ,Atomic layer deposition ,chemistry.chemical_compound ,chemistry ,Tantalum nitride ,Remote plasma ,Thin film - Abstract
Tantalum nitride thin films were deposited at 400°C by plasma enhanced atomic layer deposition using an amido-based metal organic tantalum precursor. An Ar∕N2∕H2 mixture was flowed upstream of a remote plasma system to produce the reactive species used for the nitridation process. The as-deposited film was amorphous and contained 15at.% oxygen in the bulk of the film. High resolution photoelectron spectroscopy studies of the Ta 4f feature were consistent with the presence of the semiconducting Ta3N5 phase in the as-deposited films. Electron diffraction studies were carried out by annealing the Ta3N5 film in situ in a transmission electron microscope. The high resistivity Ta3N5 phase crystallized into the cubic TaN phase at 850°C. This transformation appeared to coincide with outdiffusion of excess nitrogen from the Ta3N5 film during the anneal. The resistivity of the crystallized film was estimated to be 600μΩcm from four point probe measurements.
- Published
- 2007
15. Atomic Layer Deposition of Y[sub 2]O[sub 3]∕ZrO[sub 2] Nanolaminates
- Author
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Raghavasimhan Sreenivasan, Annamalai Karthikeyan, Shriram Ramanathan, Cynthia N. Ginestra, and Paul C. McIntyre
- Subjects
Materials science ,General Chemical Engineering ,Oxide ,Nanotechnology ,Amorphous solid ,Tetragonal crystal system ,chemistry.chemical_compound ,Atomic layer deposition ,chemistry ,Chemical engineering ,Electrical resistivity and conductivity ,Electrochemistry ,General Materials Science ,Cubic zirconia ,Crystallite ,Electrical and Electronic Engineering ,Physical and Theoretical Chemistry ,Yttria-stabilized zirconia - Abstract
We report on the growth and electrochemical properties of nanoscale (20-35 nm) yttria-zirconia alloys synthesized using a laminate approach via atomic layer deposition. We observed metal oxide layer interdiffusion in relatively long-period (∼10 nm) nanolaminates by depth profiling analysis after 950°C anneals. Short-period (< 1 nm) nanolaminates were amorphous as deposited but appeared to be completely interdiffused with a polycrystalline, tetragonal structure after similar anneals. Electrochemical characterization of annealed, short-period nanolaminate yttria-stabilized zirconia (YSZ) films containing 3 mol % Y 2 O 3 (3YSZ) indicated significant enhancement of total electrical conductivity compared to reported bulk values for this composition.
- Published
- 2007
16. Effect of impurities on the fixed charge of nanoscale HfO2 films grown by atomic layer deposition
- Author
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Paul C. McIntyre, Krishna C. Saraswat, Raghavasimhan Sreenivasan, and Hyoungsub Kim
- Subjects
Secondary ion mass spectrometry ,Atomic layer deposition ,Materials science ,Physics and Astronomy (miscellaneous) ,chemistry ,Vacuum deposition ,Impurity ,Annealing (metallurgy) ,Analytical chemistry ,chemistry.chemical_element ,Electrical measurements ,Dielectric ,Hafnium - Abstract
HfO2 films were grown by atomic layer deposition using two different precursor chemistries—HfCl4 and tetrakis(diethylamido)hafnium (TDEAH) with H2O as the oxidant. Electrical measurements on capacitor structures fabricated using the films showed a 0.4V positive shift in the flatband voltage for the chloride-HfO2 with respect to the amide-derived HfO2, indicating a considerable negative fixed charge in the dielectric. Secondary ion mass spectrometry depth profiles of the gate stack showed that Cl segregated preferentially at the HfO2∕SiO2 interface for chloride-derived HfO2. In situ vacuum anneals of the HfCl4-derived films at 500°C did not affect the profile, indicating that Cl is stably bonded at that interface. A similar analysis of the TDEAH-derived HfO2 showed very low concentrations of C, N, and H impurities. A positive fixed charge of +4.5×1011∕cm2 was extracted for the amide-HfO2 whereas a negative fixed charge of −1.86×1012∕cm2 was estimated for the chloride-HfO2. Thus, Cl incorporation can signif...
- Published
- 2006
17. Physical and electrical properties of plasma nitrided germanium oxynitride
- Author
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Takuya Sugawara, Raghavasimhan Sreenivasan, and Paul C. McIntyre
- Subjects
Suboxide ,Silicon oxynitride ,Materials science ,Hydrogen ,Inorganic chemistry ,Analytical chemistry ,chemistry.chemical_element ,Germanium ,Plasma ,Condensed Matter Physics ,chemistry.chemical_compound ,chemistry ,Electrical and Electronic Engineering ,Inductively coupled plasma ,Plasma processing ,Nitriding - Abstract
The physical and electrical properties of plasma nitrided germanium oxynitride (GeON) and silicon oxynitride (SiON) layers are studied. In this study, two kinds of plasma nitridation process were utilized to form oxynitride layers. High pressure remote inductive coupled plasma and low pressure radial line slot antenna (RLSA) plasma provide radical dominant and ion dominant plasma nitridation processes, respectively. X-ray photoelectron spectroscopy results show different properties of GeON layers based on each plasma nitridation process. The remote (radical) plasma nitridation forms water soluble nitrogen-germanium bonding, and RLSA (ion) plasma nitridation forms water resistant nitrogen-germanium bonding. Although hydrogen containing plasmas or ion dominant plasma process can incorporate high amount of nitrogen into oxynitride layers, such process is accompanied by water insoluble suboxide formation and charging damage. Using p-type metal oxide semiconductor (MOS) capacitors, basic electrical properties ...
- Published
- 2006
18. Mechanism of germanium plasma nitridation
- Author
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Paul C. McIntyre, Raghavasimhan Sreenivasan, and Takuya Sugawara
- Subjects
Materials science ,Silicon oxynitride ,Silicon ,Analytical chemistry ,chemistry.chemical_element ,Germanium ,Nitride ,Condensed Matter Physics ,chemistry.chemical_compound ,chemistry ,X-ray photoelectron spectroscopy ,Remote plasma ,Electrical and Electronic Engineering ,Inductively coupled plasma ,Plasma processing - Abstract
The mechanisms of plasma nitridation of germanium (Ge) and silicon (Si) substrates are discussed based on plasma characteristics and oxynitride film properties. Optical emission spectroscopy (OES) study and x-ray photoelectron spectroscopy were utilized to characterize the plasma and film properties, respectively. In this study, high pressure (1.8Torr) remote inductive coupled plasma and low pressure (
- Published
- 2006
19. ALD Resist Formed by Vapor-Deposited Self-Assembled Monolayers.
- Author
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Junsic Hong, David W. Porter, Raghavasimhan Sreenivasan, Paul C. McIntyre, and Stacey F. Bent
- Published
- 2007
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