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Transmission line pulse (TLP) testing is well known for device characterisation in ESD circumstances. In this paper TLP is applied to full-integrated circuits and is shown to offer valuable data for the analysis of the ESD behaviour of ICs. TLP is the only method to study ESD behaviour during ESD stressing and as such provides essential knowledge about actual ESD current paths. The paper shows that both TLP characteristics and recordings of the actual waveforms should be used for a correct analysis. As illustrated by several examples, from different design groups and from different processes, such analysis gives valuable suggestions for improving circuit designs.

A new method allowing the automatic characterization of the subthreshold hump effect (Sallagoity et al., IEEE TED vol. 43, no. 11, pp. 1900-6, 1996) is presented in this paper. It makes use of a variable transformation based on observations made with a hump model. This model considers two sub-transistors with different threshold voltages in parallel. The extracted parameters are the hump effect magnitude, the weak inversion slope and the extrapolated leakage current at V/sub g/=0 V. After implementation in our automatic test system, the routine has been successfully applied to the 0.25 /spl mu/m technology of the Crolles Centre Commun. The efficiency and reliability of this routine are demonstrated whatever the operating bias and temperature. It is noticed that this method is a useful tool to monitor and study the hump effect.

Analog applications of MOS transistors in integrated circuits impose enhanced requirements on the compact MOS models used in circuit simulators. Here we present for the Philips MOS MODEL 9 the successful confrontation with these analog requirements, the scaling of parameters with geometry, the accuracy of the model over the whole geometry range of a process, its capabilities in the description of various processes at least down to 0.35 /spl mu/m and a comparison with advanced analog models available in commercial circuit simulators. >

This paper studies the suitability of CMOS device technology for mixed-signal applications. The currently proposed scaling scenario's for CMOS technologies lead to strong degradation of analog transistor performance. As a result the combined optimization of digital and analog devices for system-on-a-chip applications will require increasingly elaborate process modifications. New device solutions such as metal gate integration and asymmetric (source-side-only) workfunction modification offer process options for future mixed-signal CMOS applications.

We have investigated the RF potential of 100nm CMOS technology. A high cut-off frequency of 140 GHz for 80nm (actual gate length) NMOS devices was achieved. Combining on wafer measurements with the compact model MOS model 11, we demonstrate that an fmax of 320GHz is achievable on scaled NMOS devices.