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A computationally efficient physics-based wideband predictive inductor compact model is presented that is capable of evaluating the impact on inductance and quality factor of dummy metal fill-cells. In a modern integrated-circuit process, high amounts of these fill-cells are required to meet metal density rules and guarantee adjacent circuit integrity. The predictions made with this model are shown to be in agreement with data measured on symmetrical octagonal inductors realized in a 90-nm CMOS process with varying amounts of dummy metal fill-cells. We further provide all inductance equations, list additional sources of eddy current losses, and discuss layout modifications, which would further improve the performance of the integrated inductors

Solid-state varactor performance is evaluated in light of fundamental tradeoffs imposed by semiconductor material. This leads to the important conclusion that the product of Q factor, frequency, tuning range, and breakdown voltage has an upper limit (between 5 and 40 THzmiddotV for silicon) that is dictated primarily by semiconductor material parameters, and to a lesser degree on doping level and temperature. This limit is then approached by experimental hyperabrupt profiles with a product of 17 THzmiddotV that were fabricated in a SiGe BiCMOS process. Two complementary analysis techniques based on LCR and high-frequency measurements are presented

A new noise-figure measurement method, which combines the simplicity of the "classical" Y-factor method with the accuracy of the widely used "cold noise-source" method, is reported. Implemented in our fully automated wide-band 1-18-GHz on-wafer noise-parameter measurement system, accurate results are obtained using a small set of precharacterized source impedances. We illustrate our method and its accuracy with data taken on a low-noise GaAs pseudomorphic high electron-mobility transistor device, and quantify the impact of the instrumental uncertainties on the extracted noise parameters.

The impedance errors remaining after applying the industry standard "open-short," a "pad-open-short," and a "open-short-load" deembedding scheme on a 0.43-nH 20-GHz high-Q single-loop inductor test structure are investigated using real S-parameter data taken up to 50 GHz. Since the latter two deembedding schemes both correct for all parasitic elements of the test structures, they are, at least in principle, error free. The accuracy of the "open-short-load" deembedding scheme, however, critically depends on how well the reactive part of the load resistance is accounted for. This issue makes the more simple "pad-open-short" deembedding scheme an attractive choice because the required split between external and internal capacitances is easy to make, either based on process and layout information or from measurements done on a "pad" dummy structure

This paper presents a new method, developed for the capacitance–voltage (C–V) characterization of leaky dielectrics. The method comprises measurements in the gigahertz range on specially designed RF test structures. The method is verified against high-frequency C–V measurements on NMOS and PMOS structures. It yields reliable results even when the gate leakage is in excess of 100 A/cm2.

The impedance errors remaining after conventional de-embedding for a high-speed transistor and a single-loop inductor test structure are investigated. A new de-embedding strategy using a physics-based lumped-element model for the test-structure parasitics calibrated on the frequency-dependent "open" and "short" dummy impedances is described, which reduces the experimental uncertainty on the de-embedded figures of merit. Using this new "calibrated lumped-element" de-embedding technique, we have been able to increase the "worst-case" values for the quality factor Q of a 0.6-nH 10-GHz single-loop inductor from 15 to 20 and for the f/sub max/ of a high-speed SiGe bipolar transistor from 80 to 110 GHz. The de-embedding technique presented here is of great importance to develop confidence in on-wafer S-parameter measurements taken at ever increasing microwave frequencies.

The RF noise in 0.18-/spl mu/m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1/f noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.

The collector epilayer is a crucial element in the behavior of modern bipolar transistors. Compact models for its description, like the Kull model, are therefore of crucial importance too. We give a Mextram-based improvement to these models for quasi-saturation and show that the output conductance and the cutoff frequency are less abrupt in this region. Apart from ohmic quasi-saturation, we also include quasi-saturation due to the Kirk effect, which results from velocity saturation.

The performance of inductors realized in various metal layer combinations available in an advanced CMOS process with a mixed copper-aluminum backend is compared. Due to the skin effect, the gain in performance is generally smaller than anticipated from the reduction in dc resistance. We show that beyond a certain frequency, adding an aluminum layer on top of a copper inductor stack actually degrades the inductor performance because the skin resistance of the top metal is enhanced.

We present a MOS Capacitance-Voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm/sup 2/. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion.

We report a single-loop inductor suitable for integration in a differential voltage-controlled oscillator (LC-VCO) with 0.6-nH inductance and record quality factors of 18 at 10 GHz and 20 at 15 GHz fabricated in an industrial CMOS process on a 10 /spl Omega/cm substrate. A new lumped element model which accurately describes the inductor performance without the need for frequency-dependent elements is presented. During the course of this work, we found that a patterned ground shield significantly improves the inductor performance at these frequencies, but only when the polysilicon bars are connected from the center of the inductor.

RF MEMS capacitive switches can be used for band switching and adaptive antenna matching in cell phone Front End Modules. They are extremely linear and, if made in standard silicon technology, can be integrated into other applications in the phone. Many efforts have been put in the intrinsic reliability of the RF MEMS capacitive switches. The main failure mechanism is stiction due to dielectric charging. The progress made in RF MEMS processing has shifted the focus towards the package. It is generally accepted that a hermetic package is needed to keep the effect of charging within specification. Since packages are very small (typically 300nl), new hermeticity tests are needed because the leak rate tests are not sensitive enough for these small packages. In this paper we demonstrate the reliability of a capacitive RF MEMS switch package. The product is assembled using a AuSn bonding process in which a Silicon cap wafer is assembled on top of the MEMS die. The package is filled with pure N2 to the desired pressure. Hermeticity is determined by measuring the pressure dependence of the mechanical resonance of the MEMS top electrode. First we will describe the method we have used to determine the pressure inside the cavity and how to apply that to hermeticity testing. Second, we describe how the requirements for the leak rate of the package can be determined. Finally we show with the use of temperature, humidity and high pressure N2 testing that our package fulfills these requirements. Although the method may not be new, the combination of extensive reliability testing and understanding the RF MEMS device using FEM simulations has not been reported before.

Passive integration technologies gain more and more interest for cellular applications due to the increasing demand for integration of functionality for cost, performance and size reasons[1-4]. One of the examples is the 6" PASSI4 process of NXP semiconductors[2]. This process consists of high ohmic Si substrates with high quality RF components such as metal-insulator-metal (MIM) capacitors and thick metal inductors. The process also includes a thick backside metal and through wafer interconnect (TWI) via holes for low inductive grounding. In addition, a high density decoupling capacitor and a resistor are available. The process results in an RF component (a sub-module) which is utilized in a stacked power amplifier (PA)/front end module (FEM) which also includes active control and RF power technologies[4]. One of the main difficulties with such a passive technology is the characterization and process control. In an active process, the performance of the circuits or sub circuits during pre-testing is closely related to the end product performance. However, the relation between the performance of the sub-modules and the performance of the final module is not straightforward at all. In this paper we will show how we have solved this issue for the process release of PASSI4.

We have optimized 3 key RF devices realized in standard logic 90 nm CMOS technology and report a record performance in terms of n-MOS maximum oscillation frequency f/sub max/ (280 GHz), varactor tuning range and varactor and inductor quality factor.

Using a semi-insulating channel stopper (SICS) layer, silicon substrate RF losses have been eliminated on high resistive silicon wafers (HRS) up to 100 GHz, even after thermal treatments up to 1100/spl deg/C. The integration of the SICS layer is demonstrated at the bottom of shallow trench isolation (STI) in a state-of-the-art CMOS technology. These results open a way to easily integrate low-cost high quality passive devices into standard high volume Si technologies.

We present two complementary, analytical calculations of the electric field, stored charge, capacitance and transit time of the collector of a III-V HBT, for respectively low- and high bias regimes. Voltage, current and temperature dependence of base-collector capacitance as well as f/sub T/-peaking at high bias is thus quantitatively related to GaAs-like electron drift-velocity characteristics. The physical insight developed serves as a basis for extension of the Mextram compact bipolar transistor model for circuit simulation.

A 2 times 2 /spl mu/m, dual damascene, dual metal Cu in SiLK/spl trade/ process on 200 mm high-resistivity silicon wafers is presented. The lines and spaces in both metal layers can be patterned to submicron dimensions. The extremely low specific contact resistance of the vias, typical for dual damascene Cu, is utilized to make coplanar waveguides, patterned specifically to suppress skin and proximity effects. RF measurements from 1 to 100 GHz show an increase in Q factor up to 30% in the 1 to 15 GHz frequency interval for the patterned lines.

An industrial SiGe BiCMOS technology is presented, in which the silicon substrate has been removed and replaced by a lossless glass substrate. This will enable the integration of better passives, while the active devices remain fully library compatible. Specifically, ideal NPN characteristics with 111/94 GHz f/sub T//f/sub max/ are shown without significant degradation of the thermal characteristics. This substrate transfer technology requires almost no changes to the standard processing and gives access to high-performance inverse NPN and vertical PNP devices, in addition to the lossless substrate.

The performance of 2 /spl mu/m thick damascene Cu lines embedded in low K material are evaluated. The process is well control over a 200 mm wafer, provided that tiling is used. A minimum linewidth of 560 nm is achieved. The RF performance of substrate and metal lines in the 1 - 100 GHz frequency range is investigated with coplanar waveguides. Various substrates were used with resistivities ranging from 3-5 /spl Omega/-cm to 4-5k/spl Omega/-cm. With a properly treated substrate, RF losses are only determined by AC series resistance of the metal lines yielding very low losses of 1.7 dB/cm at 10 GHz.

A highly accurate predictive inductor model for integrated symmetric inductors with center tap and patterned ground shield is presented. This model is based on a modified Greenhouse algorithm where current crowding due to skin and proximity effects is included by considering the spread in parallel sub-loop inductances. This scalable symmetrical inductor equivalent circuit model covers all operating conditions, and yet only requires dimensions and back-end layer thicknesses. We have verified this scalable model for a large number of inductors from three industrial IC processes and found excellent agreement with measured inductances, Q-factors, and resonance frequencies.

In this paper, the effect of process-related design rules on inductor performance are shown. In advanced processes the copper line width is limited, and the metal pattern density must be as uniform as possible. The results obtained on inductors fabricated in-one metal layer with a different number of parallel tracks, with and without copper tiles are presented. The geometry and the orientation of the tiles are also varied. The comparison allows us to quantify the influence of copper tiles on the inductor quality factor.

Accurate compact modeling of induced gate noise is a prerequisite for RF CMOS circuit design. Existing models underestimate the induced gate noise for short-channel devices. In this paper, a new model is introduced, based on an improved Klaassen-Prins approach, which accurately accounts for velocity saturation. The model accurately describes noise without fitting any additional parameters.

We demonstrate that the quality factors measured on on-wafer (spiral) inductor test-structures are largely influenced by the choice between ground-signal and ground-signal-ground probe configuration. In particular when the SOLT network analyzer calibration technique is used in combination with ground-signal probing, the quality factor value can be overestimated significantly.

We study the the thermal noise of short-channel NMOS transistors in a commercially available 0.13 micron CMOS technology. The experimental results are modeled with a non-quasi-static RF model, based on the principle of channel segmentation. The model is capable of predicting both drain and gate current noise accurately, without fitting any parmeters to the measured noise data. An essential ingredient of the model is the gate resistance, which is shown to dominate the gate current noise. In our optimized device layouts, this gate resistance is mainly determined by the silicide-to-polysilicon contact resistance.

We present an MOS capacitance-voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm/sup 2/. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion.

We present a physically based, analytical model of the electric field, charge and capacitance in the collector of a III-V HBT. The model consistently takes into account the decrease of electron drift velocity versus electric field at high fields. We achieve excellent prediction of collector-base capacitance as a function of collector-base voltage and current in the regime of partial depletion of the collector, while the only fitting needed is determination of mobility parameters from drift-velocity data.

Double-polysilicon bipolar junction transistors with an ultra shallow implanted base are fabricated using Ge pre-amorphization. The effect of implanted C, both on suppressing transient enhanced diffusion and on the junction leakage, is studied.

High-Q spiral inductors, either realized as discrete elements in thin-film technologies, or as integrated components in IC processes, are essential to realize key RF circuitry like VCO's and LNA's. We have demonstrated for the first time that by dividing a spiral inductor into four parallel current paths of equal resistance and inductance current crowding can be suppressed, allowing a record Q of 15 for a 2 GHz 5 nH inductor in standard CMOS, representing a 40 % improvement over previous art. The proposed division into parallel current paths can be realized without process modifications, reduces CMP dishing, and is expected to provide even larger performance gains in terms of quality factor Q and inductor area for IC and thin-film processes employing thicker metal layers and low-K materials.

We present compact model formulations for the description of two effects seen in SiGe HBT's, but not in pure-Si transistors. One of them is the influence on the Early effect of a graded Ge-content in the base. The other is the neutral base recombination due to the high base doping levels in some SiGe transistors. Both formulations have been implemented as options in a publicly available compact model.

The distortion behaviour of MOSFETs is important for RF-applications. In this paper the influence of technology variations (oxide thickness, substrate doping,...) on distortion is investigated using measurements and a recently developed compact MOSFET model. The influence on distortion of technology scaling down to 0.18 /spl mu/m is verified and further scaling according to the ITRS-roadmap is predicted.

In this paper, a new comprehensive bipolar transistor avalanche multiplication model is presented that takes into account the finite thickness of the epilayer, modulation of the electric field by the collector current (Kirk effect), current spreading in the epilayer and quasi-saturation. Two parameters are needed to model the collector voltage dependency at small current levels and one parameter is required to describe high current effects. The dependency of the collector-emitter breakdown voltage BV/sub ceo/ with collector current is shown. The model will be part of the bipolar compact transistor model Mextram 504, but also can be used separately.

The collector epilayer is a crucial element in the behaviour of modern bipolar transistors. Compact models for its description, like the Kull model, are also therefore of crucial importance. We give a Mextram-based improvement to these models for quasi-saturation, and show that the output conductance and the cut-off frequency are much smoother. Apart from ohmic quasi-saturation, we also include velocity saturation, which also leads to quasi-saturation (Kirk effect).

An off-state S-parameter technique characterizes the NPN substrate resistance-capacitance network. The results are useful in designing RF test structures, modeling substrate effects for circuit simulation, and characterizing perimeter and area capacitance components from a single device.

We have investigated the RF potential of 100nm CMOS technology. A high cut-off frequency of 140 GHz for 80nm (actual gate length) NMOS devices was achieved. Combining on wafer measurements with the compact model MOS model 11, we demonstrate that an fmax of 320GHz is achievable on scaled NMOS devices.

We demonstrate that by careful layout optimisation, particularly aimed at reducing the effective gate resistance, a record high maximum oscillation frequency fmax of 150 GHz can be obtained for an industrial 0.18 μm CMOS process showing a cut-off frequency fT of 70 GHz. A very low minimum noise figure and good suppression of the substrate noise using a guard-ring is also shown.

Modem CMOS technologies are becoming increasingly attractive for RF applications.This imposes stringent requirements on compact models used in circuit simulation: not only currents and charges, but also noise, power gain, impedances, and harmonic distortion must be modelled accurately. In this paper several of these issues will be addressed with the help of Philips’ new public-domain compact MOS model, MOS Model 11.

The thermal noise of short-channel NMOS transistors in a commercially available 0.13 -mm CMOS technology is studied. The experimental results are modelled with a non-quasi- static RF model, based on the principle of channel segmentation. The model is capable of predicting both drain and gate current noise accurately, without fitting any parameters to the measured noise data. An essential ingredient of the model is the gate resistance, which is shown to dominate the gate current noise. In the optimised device layouts, this gate resistance is mainly determined by the silicide-to-polysilicon contact resistance. The ever-continuing downscaling of CMOS technologies has resulted in a strong improvement in the RF perfor- mance of MOS devices (1-3). Consequently, CMOS has become a viable option for analogue RF applications and RF system-on-chip. For the application of modern CMOS technologies in low-noise RF circuits, accurate modelling of noise is a prerequisite. In MOSFETs, there are two intrinsic sources of noise: 1/f noise and thermal noise, the latter being the topic of this paper. Thermal noise is due to the random thermal motion of charge carriers. It not only manifests itself in the drain current noise spectrum, but, due to the capacitive coupling between channel and gate, also in the gate current noise spectrum. The latter effect is known as 'induced gate noise'. In addition to the intrinsic MOSFET thermal noise, the parasitic resistances (gate resistance, bulk resistance, and source/drain resistances) also exhibit thermal noise. Thermal noise of deep-submicron MOSFETs has received considerable attention lately, triggered by publica- tions reporting a strong enhancement of thermal noise with respect to long-channel theory (4-8). In the earliest of these publications (4), thermal noise was found to be enhanced by a factor upto 12 in n-channel devices with gate length 0.7mm, and hot electrons were proposed to explain these results. More recently, Klein (5, 6) reported very similar enhancement of drain current thermal noise in devices with gate length 0.65mm and proposed a model that invokes heating of the charge carriers in the inversion channel to explain the experiments. For the induced gate noise, an even more dramatic enhancement factor as large as 30 was found by Knoblinger (7) for a 0.25 -mm gate length n-channel MOSFET. Evidently, these reported noise enhancements would seriously limit the viability of RF CMOS, and a detailed study is called for. In previous work (9-11), in sharpcontrast to the above- mentioned authors, only moderate enhancement of the MOSFET drain current thermal noise was found, mainly caused by parasitic resistances and channel length modula- tion. This was found for 0.35 -mm, 0.25 -mm, and 0.18 -mm CMOS technologies. MOSFET gate current thermal noise, on the other hand, was found to be enhanced more severely. This enhancement could be traced back to the effects of gate resistance, and the silicide-to-polysilicon contact resistance in particular. Although the thermal noise, as found in CMOS fabrication down to 0.18mm, seems fairly well understood, it remains important to study the phenomenon for more advanced CMOS technologies: it seems probable that at some point down the ITRS roadmap, the main assumption of our theory, i.e. thermal equilibrium, will break down. Therefore, in this work (which was reported earlier in (12)), we extend our study of MOSFET thermal noise to 0.13 -mm technology. We present a large number of new experimental results in the 1-18 GHz frequency range, and compare them with the predictions of our previously developed RF MOSFET model.

Extensive measurements of drain current thermal noise are presented for 3 different CMOS technologies and for gate lengths ranging from 2 /spl mu/m down to 0.17 /spl mu/m. Using a surface-potential-based compact MOS model with improved descriptions of carrier mobility and velocity saturation, all the experimental results can be described accurately without invoking carrier heating effects or introducing additional parameters.

A model for RF CMOS circuit design is presented that is capable of predicting drain and gate current noise without adjusting any parameters. Additionally, the presence of (i) noise associated with avalanche multiplication, and (ii) shot noise of the direct-tunneling gate current in leaky dielectrics is revealed.