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Summary The movement of chloride ion and the movement and degradation of fluometuron in two soils of contrasting texture and structure was predicted with a simulation model which included terms for the degradation of fluometuron as a function of temperature and moisture. The simulated distributions of soil water, chloride ion and fluometuron were compared with the observations reported in a previous paper (Hance, Embling, Hill, Graham-Boyce & Nicholls, 1981), Soil waler contents and fluometuron distribution were simulated reasonably accurately. Movement of chloride to below 30 cm in both soils and degradation of fluometuron in the WRO sandy loam soil were not well simulated. The discrepancies between observed and predicted water contents and chloride distribution show the importance of measuring dynamic as well as static water properties. Therefore refined simulation models may need to account for pore continuity, soil particle movement and mobile and immobile categories of water. Resume Mouvement du fluometuron et du 36Cl− dans le sol dans des conditions se plein champ: modele telematique Le mouvement de l'ion chlore et le mouvement ainsi que la degradation du fluometuron dans deux sols de texture et de structure differentes ont eteetudies par modele mathematique incluant la degradation du fluometuron en fonction de la temperature et de l'humidite. Les distributions simulees de l'eau du sol, de l'ion chlore et du fluometuron ont ete comparees aux observations consignees dans un precedent article (Hance, Embling, Hill, Graham-Bryce et Nicholls, 1981). La teneur en eau du sol et la distribution du fluometuron ont ete estimees de facon assez precise. Le mouvement du chlore en-dessous de 30 cm dans les deux sols, ainsi que la degradation du fluometuron dans un sol limono-argileux sur la station de la W.R.O. n'etaient pas conformes aux estimations. Les differences entre la teneur en eau du sol et la distribution du chlore observees et simulees montrent l'importance d'une mesure dynamique mais aussi statique des proprietes de l'eau du sol. Donc, des modeles mathematiques plus precis peuvent necessiter la prise en compte de l'homogeneite des pores, du mouvement des particules de sol ainsi que des differentes categories d'eau mobile et immobile. Zusammenfassung Transport von Fluometuron und 36Cl− im Boden unter Feldbedingungen: Computer-Simulationen Der Transport von Chlorid als auch der Transport und der Abbau von Fluometuron in zwei in ihrer Textur und Struktur sehr verschiedenen Boden, wurde mit einem Simulationsmodell vorhergesagt. Die Kennwerte fur den Fluometuronabbau waren eine Fuktion der Temperatur und der Feuchtigkeit. Die simulierte Verteilung von Bodenwasser, von Chlorid und von Fluometuron wurde mit den in einer fruheren Arbeit gefundenen Ergebnissen verglichen (Hance. Embling, Hill. Graham-Bryce & Nicholls, 1981). Der Bodenwassergehalt und die Verteilung von Fluo-meturon Hessen sich mit ausreichender Genauig-keit simulieren. In beiden Boden liess sich der Transport von Chlorid uber eine Tiefe von 30 cm hinaus nicht befriedigend simulieren und das gieiche gait fur die Simulation des Fluometur-onabbaus im sandigen Lehmboden der WRO, Die Unterschiede zwischen den beobachteten und den vorhergesagten Wassergehalten und Chlorid-verteilung zeigen. wie wichtig es ist. die Eigens-chaften des dynamischen als auch des statischen Wassers zu messen. In verbesserten Simulations-modeilen mussen deshalb die Porenkontinuitat, der Transport von Bodenpartikein und des mobilen und immobilen Wassers starker beruck-sichtigt werden.

A sensing technique using a voltage-mode architecture, noise-shaping modulator, and digital filter (a counter) is presented for use with cross-point MRAM arrays and magnetic tunnel junction memory cells. The presented technique eliminates the need for precision components, the use of calibrations, and reduces the effects of power supply noise. To obviate the effects of cell-to-cell variations in the array, a digital self-referencing scheme using the counter is presented. Measured experimental results in a 180-nm CMOS process indicate an RMS sensing noise of 20 /spl mu/V for a 5-/spl mu/s sense time. Further increases in sense time are shown to increase the signal-to-noise ratio. The current used by the sense amplifier and counter was measured as 10 /spl mu/A when running at 100 MHz or 10 mA when 1000 sense amplifiers are used with a memory subarray having 1000 bitlines.

A reliable configuration for triggering a series string of power metal oxide semiconductor (MOS) devices without the use of transformer coupling is presented. A capacitor is inserted between the gate and ground of each metal oxide semiconductor field effect transistor (MOSFET), except for the bottom MOSFET in the stack. Using a single input voltage signal to trigger the bottom MOSFET, a voltage division across the network of device capacitance and inserted capacitances triggers the entire series stack reliably. Design formulas are presented and simple circuit protection is discussed. Simulation shows reliable operation and experimental verification is presented, Application of the method is applied to series insulated gate bipolar transistors (IGBTs).

This paper describes a register-controlled symmetrical delay-locked loop (RSDLL) for use in a high-frequency double-data-rate DRAM. The RSDLL inserts an optimum delay between the clock input buffer and the clock output buffer, making the DRAM output data change simultaneously with the rising or falling edges of the input clock. This RSDLL is shown to be insensitive to variations in temperature, power-supply voltage, and process after being fabricated in 0.21 /spl mu/m CMOS technology. The measured r.m.s. jitter is below 50 ps when the operating frequency is in the range of 125-250 MHz.

The piezospectroscopy of Sb in Ge, with a compressive force F ‖ 〈1 1 1〉, has been reinvestigated using state-of-the-art instrumentation. In the high stress limit, where the splitting of the donor states is an order of magnitude larger than the valley-orbit (chemical) splitting of the ground state, the results are remarkable, yielding for E ‖ F , a series of nine very sharp stress-induced components, five of which belong to the np 0 (1) series. It is not clear if the other four also belong to this series. For E ⊥ , seven components, mainly of the np ± (1) and nf ± (1) series, are observed.

An analog layout assistant (ALAS!) is presented that automatically generates common-centroid, interdigitated device pairs and passive components. The user inputs a minimum of input parameters and has the ability to interactively alter the parameters of the program. The program can be used in conjunction with any layout editor that imports CalTech Intermediate Format (CIF) layouts and is platform and technology independent.

A brief review is given of the Zeeman and piezo-Zeeman results for the spectra of shallow acceptors in germanium. Also included are new data for the Zeeman spectra of thallium with B ∥〈100〉 and boron, gallium and thallium under B ∥〈111〉. The observations are for field strengths up to 7T and the results compared with recent calculations of these effects. New data for neutral zinc in germanium with B ∥〈100〉 is also indicated.

The design of four resistive memory sensing circuit topologies employing delta-sigma (DeltaSigma) modulation are presented. Operation of the designs and a comparison between simulations and experimentation is given. The designs were fabricated in a 500 nm CMOS process. Measured results indicate that the resistive values ranging from a chosen reference resistance to several hundred kOmega can be sensed reliably.

A silicon bipolar transistor operating in the avalanche region was optically triggered into secondary breakdown. This transistor has been given the name fiber-optically triggered avalanche transistor (FOTAT). The FOTAT acts as an optical power discriminator. That is, secondary breakdown occurs when the triggering optical power exceeds the triggering threshold of the FOTAT. This secondary breakdown is seen as a negative resistance between the collector and emitter. High voltage (>100 V) nanosecond transition duration pulses are generated using this negative resistance. >

A unified presentation, a synthesis, and an evaluation of the methods employed in the estimation of heritability in plants are presented. Asexual, cross‐fertilizing, and self‐fertilizing diploid species, as well as annual and perennial ones, are considered. All broad‐ and narrow‐sense heritabilities are defined on individual and family bases for prediction of response to selection for a target population of environments in space and time. Narrow‐sense heritabilities are defined in cross‐fertilizing species for expected response to variations of mass, half‐sib, and full‐sib family selection for the next generation and the long term, and similarly in self‐fertilizing species. The use of both collateral and lineal relatives to estimate heritability is discussed, and the biases present in the estimators are given. Many departures and variations of the common procedures are discussed. The standard errors of heritability estimators and confidence intervals are presented.

Theoretical and experimental results are presented for op-amp compensation using split-length transistors. By using split-length devices the right-half plane zero which plagues op-amp performance can be eliminated. Experimental results indicate substantial enhancements in speed while reducing power consumption and layout area. Further, these techniques can be used to compensate op-amps when using small supply voltage (VDD).

A new approach to developing, fabricating, and testing chalcogenide-based multi-state phase-change nonvolatile memory (NVM) is presented. A test chip is fabricated through the MOSIS service. Then post processing, in the Boise State University lab, is performed on the chip to add the chalcogenide material that forms the NVM. Each memory bit consists of an NMOS access transistor and the chalcogenide material placed between the metal3 of the test chip, connected to the access device, and a common, to all memory bits, electrode. This paper describes the design of the memory bit and of the test structures used for reliability and radiation testing. Fabrication and post-processing of the memory are also discussed.

This paper presents the design of a fully differential sigma-delta temperature sensor using Schottky diode-based current references as a replacement for the traditional PN junction diode-based current references. This sensor was designed using the AMI 0.5um process through the MOSIS fabrication organization, and the chip performance will be evaluated and compared to the simulated results. The use of the Schottky diode and differential current sensing in the sigma-delta-type sensor allows for lower voltage operation and better noise performance.

This paper illustrates design, fabrication and testing of novel differential high-speed digital input buffers. The delay of the proposed input buffers are nearly independent of power supply voltage and input signal amplitudes. The pulse shape of the output signal is highly symmetric which mitigates skew related errors.

This paper presents the design of CMOS op-amps using indirect feedback compensation technique. The indirect feedback compensation results in much faster and low power op-amps, significant reduction in the layout size and better power supply noise rejection.

The voltage-time domain (VT) characteristics of the CMOS NOR logic circuit are investigated using a switch matrix technique (SMT). VT performance is analyzed following gate oxide wearout in a pMOSFET, induced by applying a constant voltage stress (CVS) at -4.0 V. Results for the NOR VT characteristics show approximately 30% increase in rise time a considerable digression from nominal operation.

CMOS NAND gate circuit performance degradation caused by a single pMOSFET wearout induced by constant voltage stress in 2.0 nm gate dielectrics is examined using a switch matrix technique. The NAND gate rise time is found to increase by approximately 64%, which may lead to timing errors in high frequency digital circuits. The degraded pMOSFET reveals that a decrease in drive current by 41% and an increase in threshold voltage by 18% are directly proportional to an increase in channel resistance, thereby substantially increasing the NAND gate circuit timing delay.

A LAyout system for individuals (LASI) that runs on the PC platform is presented, LASI is a general use layout, DRC, and extraction program that accepts and generates layouts in both CIF and GDS formats. The contents and operation of LASI are discussed.

Degradation in CMOS inverter circuit performance as a result of gate oxide wearout in 2.0 nm pMOSFETs was investigated using a constant voltage stress (CVS) technique. It is demonstrated that inverter performance in the time-domain shows significant deterioration when only the pMOSFET experiences wearout. Experimental results indicate loss of inverter circuit performance in the time-domain given by approximately 36% to 62% increase in the rise time. Conversely, DC inverter characteristics are potentially misleading showing that inverter performance was only partially altered. In both cases, inverter degradation is related to the pMOSFET suffering as much as a 40% decrease in drive current after wearout. This and other large changes in device parameters are compared to a typical logic process revealing that the device parameters are outside the process window. Ultimately, this study suggests that wearout in ultra-thin gate oxides may lead to increased circuit degradation despite the gate leakage current associated with a known circuit component being lower than that required for a typical or traditional BD event to occur.

A system for developing microwave induced hyperthermia in small animals is described, for the purpose of assessing the effects of heat alone and heat plus ionizing radiation on normal tissue and tumors. The temperature is monitored using thermistors, and with the use of a scanner, recorded on a single channel recorder. The thermometry technique is still under review. Thermographic studies on a sacrificed animal and thermistor measurements in a phantom reveal a pattern of deep heating in a well defined region. Preliminary biological measurements are presented, but currently long term animal survival remains a problem.

As semiconductor device geometries continue to shrink, the corresponding voltage applied across the processed devices must also be reduced. Therefore reference voltages used in integrated circuits will need to be reduced as well. A typical bandgap reference (BGR) voltage generator uses PN junction diodes or PNP BJT's to bias the reference. The forward bias voltage of these devices is typically 0.7 volts, and has a limiting effect on how low a reference voltage can be generated, as well as how low a system voltage can be applied. Schottky, or metal-semiconductor (MS), diodes have a lower forward bias voltage, typically of about 0.3 volts. The implementation of Schottky metal-semiconductor diodes in place of PN diodes in the design of the BGR, should allow for lower reference voltage generation. This project consists of the design and simulation of a BGR utilizing MS diodes, followed by fabrication and validation of the design

Circuit-level oxide degradation effects on CMOS inverter circuit operation and individual MOSFET behavior is investigated. Individual PMOSFET and NMOSFET devices are assembled off-wafer in the inverter configuration through a switch matrix. A range of gate oxide degradation mechanisms are induced by applying a ramped voltage stress (RVS) of various magnitudes to the input of the inverter. A novel circuit model is used to simulate the voltage transfer curves (VTCs) of degraded inverters. At the transistor level, increased gate leakage currents of nearly eight orders of magnitude are observed, in addition to severely reduced on-currents (> 50 percent reduction), and large threshold voltage (V/sub th/) shifts (> 100 mV). At the circuit-level, stress of either polarity results in inverter performance degradation. For the DC characteristics, oxide degradation attributed to limited hard breakdown (LHBD) in the NMOSFET and hard breakdown (HBD) in the PMOSFET, results in decreased output voltage swing (> 260 mV). Under the same conditions, inverter degradation in the voltage-time (V-t) domain exposes much larger changes in performance. For instance, significant increase in the rise time results in the output voltage being pulled up to only 660 MV (V/sub DD/ = 1.8 V) before switching low. From a circuit reliability viewpoint, it may be possible for subsequent circuit stages to compensate for a few degraded devices, but in highspeed circuits, increased rise/fall and delay times may cause timing issues. Furthermore, increased gate or off-state leakage currents can potentially load previous circuit stages or result in increased power consumption.

The effects of circuit level-stress on both inverter operation and MOSFET characteristics have been investigated. Individual MOSFETs, with gate oxide thicknesses of 3.2 nm and active dimensions of 25/spl mu/m /spl times/ 25/spl mu/m, are connected in an inverter configuration off-wafer via low-leakage switch matrix. Inverters are stressed with a ramped voltage stress (RVS) of various magnitudes to induce different degrees of gate oxide degradation. In addition voltage transfer curves (VTCs) of degraded inverters are simulated using a new circuit model. AT the transistor level, both the PMOSFET and NMOSFET show increase gate leakage current up to eight orders of magnitude, severely reduced on-currents and transconductance (g/sub m/), and large threshold voltage (V/sub t/) shifts of 100 mV or more. Different trends in inverter performance are observed following positive and negative stress. However, regardless of stress polarity, circuit-level stress results in inverter performance degradation, such as reduced output swing, switching point shifts, and increased rise/fall times. After the largest positive RVS, the output voltage swing has decreased from 1.8 V fresh, to 1.54 V post-stress. Much larger changes in the inverter voltage (V-t) time domain performance are observed. The minimum output low voltage is similar to that of the VTC, but the rise time increase significantly enough that the output voltage is only pull up to 660 mV (V/sub DD/=1.8V) before it switches low. In terms of circuit reliability, it maybe possible for subsequent circuit stages to compensate for a few degraded devices, but increase rise/fall and delay times may cause timing issues in high-speed circuits. Furthermore, increased gate or off-state leakage currents can potentially load previous circuit stages or result in increase power consumption.

This paper discusses educating electrical engineering students so they can do mixed-signal design (MSD). It also discusses why MSD is important and how it fits into a contemporary electrical engineering curriculum. The paper concludes with a practical example of MSD (the design of a memory sensing circuit) that shows the benefits over traditional analog techniques.

The effects of noise on gate oxide reliability were examined in nMOSCAPs. Noise is modeled as a voltage spike constructively interfering with a carrier signal. This data correlates to the noise model where device lifetime exponentially decreases with an increase in noise voltage. Noise voltages with the same magnitude as the carrier signal voltage decrease the lifetime by as much as three orders of magnitude. For noise that is one-fifth of the magnitude of the carrier signal voltage, an order of magnitude is observed. As interconnect spacing decreases, the probability of noise and capacitive coupling increases; therefore, the effect of noise on the lifetime of MOS devices may be of great concern.

The beta multiplier voltage reference (BMVR) is discussed as a direct replacement for the bandgap voltage reference in a CMOS process especially when substrate current is a concern. Performance of the BMVR with regard to temperature and process variations is covered. Experimental results from a 2-micron MOSIS test chip indicate that the BMVR can be tuned to within 10 mV of a desired value while maintaining a temperature coefficient below 1000 ppm/C and a supply sensitivity under 50 mV/V.

This paper addresses several concerns for increasing the frequency range in a Schottky diode detector circuit through a layout design solution. To increase the frequency and active range of the diode, reducing the series resistance was the first concern addressed, and this was accomplished by interdigitating the fingers of the Schottky and ohmic contacts. The capacitor was laid out in a manner to decrease charge lost to the substrate through parasitic substrate capacitance. For added accuracy, an averaging resistor/capacitor was added to isolate the Schottky diode detector circuit from the measuring circuit. With these improvements in the layout design, it is expected that the frequency and dynamic range of the Schottky diodes in the detector circuit will be extended further into the GHz range.

Examination of allozymic variation in a chromosomally highly polymorphic population of Oryzomys documented that the sample consisted of two species, one that was chromosomally monomorphic and the other containing nine centric fusion polymorphisms. The existence of allozymic variation indicates that it is highly improbable that the polymorphic sample was the result of hybridization. These centric fusion polymorphisms appeared to cause little or no negative selection.

For the original article see ibid., vol. 31, no. 2, p. 271-4 (1996). In the aforementioned paper the authors consider the advantages of laying out matched pairs of transistors, resistors, capacitors, etc., with interdigitated geometries and common centroid. Then they show six examples of "matched devices". However, the commenters point out that not one has a common centroid. This leads to the conclusion that the computer program ALAS! seems to have a remarkable consistency in making layouts where the centroids are never in common. In reply, the authors thanks R.A. Pease for his comments on their paper and respond to his concerns, especially clarifying the issues regarding common-centroid versus interdigitated layout.

A novel monolithic VCO using a transconductance architecture and with adjustable operating and centre frequencies is presented. Oscillating frequencies from 50 MHz were attained with external capacitors. Power dissipation from a 5 V supply was 150 mW driving a 20 pF load. The die size was 400/spl times/1500 /spl mu/m/sup 2/ and was fabricated using a 2 /spl mu/m n-well double-metal CMOS process.

Power MOSFETs in series are used for generating high voltage, >1 kV, pulses with nanosecond rise and fall times. The design procedures for series operation and driving power MOSFETs to attain nanosecond switching times are given. A -1500 V pulse generator is designed with a 3 ns falltime and a 15 ns risetime into a 50 Omega load. >

Power MOSFETs operated in a Marx bank circuit configuration are presented. This circuit is useful for generating high voltage (greater than 1 kV) nanosecond risetime pulses. After the design procedure is given an example circuit is designed which generates a -1800 V pulse with a 3-0 ns falltime into 50 Ω