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Position sensitive detectors (PSDs), used in high-end biotechnology, are based on optical sensors built over quadrant photodetectors (QPDs) or active pixel sensor (APS). These devices are intended to measure slight movements of laser spots. The QPD are, by far, the best approach in terms of resolution and noise, but requires complex and expensive x - y micropositioners to perform sensor alignment with the incoming laser spot. The APSs are more versatile devices that can virtually align with the spot by means of device configuration. However, due to its intrisic digital nature, the SNR and the resolutions are degraded in APS. In this paper, a new type of device called configurable QPD and its theory of operation is presented. This new device combines the analog operation of the QPD with the configurability of the APS, by means of combining photodetectors elements with analog switches in a matrix-shaped architecture. Finally, a prototype chip has been fabricated and tested and its measurements results are presented.

Position sensitive detectors (PSDs), used in high-end biotechnology, are based on optical sensors built over quadrant photodetectors and active pixel sensors. These devices are intended to measure slight movements of a laser spot. Quadrant photodetectors (QD) are, by far, the best approach in terms of resolution and noise, but require complex and expensive micropositioning machinery to perform sensor alignment with the incoming laser spot. Active pixel sensors (APS) are more versatile devices that can virtually align with the spot by means of device configuration. However, due to its intrinsic digital nature, the SNR and resolutions are degraded in APS. In this article, a new type of device called configurable quadrant photodetector (CQD) is presented. It combines the analog operation of the QD with the configurability of the APS, by means of combining photodetector elements with analog switches in a matrix-shaped architecture. A prototype has been designed, fabricated, and tested, and its electrical characterisation is presented.

The maximum data rate in today's available multidrop backplanes is significantly limited due to signal integrity concerns. In this brief, a novel gigabit multidrop serial link configuration for high-speed digital systems based on newly developed asymmetrical broadband power splitters with matching trace impedance, is presented. The proposed power splitter features good impedance match at all ports without the insertion losses being inherent to common resistive power splitters. Experimental results obtained from implemented prototypes demonstrate a satisfactory operation of the proposed multidrop serial backplane for a data rate above 3.5 Gbps.

Today's data communication systems are demanding increasing off-chip data rates. To satisfy this demand, high-speed serial links are used, saving area and power dissipation compared to highly parallel buses. However, power dissipation and noise generated by this system is still a critical issue. In this article, a novel approach using differential current mode is presented, which combines low power dissipation with low noise generated due to the reduced power transmission.

Mathematical morphology (MM) appears as a theory that can solve some drawbacks of the classical lineal image processing. Linear filters generate a spatial distortion from initial image, what gives as result that specific algorithms are usually needed for each process with a complexity that cannot be implemented in VLSI systems for real time image processing. MM overcome the inherent drawbacks of the linear processing based on the comparison of an initial image with some well-known geometric figures. In this paper we present the implementation of a specific processor that computes MM basic operations. Using a clock frequency of 250 MHz this processor is able to handle real time 512×512 pixels video images. MM allows non-linear processing of images and it is based on dilation and erosion operations using a geometric figure called structural element (SE). More complex image processing can be performed using these two basic operations. In this implementation the SE of 3×3 pixels was chosen. 0.6 μm HGaAs standard cells technology, from Vitesse Semiconductor Corporation, has been used achieving a logic level gate description with the possibility of migration to another technologies.

In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 /spl mu/m gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 /spl mu/s, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation (MAC) units, but evaluates the trigonometric functions using only add and shift operations, Improvements to the basic CORDIC architecture are introduced in order to reduce the area and power of the processor. This together with the use of pipelining and carry save adders produces a very regular and fast processor, The CORDIC units were fabricated and tested in order to anticipate the final performance of the processor. This work also demonstrates the maturity of GaAs technology for implementing ultrahigh-performance signal processors.

In recent years, IEEE 802.15.4-based Wireless Sensor Networks (WSN) have experienced significant growth, mainly motivated by the standard features, such as small size oriented devices, low power consumption nodes, wireless communication links, and sensing and data processing capabilities. In this paper, the development, implementation and deployment of a novel fully compatible IEEE 802.15.4-based WSN architecture for applications operating over extended geographic regions with high node mobility support, is described. In addition, a practical system implementation of the proposed WSN architecture is presented and described for experimental validation and characterization purposes.

In this paper, a real output queuing switch prototype implementation is presented. This implementation is based on a novel high speed multidrop backplane and a general purpose line card which includes a Virtex-II 6000 FPGA. This switch is named GMDS (Gigabit MultiDrop Switch) and its main features are the switch matrix replacement by the multidrop backplane -increasing system reliability-, variable lenght packet switching support -avoiding bandwidth efficient loss-, multiple output queuing structure for supporting QoS (Quality of Service) and a minimum speedup.

A novel variable length packet scheduling algorithm focused on real output queue reference architecture is presented in this paper. The main features of this packet scheduler development are the Quality of Service (QoS) and variable length packet support. The packet scheduler supports up to eight traffic classes which can be assigned up to two different priorities. The bandwidth assigned to any traffic class is configurable. The packet scheduler has been described and simulated in C++ language under uniform and bursty traffic conditions.

In this paper, the implementation of a 900 MHz multiphase oscillator with sinusoidal outputs in SiGe technology is presented. The circuit is based on a differential cross-coupled topology formed by four differential LC-oscillators that provide eight output signals with 45deg phase differences. The whole circuit was implemented full-custom. The final IC has an area of 1238 mum times 1238 mum and a total power consumption of 75 mW.

In this paper, the implementation of a 2.5 Gbps 1:32 deserializer in SiGe BiCMOS technology using standard cells and ECL bipolar circuits in order to minimize power consumption, is presented. The deserializer is composed of two main circuits: a demultiplexer and a clock distribution network. The architecture of the demultiplexer is based on a tree structure which allows using CMOS technology for low-speed stages. Clock signals are generated by the clock distribution network which is formed by static frequency dividers. In order to adapt both logic families, an ECL to CMOS converter was designed. High-speed ECL circuits were implemented full-custom with Cadence Virtuoso whereas standard cells were used for CMOS circuits were designed with Silicon Ensemble. Functionality has been verified through post-layout simulations performed in all technology's corner cases. The final IC has an area of 700 mum times 1045 mum and a total power consumption of 300 mW approximation

Maximum data rate in today's available multidrop backplanes is limited to 400 Mbps due to signal integrity concerns. In this paper, an experimental gigabit multidrop serial backplane for high-speed digital systems based on a novel asymmetrical broadband power splitter configuration with matching trace impedance, is presented. Experimental results obtained from constructed prototype demonstrate a satisfactory operation of the proposed multidrop serial backplane for a data transfer rate of 3 Gbps.

A multidrop backplane based on point-to-multipoint serial links enables interconnection between line cards without requiring a central switch fabric. However, maximum data rate in today's available multidrop serial links is limited to 400Mbps due to signal integrity concerns. In this paper, a novel gigabit multidrop serial link configuration for high-speed digital systems based on broadband power splitters with matching trace impedance, is proposed. Experimental results obtained from implemented prototypes demonstrate a satisfactory operation of the proposed multidrop serial backplane for a data rate of 3.5Gbps.

Classification of Internet protocol (IP) packets has become a bottleneck for the effective operation of QoS capable routers. In this paper, a novel packet classification scheme for high performance routers on different QoS architectures, named split-engine packet classification (SPC), is proposed. The key feature of the presented architecture is its ability to address a wide variety of inherently incompatible performance requirements by efficiently combining existing classification methods. To prove the validity of the proposed approach, a low cost SPC packet classifier architecture with per-flow packet treatment and dynamic resource reservation support on an OC-24 link as required by the Integrated Services framework, has been developed.

Nowadays digital networks require architectures based on standards that are implemented independently of the technology. Besides, these network specifications can easily change to include novel services. For these reasons, dominant trends are to design and verify systems at high level, prior to technology mapping. In this paper, a methodology is proposed to obtain a full verified system from an architecture specification. In order to validate this methodology, a system specification document is used as starting point. This specified system is partitioned in average size modules and then each module is described itself in design specification documents, which are the basis of their implementation using Hardware Description Languages (HDL). Each module is verified based on test specification documents generated along with the design specification. Finally, all the modules are interconnected and verified using an automatic test vector generator. Firstly, this approach introduces a method that, independently of the size of the system, improves reliability in the results, and secondly, it documents all the steps performed during the different stages. In order to validate this methodology, SDH (Synchronous Digital Hierarchy) and ATM (Asynchronous Transfer Mode) standards was chosen. Based on these standards, an ATM over SDH transceiver with add/drop functionality is studied, designed, implemented and verified. This system is described and verified using HDL and, after that, it is synthesized in FPGA devices. The obtained results show that a complex digital system has been developed guaranteeing the specifications, and, on the other hand, the optimization of the human resources and the effort of engineering. This methodology encourages the documentation process while the system is developed, easing the knowledge transfer process.

Nowadays clock recovery units are key elements in high speed digital communication systems. For an efficient operation, this units should generate a low jitter clock based on the NRZ received data, and be tolerant to long absence of transitions. Architectures based on Hogge phase detectors have been widely used, nevertheless, they are very sensitive to jitter of the received data and they have a limited tolerance to the absence of transitions. This paper shows a novel high speed clock recovery unit based on a phase aligner. The system allows a very fast clock recovery with a low jitter, moreover, it is very resistant to absence of transitions. The design is based on eight phases obtained from a reference clock running at the nominal frequency of the received signal. This high speed reference clock is generated using a crystal and a clock multiplier unit. The phase alignment system chooses, as starting point, the two phases closest to the data phase. This allows a maximum error of 45 degrees between the clock and data signal phases. Furthermore, the system includes a feed-back loop that interpolates the chosen phases to reduce the phase error to zero. Due to the high stability and reduced tolerance of the local reference clock, the jitter obtained is highly reduced and the system becomes able to operate under long absence of transitions. This performances make this design suitable for systems such as high speed serial link technologies. This system has been designed for CMOS 0.25μm at 1.25GHz and has been verified through HSpice simulations.

In this paper we present the design of a 2D discrete cosine transform (2D-DCT) processor and its implementation using 0.6 /spl mu/m GaAs technology. The architecture of the processor, that resembles an FCT-MMM (fast cosine transform-matrix matrix multiplication) architecture, was development using distributed arithmetic (DA) in order to reduce the area required. The processor has about 50k transistors and occupies an area of 31.8 mm/sup 2/. It is able to process 400 Mpixels per second and at a clock frequency of 600 MHz, which is far beyond the requirements for real time high definition moving pictures in the MPEG-2 standard. Special consideration is given to the implementation of a transposition RAM which constitutes the bottleneck of the algorithm. A 64 word/spl times/12 bit, 1 ns access time transposition RAM was developed using a new dynamic RAM cell.

Mathematical Morphology appears as a theory that can solve some drawbacks of the classical lineal image processing. Linear filters generate a spatial distortion from initial image, what gives as a result that specific algorithms are usually needed for each process with a complexity that can not be implemented in VLSI systems for Real Time Image Processing. Mathematical Morphology is an alternative method to overcome the inherent drawbacks of the linear processing based on the comparison of an initial image with some well known geometric figures. In this paper we present the implementation of a specific processor that computes Mathematical Morphology (MM) basic operations. Using a clock frequency of 250 MHz this processor is able to handle real time 512x512 pixels video images. Mathematical Morphology allows the nonlinear processing of images and it is based on Dilation and Erosion operations using a geometric figure called Structural Elements (SE). More complex image processing can be performed using these basic operations. In this implementation the structural element of 3x3 pixels was chosen. 0.6micrometers HgaAsIV standard cells technology, from Vitesse Semiconductor Corporation, has been used achieving a logic level gate description with the possibility of migration to another technologies.

This article describes an ATM transceiver implementation with add/drop function over Synchronous Digital Hierarchy (SDH) able to handle STM-16c (OC-48c) signals. The design has been developed using Vitesse HGaAs-IV technology using Direct Coupled FET Logic (DCFL) standard cells and obtaining, in this way, a logic gate level description which could be easily exportable to any technology.

Today's increasing data rates in digital communication circuits are demanding higher speeds in the interchip communication. This throughput can be achieved using high rate serial links. Good noise inmunity can be obtained by means of differential strategies and an important power reduction can be obtained by using current mode operation. In this paper, a innovative differential current mode transmitter/receiver pair is presented which combines both, good noise inmunity with low power dissipation.

The parallelization of numerical algorithms is very important in scientific applications, but many points of this parallelization remain open today. Specifically, the overhead introduced by loading and unloading the data degrades the efficiency, and in a realistic approach should be taking into account for performance estimation. The authors of this paper present a way of overcoming the bottleneck of loading and unloading the data by overlapping computations and communications in a specific algorithm such as matrix-vector multiplication. Also, a way of mapping this algorithm in hardware is presented in order to demonstrate the parallelization methodology.

Scheduling algorithms developed for virtual-output-queuing (VOQ) switches have focused on the throughput enhancement, rather than provide QoS guarantees for different priority levels. Presented, is a new scheduling scheme to effectively support real-time and data applications in VOQ switches with negligible complexity increment.

Virtual output queue (VOQ) is an efficient architecture for high-speed switches because it combines the low cost of input-queuing with high performance of output-queuing. The achievable throughput and delay performance heavily depends on the scheduling algorithm used to resolve the contention for the same output ports in each cell slot. Most VOQ scheduling algorithms, as exemplified by PIM and iSLIP, re based on parallel and iterative request-grant-accept arbitration schemes. Conventional performance evaluation of these scheduling algorithms, does not consider the effect of some issues inherent to their implementation on a modular and scalable VOQ switch with input ports and switch matrix residing on separate cards. One of the main issues is the Round-Trip Delay (RTD), defined as the latency between a connection is requested to the switch matrix card and the associated acceptance notification is received on the input port card. In this paper, the effect of RTD on performance parameters for PIM and iSLIP algorithms is presented, not being considered in deep in previous works appearing In the literature. Based on simulation results, RTD is demonstrated to affect significantly contention on output ports and mean queuing delay, and thus degrade the performance of cell-based VOQ switches.

This paper reports on work done by project GARDEN under EU ESPRIT Research Programme in the past three years for developing ATM line units and ATM switch fabric operating at 2.5 Gb/s, and ongoing work for system upgrading to 10 Gb/s operation. A circuit of each type of unit is presented. This project has required the detailed specification of the system architecture, partitioning, interconnection, and technology mapping of the ATM functions into different chips, the development of full custom layout methodology and tools for MESFET HGaAs III, IV and HEMT technologies, and the actual design, fabrication and test of a set of IC's performing physical layer, ATM layer, buffering and switching functions.