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High-speed clock recovery unit based on a phase aligner
- Source :
- SPIE Proceedings.
- Publication Year :
- 2003
- Publisher :
- SPIE, 2003.
-
Abstract
- Nowadays clock recovery units are key elements in high speed digital communication systems. For an efficient operation, this units should generate a low jitter clock based on the NRZ received data, and be tolerant to long absence of transitions. Architectures based on Hogge phase detectors have been widely used, nevertheless, they are very sensitive to jitter of the received data and they have a limited tolerance to the absence of transitions. This paper shows a novel high speed clock recovery unit based on a phase aligner. The system allows a very fast clock recovery with a low jitter, moreover, it is very resistant to absence of transitions. The design is based on eight phases obtained from a reference clock running at the nominal frequency of the received signal. This high speed reference clock is generated using a crystal and a clock multiplier unit. The phase alignment system chooses, as starting point, the two phases closest to the data phase. This allows a maximum error of 45 degrees between the clock and data signal phases. Furthermore, the system includes a feed-back loop that interpolates the chosen phases to reduce the phase error to zero. Due to the high stability and reduced tolerance of the local reference clock, the jitter obtained is highly reduced and the system becomes able to operate under long absence of transitions. This performances make this design suitable for systems such as high speed serial link technologies. This system has been designed for CMOS 0.25μm at 1.25GHz and has been verified through HSpice simulations.
- Subjects :
- Synchronous circuit
Data strobe encoding
Serial communication
Clock signal
Computer science
Underclocking
Circuit design
Clock rate
Clock drift
Clock gating
Integrated circuit
Phase detector
Clock synchronization
law.invention
law
Clock domain crossing
Electronic engineering
Waveform
Clock recovery
Jitter
business.industry
Digital clock manager
Clock skew
Timing failure
Phase-locked loop
Clock angle problem
CMOS
Embedded system
Self-clocking signal
business
CPU multiplier
Data transmission
Subjects
Details
- ISSN :
- 0277786X
- Database :
- OpenAIRE
- Journal :
- SPIE Proceedings
- Accession number :
- edsair.doi...........e84d8ece14e47f361a3f80cd0825ffbc