1. Fast FPGA prototyping for real-time image processing with very high-level synthesis
- Author
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Yanjing Bi, Chao Li, Fan Yang, Franck Marzani, Laboratoire d'Electronique, d'Informatique et d'Image [EA 7508] (Le2i), Université de Technologie de Belfort-Montbeliard (UTBM)-Université de Bourgogne (UB)-École Nationale Supérieure d'Arts et Métiers (ENSAM), Arts et Métiers Sciences et Technologies, HESAM Université (HESAM)-HESAM Université (HESAM)-Arts et Métiers Sciences et Technologies, HESAM Université (HESAM)-HESAM Université (HESAM)-AgroSup Dijon - Institut National Supérieur des Sciences Agronomiques, de l'Alimentation et de l'Environnement-Centre National de la Recherche Scientifique (CNRS), Université Bourgogne Franche-Comté [COMUE] (UBFC), Equipe CORES [ImViA - EA7535] (CORES), Imagerie et Vision Artificielle [Dijon] (ImViA), Université de Bourgogne (UB)-Université de Bourgogne (UB), China Scholarship Council, and Région Bourgogne-Franche-Comte
- Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR] ,Register transfer language ,business.industry ,Computer science ,020207 software engineering ,Image processing ,02 engineering and technology ,Abstraction layer ,Embedded system ,High-level synthesis ,Digital image processing ,0202 electrical engineering, electronic engineering, information engineering ,020201 artificial intelligence & image processing ,business ,Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION ,ComputingMilieux_MISCELLANEOUS ,Digital signal processing ,Information Systems ,FPGA prototype ,Register-transfer level - Abstract
Programming in high abstraction level can facilitate the development of digital signal processing systems. In the recent 20 years, high-level synthesis (HLS) has made significantly progress. This technique greatly benefits the R&D productivity of the Field Programmable Gate Array (FPGA) developments and helps for adding to the maintainability of the products by automating the C-to-RTL (register transfer language) conversion. However, due to the high complexity and computational intensity, image processing algorithms usually necessitate a higher abstraction environment than C-synthesis, and the current HLS tools do not have the ability of this kind. This paper presents a conception of very high-level synthesis method which allows fast prototyping and verifying the FPGA-based image processing designs in the MATLAB environment. We build a heterogeneous development flow by using currently available tool kits for verifying the proposed approach and evaluated it within two real-life applications. Experiment results demonstrate that it can effectively reduce the complexity of the development by automatically synthesizing the algorithm behavior from the user level into the low register transfer level and give play to the advantages of FPGA related to the other devices.
- Published
- 2017
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